[ARM Disassembler] Flawed display of ALU instructions with a shift-rotate by r0

[lunasorcery]

Observed at 0.10.4 (6c2da7b)

ARM-mode ALU instructions with a shift-rotate by r0 will mistakenly render as rrx, the special-case for rotate-by-immediate-zero.

Given the following assembly:

mov r2, r3, rrx      ; opcode E1A02063
mov r2, r3, ror #1   ; opcode E1A020E3
mov r2, r3, ror r0   ; opcode E1A02073
mov r2, r3, ror r1   ; opcode E1A02173

mGBA will disassemble as:

mov r2, r3, rrx
mov r2, r3, ror #1
mov r2, r3, rrx
mov r2, r3, ror r1