cm.yaml

---
name: CM
brief: Clock Management
size: 0x1000
desc: |
  The BCM2835 system has a number of clocks for the various components which are
  driven either by a PLL or the external 19.2 MHz oscillator. Known clocks are
  the core clock (CM_VPU), the system timer clock (PM_TIME) which controls the
  speed of the system timer and the GPIO clocks which are documented in the
  Raspberry Pi peripheral documentation. The interactions between the clocks are
  mostly unknown. The core clock affects at least execution speed on the
  videocore processor and the speed of the mini uart.
arrays:
  0x8:
    name: VPU
    length: 1
    stride: 0x8
    block: &CLOCK_CTL
      brief: Clocks Control
      size: 0x8
      desc: >
        Registers to control clock generation
      registers:
        0x0:
          name: CTL
          brief: Clock Control
          type: CTL

        0x4:
          name: DIV
          brief: Clock Divisor
          type: DIV
  0x28:
    name: H264
    length: 1
    block: *CLOCK_CTL
  0x30:
    name: UNK_0x30
    length: 1
    block: *CLOCK_CTL
  0x38:
    name: V3D
    length: 1
    block: *CLOCK_CTL
  0x40:
    name: CAM0_LP
    length: 1
    block: *CLOCK_CTL
  0x58:
    name: DSI0_ESC/DSI1_ESC
    length: 1
    block: *CLOCK_CTL
  0x68:
    name: DPI
    length: 1
    block: *CLOCK_CTL
  0x70:
    name: GP${n}
    length: 3
    stride: 0x8
    block: *CLOCK_CTL
  0x88:
    name: HSM
    length: 1
    block: *CLOCK_CTL
  0x90:
    name: ISP
    length: 1
    block: *CLOCK_CTL
  0x98:
    name: PCM
    length: 1
    block: *CLOCK_CTL
  0xa0:
    name: PWM
    length: 1
    block: *CLOCK_CTL
  0xa8:
    name: SLIM
    length: 1
    block: *CLOCK_CTL
  0xb0:
    name: SMI
    length: 1
    stride: 0x8
    block: *CLOCK_CTL
  0xc0:
    name: eMMC
    length: 1
    block: *CLOCK_CTL
  0xe0:
    name: TSENS
    length: 1
    block: *CLOCK_CTL
  0xe8:
    name: TIME
    length: 1
    block: *CLOCK_CTL
  0xf0:
    name: UART
    length: 1
    block: *CLOCK_CTL
  0xf8:
    name: VEC
    length: 1
    block: *CLOCK_CTL
  0x190:
    name: UNK_0x190
    length: 1
    block: *CLOCK_CTL
#   0x1a8:
#     name: UNK_0x1a8
#     length: 1
#     stride: 0x8
#     block: *CLOCK_CTL
  0x1b0:
    name: ARM
    length: 1
    block: *CLOCK_CTL
  0x1c0:
    name: UNK_0x1c0
    length: 1
    block: *CLOCK_CTL

types:
  CTL:
    name: CTL
    brief: Clock Control Registers
    access: rw
    bits:
      31-24: &PASSWD_FIELD
        name: PASSWD
        access: w
        values:
          0x5a:
            name: PASSWD
      10-9:
        name: MASH
      8:
        name: FLIP
      7:
        name: BUSY
      5:
        name: KILL
      3-0:
        name: SRC
        access: rw
        values:
          0:
            name: GND
          1:
            name: OSC
            desc: External oscillator
          4:
            name: PLLA
          5:
            name: PLLC
          6:
            name: PLLD
          7:
            name: HDMI
  DIV:
    name: DIV
    brief: Clock Divisor Registers
    desc: |
      The resulting clock is the source divided by (DIVI + DIVF / 1024).
    access: rw
    bits:
      31-24: *PASSWD_FIELD
      23-12:
        name: DIVI
        desc: Integer part
      11-0:
        name: DIVF
        desc: Fractional part