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An open-source static random access memory (SRAM) compiler.
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Python 3.5 License: BSD 3-clause

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An open-source static random access memory (SRAM) compiler.

What is OpenRAM?

OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.


Please take a look at our presentation We have created a detailed presentation that serves as our documentation. This is the most up-to-date information, so please let us know if you see things that need to be fixed.

Basic Setup

Docker Image

We have a pre-configured Ubuntu Docker image available that has all tools installed for the SCMOS process. It is available at docker hub. Please see our for information on how to use this docker image.


The OpenRAM compiler has very few dependencies:

  • Ngspice 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
  • Python 3.5 or higher
  • Python numpy (pip3 install numpy to install)
  • Python scipy (pip3 install scipy to install)

If you want to perform DRC and LVS, you will need either:

You must set two environment variables:

  • OPENRAM_HOME should point to the compiler source directory.
  • OPENERAM_TECH should point to a root technology directory.


For example add this to your .bashrc:

  export OPENRAM_HOME="$HOME/openram/compiler"
  export OPENRAM_TECH="$HOME/openram/technology"

You may also wish to add OPENRAM_HOME to your PYTHONPATH:


We include the tech files necessary for SCMOS SCN4M_SUBM. The SCMOS spice models, however, are generic and should be replaced with foundry models. If you are using FreePDK45, you should also have that set up and have the environment variable point to the PDK. For example add this to your .bashrc:

  export FREEPDK45="/bsoe/software/design-kits/FreePDK45"

You may get the entire FreePDK45 PDK here. If you are using SCMOS, you should install Magic and Netgen. We have included the most recent SCN4M_SUBM design rules from Qflow.

Basic Usage

Once you have defined the environment, you can run OpenRAM from the command line using a single configuration file written in Python.

For example, create a file called specifying the following parameters for your memory:

# Data word size
word_size = 2
# Number of words in the memory
num_words = 16

# Technology to use in $OPENRAM_TECH
tech_name = "scn4m_subm"
# Process corners to characterize
process_corners = ["TT"]
# Voltage corners to characterize
supply_voltages = [ 3.3 ]
# Temperature corners to characterize
temperatures = [ 25 ]

# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False

# To force this to use magic and netgen for DRC/LVS/PEX
# Could be calibre for FreePDK45
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"

You can then run OpenRAM by executing:

python3 $OPENRAM_HOME/ myconfig

You can see all of the options for the configuration file in $OPENRAM_HOME/

Unit Tests

Regression testing performs a number of tests for all modules in OpenRAM. From the unit test directory ($OPENRAM_HOME/tests), use the following command to run all regression tests:


To run a specific test:

   python3 {unit test}.py 

The unit tests take the same arguments as itself.

To increase the verbosity of the test, add one (or more) -v options:

   python3 tests/ -v -t freepdk45

To specify a particular technology use "-t " such as "-t freepdk45". The default for a unit test is scn4m_subm. The default for is specified in the configuration file.

Porting to a New Technology

If you want to support a enw technology, you will need to create:

  • a setup script for each technology you want to use
  • a technology directory for each technology with the base cells

We provide two technology examples for SCMOS and FreePDK45. Each specific technology (e.g., FreePDK45) should be a subdirectory (e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files:

  • gds_lib folder with all the .gds (premade) library cells:
    • dff.gds
    • sense_amp.gds
    • write_driver.gds
    • cell_6t.gds
    • replica_cell_6t.gds
    • dummy_cell_6t.gds
  • sp_lib folder with all the .sp (premade) library netlists for the above cells.
  • A valid tech Python module (tech directory with and with:
    • References in to spice models
    • DRC/LVS rules needed for dynamic cells and routing
    • Layer information
    • Spice and supply information
    • etc.

Get Involved

Further Help


OpenRAM is licensed under the BSD 3-clause License.

Contributors & Acknowledgment

  • Matthew Guthaus from VLSIDA created the OpenRAM project and is the lead architect.
  • James Stine from VLSIARCH co-founded the project.
  • Hunter Nichols maintains and updates the timing characterization.
  • Michael Grimes created and maintains the multiport netlist code.
  • Jennifer Sowash is creating the OpenRAM IP library.
  • Jesse Cirimelli-Low created the datasheet generation.
  • Samira Ataei created early multi-bank layouts and control logic.
  • Bin Wu created early parameterized cells.
  • Yusu Wang is porting parameterized cells to new technologies.
  • Brian Chen created early prototypes of the timing characterizer.
  • Jeff Butera created early prototypes of the bank layout.

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