From b43330053858ea5add7078d974d4a19516180294 Mon Sep 17 00:00:00 2001 From: mibodhi Date: Wed, 8 Nov 2017 19:45:33 -0800 Subject: [PATCH] Rebase to 2017.07 --- README.u-boot-kirkwood | 81 +++ arch/arm/include/asm/mach-types.h | 49 ++ arch/arm/mach-kirkwood/Kconfig | 31 ++ arch/arm/mach-kirkwood/cpu.c | 14 + arch/arm/mach-kirkwood/include/mach/config.h | 9 + .../mach-kirkwood/include/mach/kw88f6192.h | 2 +- arch/arm/mach-kirkwood/include/mach/mpp.h | 2 + arch/arm/mach-mvebu/include/mach/soc.h | 2 + board/Marvell/dreamplug/dreamplug.h | 16 +- board/Marvell/netgear_ms2110/Kconfig | 12 + board/Marvell/netgear_ms2110/MAINTAINERS | 6 + board/Marvell/netgear_ms2110/Makefile | 13 + board/Marvell/netgear_ms2110/kwbimage.cfg | 167 ++++++ board/Marvell/netgear_ms2110/netgear_ms2110.c | 151 ++++++ board/Marvell/netgear_ms2110/netgear_ms2110.h | 41 ++ board/Marvell/sheevaplug/kwbimage.cfg | 5 +- board/Seagate/goflexhome/goflexhome.c | 1 + board/Seagate/goflexhome/kwbimage.cfg | 1 + board/Seagate/goflexnet/Kconfig | 12 + board/Seagate/goflexnet/MAINTAINERS | 6 + board/Seagate/goflexnet/Makefile | 12 + board/Seagate/goflexnet/goflexnet.c | 184 +++++++ board/Seagate/goflexnet/goflexnet.h | 44 ++ board/Seagate/goflexnet/kwbimage.cfg | 165 ++++++ board/cloudengines/pogo_e02/pogo_e02.c | 34 ++ board/cloudengines/pogo_v4/Kconfig | 12 + board/cloudengines/pogo_v4/MAINTAINERS | 6 + board/cloudengines/pogo_v4/Makefile | 11 + board/cloudengines/pogo_v4/kwbimage.cfg | 167 ++++++ board/cloudengines/pogo_v4/pogo_v4.c | 210 ++++++++ board/cloudengines/pogo_v4/pogo_v4.h | 50 ++ board/hp/t5325/Kconfig | 16 + board/hp/t5325/MAINTAINERS | 6 + board/hp/t5325/Makefile | 11 + board/hp/t5325/kwbimage.cfg | 149 ++++++ board/hp/t5325/t5325.c | 175 +++++++ board/hp/t5325/t5325.h | 37 ++ board/iomega/iconnect/iconnect.c | 31 ++ board/zyxel/nsa310/Kconfig | 12 + board/zyxel/nsa310/MAINTAINERS | 6 + board/zyxel/nsa310/Makefile | 12 + board/zyxel/nsa310/kwbimage.cfg | 166 ++++++ board/zyxel/nsa310/nsa310.c | 196 +++++++ board/zyxel/nsa310/nsa310.h | 56 ++ board/zyxel/nsa310s/Kconfig | 4 +- board/zyxel/nsa310s/MAINTAINERS | 4 +- board/zyxel/nsa310s/Makefile | 4 +- board/zyxel/nsa310s/kwbimage.cfg | 4 +- board/zyxel/nsa310s/nsa310s.c | 186 +++++-- board/zyxel/nsa310s/nsa310s.h | 32 +- board/zyxel/nsa320/Kconfig | 12 + board/zyxel/nsa320/MAINTAINERS | 6 + board/zyxel/nsa320/Makefile | 14 + board/zyxel/nsa320/kwbimage.cfg | 164 ++++++ board/zyxel/nsa320/nsa320.c | 224 ++++++++ board/zyxel/nsa320/nsa320.h | 69 +++ board/zyxel/nsa325/Kconfig | 12 + board/zyxel/nsa325/MAINTAINERS | 6 + board/zyxel/nsa325/Makefile | 13 + board/zyxel/nsa325/kwbimage.cfg | 77 +++ board/zyxel/nsa325/nsa325.c | 269 ++++++++++ board/zyxel/nsa325/nsa325.h | 77 +++ cmd/jffs2.c | 11 +- cmd/mmc.c | 3 + cmd/usb.c | 5 +- common/board_r.c | 4 +- common/bootm.c | 8 + common/usb.c | 9 +- common/usb_storage.c | 106 +++- configs/dockstar_defconfig | 18 +- configs/dreamplug_defconfig | 20 +- configs/goflexhome_defconfig | 12 +- configs/goflexnet_defconfig | 38 ++ configs/iconnect_defconfig | 18 +- configs/netgear_ms2110_defconfig | 35 ++ configs/nsa310_defconfig | 36 ++ configs/nsa310s_defconfig | 18 +- configs/nsa320_defconfig | 35 ++ configs/nsa325_defconfig | 36 ++ configs/pogo_e02_defconfig | 14 +- configs/pogo_v4_defconfig | 35 ++ configs/sheevaplug_defconfig | 15 +- configs/t5325_defconfig | 46 ++ drivers/gpio/kw_gpio.c | 47 +- drivers/mmc/kirkwood_mmc.c | 480 ++++++++++++++++++ drivers/net/netconsole.c | 6 +- drivers/usb/host/ehci-hcd.c | 30 +- drivers/usb/host/xhci.c | 8 +- drivers/usb/host/xhci.h | 4 +- include/configs/dockstar.h | 85 +++- include/configs/dreamplug.h | 110 +++- include/configs/goflexhome.h | 83 ++- include/configs/goflexnet.h | 173 +++++++ include/configs/iconnect.h | 88 +++- include/configs/mv-common.h | 6 + include/configs/netgear_ms2110.h | 210 ++++++++ include/configs/nsa310.h | 181 +++++++ include/configs/nsa310s.h | 174 +++++-- include/configs/nsa320.h | 178 +++++++ include/configs/nsa325.h | 181 +++++++ include/configs/pogo_e02.h | 80 ++- include/configs/pogo_v4.h | 184 +++++++ include/configs/sheevaplug.h | 116 +++-- include/configs/t5325.h | 155 ++++++ include/kirkwood_mmc.h | 268 ++++++++++ include/usb.h | 1 + include/usb_defs.h | 1 + 107 files changed, 6639 insertions(+), 298 deletions(-) create mode 100644 README.u-boot-kirkwood create mode 100644 board/Marvell/netgear_ms2110/Kconfig create mode 100644 board/Marvell/netgear_ms2110/MAINTAINERS create mode 100644 board/Marvell/netgear_ms2110/Makefile create mode 100644 board/Marvell/netgear_ms2110/kwbimage.cfg create mode 100644 board/Marvell/netgear_ms2110/netgear_ms2110.c create mode 100644 board/Marvell/netgear_ms2110/netgear_ms2110.h create mode 100644 board/Seagate/goflexnet/Kconfig create mode 100644 board/Seagate/goflexnet/MAINTAINERS create mode 100644 board/Seagate/goflexnet/Makefile create mode 100644 board/Seagate/goflexnet/goflexnet.c create mode 100644 board/Seagate/goflexnet/goflexnet.h create mode 100644 board/Seagate/goflexnet/kwbimage.cfg create mode 100644 board/cloudengines/pogo_v4/Kconfig create mode 100644 board/cloudengines/pogo_v4/MAINTAINERS create mode 100644 board/cloudengines/pogo_v4/Makefile create mode 100644 board/cloudengines/pogo_v4/kwbimage.cfg create mode 100644 board/cloudengines/pogo_v4/pogo_v4.c create mode 100644 board/cloudengines/pogo_v4/pogo_v4.h create mode 100644 board/hp/t5325/Kconfig create mode 100644 board/hp/t5325/MAINTAINERS create mode 100644 board/hp/t5325/Makefile create mode 100644 board/hp/t5325/kwbimage.cfg create mode 100644 board/hp/t5325/t5325.c create mode 100644 board/hp/t5325/t5325.h create mode 100644 board/zyxel/nsa310/Kconfig create mode 100644 board/zyxel/nsa310/MAINTAINERS create mode 100644 board/zyxel/nsa310/Makefile create mode 100644 board/zyxel/nsa310/kwbimage.cfg create mode 100644 board/zyxel/nsa310/nsa310.c create mode 100644 board/zyxel/nsa310/nsa310.h create mode 100644 board/zyxel/nsa320/Kconfig create mode 100644 board/zyxel/nsa320/MAINTAINERS create mode 100644 board/zyxel/nsa320/Makefile create mode 100644 board/zyxel/nsa320/kwbimage.cfg create mode 100644 board/zyxel/nsa320/nsa320.c create mode 100644 board/zyxel/nsa320/nsa320.h create mode 100644 board/zyxel/nsa325/Kconfig create mode 100644 board/zyxel/nsa325/MAINTAINERS create mode 100644 board/zyxel/nsa325/Makefile create mode 100644 board/zyxel/nsa325/kwbimage.cfg create mode 100644 board/zyxel/nsa325/nsa325.c create mode 100644 board/zyxel/nsa325/nsa325.h create mode 100644 configs/goflexnet_defconfig create mode 100644 configs/netgear_ms2110_defconfig create mode 100644 configs/nsa310_defconfig create mode 100644 configs/nsa320_defconfig create mode 100644 configs/nsa325_defconfig create mode 100644 configs/pogo_v4_defconfig create mode 100644 configs/t5325_defconfig create mode 100644 drivers/mmc/kirkwood_mmc.c create mode 100644 include/configs/goflexnet.h create mode 100644 include/configs/netgear_ms2110.h create mode 100644 include/configs/nsa310.h create mode 100644 include/configs/nsa320.h create mode 100644 include/configs/nsa325.h create mode 100644 include/configs/pogo_v4.h create mode 100644 include/configs/t5325.h create mode 100644 include/kirkwood_mmc.h diff --git a/README.u-boot-kirkwood b/README.u-boot-kirkwood new file mode 100644 index 0000000000..a558b7d9bb --- /dev/null +++ b/README.u-boot-kirkwood @@ -0,0 +1,81 @@ +Current version branch 2017.07-kirkwood-tld-1 + +Supports the following Kirkwood devices: + +GoFlexNet, GoFlexHome, PogoE02, Dockstar, iConnect, NetgearStora, PogoV4/Mobile, Sheevaplug, NSA325, NSA320, NSA310S/320S, NSA310, HP T5325, Dreamplug. + +For u-boot images: + +http://forum.doozan.com/read.php?3,12381 + +============================================== + +Change log (chronological order): + +-------- + +Removed EXTRAVERSION from IDENT string in Kirkwood headers +Added Netgear Stora + +-------- + +Add new U-Boot env: usb_ready_retry + +This env allows users to select how long U-Boot will retry in testing the USB drive readiness. +To enable the feature, set this env either in Linux or U-Boot. +The period could be any unsigned integer, so increase the period as needed to a +number where you are comfortable that the USB drive is working, and add a few seconds to be sure. + +-------- + +Forwarding to 2014.01 U-Boot +Merge branch '2013.10-kirkwood' into 2014.01-kirkwood + +-------- + +Forwarding to 2014.07 U-Boot +Merge branch '2014.01-kirkwood' into 2014.07-kirkwood +New tag v2014.07-kirkwood. + +Completed pogo_v4, now supports USB, MMC, SATA +Add LED boot sequences for boxes that did not have this code +Add various features missing in some boxes +Add bootz + +-------- + +Added NSA325 and NSA320 u-boots (modified and manually patched with u-boot code from https://github.com/WarheadsSE/u-boot-kirkwood) +Add uEnv.txt loading capability (u-boot command load) +Modified jffs2 file load and list command names due to name conflicts (fsls, fsload) +Add new default envs in all supported u-boot to load uEnv.txt and also default booting to USB +Various editorial changes + + +----------- + +Added NSA310S and NSA310 u-boots +Modified NSA3xx u-boots to activate the Ethernet PHY + +----------- + +Forwarding to 2015.10 U-Boot + +----------- +version 2015.10-kirkwood-tld-2 + +Added HP Thin Client T5325 u-boot +Added buttons capability to all boxes that have buttons +Activated 2nd SATA for NSA310S/320S u-boot +Activated SATA and other functionalities for Sheevaplug u-boot + +----------- +version 2016.05-kirkwood-tld-1 + +Rebase to 2016.05 mainline + +----------- +version 2017.07-kirkwood-tld-1 + +- Rebase to 2017.07 mainline +- Incorporated patch to fix "EHCI timed out on TD" error with USB drives. + diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 9f82efe007..c83ff61c1c 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -5058,3 +5058,52 @@ #define MACH_TYPE_TOMATO 5113 #define MACH_TYPE_OMAP3_MRC3D 5114 #endif + +#ifdef CONFIG_MACH_NSA310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSA310 +# endif +# define machine_is_nsa310() (machine_arch_type == MACH_TYPE_NSA310) +#else +# define machine_is_nsa310() (0) +#endif + +#ifdef CONFIG_MACH_NSA320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSA320 +# endif +# define machine_is_nsa320() (machine_arch_type == MACH_TYPE_NSA320) +#else +# define machine_is_nsa320() (0) +#endif + +#ifdef CONFIG_MACH_NSA325 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSA325 +# endif +# define machine_is_nsa325() (machine_arch_type == MACH_TYPE_NSA325) +#else +# define machine_is_nsa325() (0) +#endif + +#ifdef CONFIG_MACH_NSA310S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSA310S +# endif +# define machine_is_nsa310s() (machine_arch_type == MACH_TYPE_NSA310S) +#else +# define machine_is_nsa310s() (0) +#endif + diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 2dd107a8b3..9420c5ad49 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -59,6 +59,30 @@ config TARGET_NAS220 config TARGET_NSA310S bool "Zyxel NSA310S" +config TARGET_GOFLEXNET + bool "GoFlex Net Board" + +config TARGET_POGO_V4 + bool "Pogoplug V4 Board" + +config TARGET_NSA325 + bool "Zyxel NSA325 Board" + +config TARGET_NSA310S + bool "Zyxel NSA310S NSA320S Board" + +config TARGET_NSA320 + bool "Zyxel NSA320 Board" + +config TARGET_NSA310 + bool "Zyxel NSA310 Board" + +config TARGET_NETGEAR_MS2110 + bool "Netgear MS2110 Board" + +config TARGET_T5325 + bool "HP T5325 Board" + endchoice config SYS_SOC @@ -81,5 +105,12 @@ source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" +source "board/Seagate/goflexnet/Kconfig" +source "board/cloudengines/pogo_v4/Kconfig" +source "board/zyxel/nsa325/Kconfig" +source "board/zyxel/nsa320/Kconfig" +source "board/zyxel/nsa310/Kconfig" +source "board/Marvell/netgear_ms2110/Kconfig" +source "board/hp/t5325/Kconfig" endif diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 4c9d3fde47..0968622b90 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -183,6 +183,20 @@ int print_cpuinfo(void) { char *rev = "??"; u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; + +#ifndef CONFIG_KW88F6192 + devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; +#else + /* Temporary hack until we have a proper way to id the SoC + * KW88F6192 and KW88F6702 is not correctly determined, so force correct SoC. + * Note that this is just for displaying purpose during U-Boot initialization */ + devid = 0x6192; +#ifdef CONFIG_KW88F6702 + devid = 0x6702; +#endif + +#endif + u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index ba6007186e..2c954fe5d1 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -77,6 +77,7 @@ * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET +#define CONFIG_FEATURE_COMMAND_EDITING #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_MII /* expose smi ove miiphy interface */ #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ @@ -110,6 +111,7 @@ #define CONFIG_SYS_ATA_STRIDE 4 /* Controller supports 48-bits LBA addressing */ #define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA /* CONFIG_IDE requires some #defines for ATA registers */ #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_IDE_MAXDEVICE 2 @@ -134,4 +136,11 @@ #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK +/* + * GPIO + */ +#define CONFIG_CMD_GPIO +#define CONFIG_KIRKWOOD_GPIO + + #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h index de220d57d4..6d5a61df08 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h @@ -16,6 +16,6 @@ #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CONFIG_SYS_TCLK 166666667 /* 166MHz */ #endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h index 7c8f6eba97..0956f3ffdc 100644 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h @@ -217,10 +217,12 @@ #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP33_SATA1_ACTn MPP( 33, 0x5, 0, 1, 0, 1, 1, 1 ) #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 1, 1, 1 ) #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0900e4008c..bee4e9b4a8 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -18,6 +18,8 @@ #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 #define SOC_88F6828_ID 0x6828 +#define SOC_88F6192_ID 0x6192 +#define SOC_88F6702_ID 0x6702 /* A375 revisions */ #define MV_88F67XX_A0_ID 0x3 diff --git a/board/Marvell/dreamplug/dreamplug.h b/board/Marvell/dreamplug/dreamplug.h index 18ea41cba7..d720c5d5aa 100644 --- a/board/Marvell/dreamplug/dreamplug.h +++ b/board/Marvell/dreamplug/dreamplug.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2017 bodhi + * + * Based on: * (C) Copyright 2011 * Jason Cooper * @@ -12,10 +15,19 @@ #ifndef __DREAMPLUG_H #define __DREAMPLUG_H +#define BLUETOOTH_BLUE_LED (1 << 15) +#define WIFI_GREEN_LED (1 << 16) +#define WIFIAP_GREEN_LED (1 << 17) + #define DREAMPLUG_OE_LOW (~(0)) -#define DREAMPLUG_OE_HIGH (~(0)) #define DREAMPLUG_OE_VAL_LOW 0 -#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */ + +/* #define DREAMPLUG_OE_HIGH (~(0)) */ +/* #define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /4 LED Pins high */ + +#define DREAMPLUG_OE_HIGH ((BLUETOOTH_BLUE_LED | WIFI_GREEN_LED | WIFIAP_GREEN_LED)) +#define DREAMPLUG_OE_VAL_HIGH (~(BLUETOOTH_BLUE_LED | WIFI_GREEN_LED | WIFIAP_GREEN_LED)) + /* PHY related */ #define MV88E1116_MAC_CTRL2_REG 21 diff --git a/board/Marvell/netgear_ms2110/Kconfig b/board/Marvell/netgear_ms2110/Kconfig new file mode 100644 index 0000000000..2d32f8bc40 --- /dev/null +++ b/board/Marvell/netgear_ms2110/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NETGEAR_MS2110 + +config SYS_BOARD + default "netgear_ms2110" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "netgear_ms2110" + +endif diff --git a/board/Marvell/netgear_ms2110/MAINTAINERS b/board/Marvell/netgear_ms2110/MAINTAINERS new file mode 100644 index 0000000000..5f96d15001 --- /dev/null +++ b/board/Marvell/netgear_ms2110/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR_MS2110 BOARD +M: bodhi +S: Maintained +F: board/Marvell/netgear_ms2110 +F: include/configs/netgear_ms2110.h +F: configs/netgear_ms2110_defconfig diff --git a/board/Marvell/netgear_ms2110/Makefile b/board/Marvell/netgear_ms2110/Makefile new file mode 100644 index 0000000000..e8b31046ac --- /dev/null +++ b/board/Marvell/netgear_ms2110/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2014 bodhi +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := netgear_ms2110.o + diff --git a/board/Marvell/netgear_ms2110/kwbimage.cfg b/board/Marvell/netgear_ms2110/kwbimage.cfg new file mode 100644 index 0000000000..877aa37df5 --- /dev/null +++ b/board/Marvell/netgear_ms2110/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000833 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000099 # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x03FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x04000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x03FFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Marvell/netgear_ms2110/netgear_ms2110.c b/board/Marvell/netgear_ms2110/netgear_ms2110.c new file mode 100644 index 0000000000..750f8781d2 --- /dev/null +++ b/board/Marvell/netgear_ms2110/netgear_ms2110.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2014-2017 bodhi + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "netgear_ms2110.h" +#include + +DECLARE_GLOBAL_DATA_PTR; +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NETGEAR_MS2110_OE_VAL_LOW, + NETGEAR_MS2110_OE_VAL_HIGH, + NETGEAR_MS2110_OE_LOW, NETGEAR_MS2110_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_SPI_SCn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GE1_13, + MPP34_SATA1_ACTn, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NETGEAR_MS2110; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + diff --git a/board/Marvell/netgear_ms2110/netgear_ms2110.h b/board/Marvell/netgear_ms2110/netgear_ms2110.h new file mode 100644 index 0000000000..6ed0440110 --- /dev/null +++ b/board/Marvell/netgear_ms2110/netgear_ms2110.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __NETGEAR_MS2110_H +#define __NETGEAR_MS2110_H + +#define NETGEAR_MS2110_OE_LOW (~(1 << 7)) +#define NETGEAR_MS2110_OE_HIGH (~(1 << 2 | 1 << 12)) +#define NETGEAR_MS2110_OE_VAL_LOW (0) +#define NETGEAR_MS2110_OE_VAL_HIGH (1 << 12) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __NETGEAR_MS2110_H */ diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg index 76b7528462..439f6f019d 100644 --- a/board/Marvell/sheevaplug/kwbimage.cfg +++ b/board/Marvell/sheevaplug/kwbimage.cfg @@ -1,7 +1,5 @@ # -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar +# (C) Copyright 2009 Marvell Semiconductor Written-by: Prafulla Wadaskar # # SPDX-License-Identifier: GPL-2.0+ # @@ -11,6 +9,7 @@ # Boot Media configurations BOOT_FROM nand +#BOOT_FROM uart NAND_ECC_MODE default NAND_PAGE_SIZE 0x0800 diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index 5d0a4242a8..54b74c53cd 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -88,6 +88,7 @@ int board_early_init_f(void) GOFLEXHOME_OE_VAL_HIGH, GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; } diff --git a/board/Seagate/goflexhome/kwbimage.cfg b/board/Seagate/goflexhome/kwbimage.cfg index 9d147ea251..8bba013873 100644 --- a/board/Seagate/goflexhome/kwbimage.cfg +++ b/board/Seagate/goflexhome/kwbimage.cfg @@ -17,6 +17,7 @@ # Boot Media configurations BOOT_FROM nand +#BOOT_FROM uart NAND_ECC_MODE default NAND_PAGE_SIZE 0x0800 diff --git a/board/Seagate/goflexnet/Kconfig b/board/Seagate/goflexnet/Kconfig new file mode 100644 index 0000000000..8a53112ebb --- /dev/null +++ b/board/Seagate/goflexnet/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GOFLEXNET + +config SYS_BOARD + default "goflexnet" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "goflexnet" + +endif diff --git a/board/Seagate/goflexnet/MAINTAINERS b/board/Seagate/goflexnet/MAINTAINERS new file mode 100644 index 0000000000..86c12c2068 --- /dev/null +++ b/board/Seagate/goflexnet/MAINTAINERS @@ -0,0 +1,6 @@ +GOFLEXNET BOARD +M: bodhi +S: Maintained +F: board/Seagate/goflexnet/ +F: include/configs/goflexnet.h +F: configs/goflexnet_defconfig diff --git a/board/Seagate/goflexnet/Makefile b/board/Seagate/goflexnet/Makefile new file mode 100644 index 0000000000..17f07f310f --- /dev/null +++ b/board/Seagate/goflexnet/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2014 bodhi +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := goflexnet.o diff --git a/board/Seagate/goflexnet/goflexnet.c b/board/Seagate/goflexnet/goflexnet.c new file mode 100644 index 0000000000..227967f628 --- /dev/null +++ b/board/Seagate/goflexnet/goflexnet.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2010 Eric C. Cooper + * + * Based on sheevaplug.c originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "goflexnet.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(GOFLEXNET_OE_VAL_LOW, + GOFLEXNET_OE_VAL_HIGH, + GOFLEXNET_OE_LOW, GOFLEXNET_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_GOFLEXNET; + + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + +#define GREEN_LED (1 << 14) +#define ORANGE_LED (1 << 15) +#define BOTH_LEDS (GREEN_LED | ORANGE_LED) +#define NEITHER_LED 0 + +static void set_leds(u32 leds, u32 blinking) +{ + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 oe = readl(&r->oe) | BOTH_LEDS; + writel(oe & ~leds, &r->oe); /* active low */ + u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; + writel(bl | blinking, &r->blink_en); +} + +void show_boot_progress(int val) +{ + switch (val) { + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ + set_leds(BOTH_LEDS, NEITHER_LED); + break; + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ + set_leds(GREEN_LED, GREEN_LED); + break; + default: + if (val < 0) /* error */ + set_leds(ORANGE_LED, ORANGE_LED); + break; + } +} diff --git a/board/Seagate/goflexnet/goflexnet.h b/board/Seagate/goflexnet/goflexnet.h new file mode 100644 index 0000000000..aaf555c511 --- /dev/null +++ b/board/Seagate/goflexnet/goflexnet.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2010 Eric C. Cooper + * + * Based on sheevaplug.h originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __GOFLEXNET_H +#define __GOFLEXNET_H + +#define GOFLEXNET_OE_LOW (~(0)) +#define GOFLEXNET_OE_HIGH (~(0)) +#define GOFLEXNET_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ +#define GOFLEXNET_OE_VAL_HIGH (1 << 17) /* LED pin high */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __GOFLEXNET_H */ diff --git a/board/Seagate/goflexnet/kwbimage.cfg b/board/Seagate/goflexnet/kwbimage.cfg new file mode 100644 index 0000000000..98b514ddfd --- /dev/null +++ b/board/Seagate/goflexnet/kwbimage.cfg @@ -0,0 +1,165 @@ +# +# Copyright (C) 2010 Eric C. Cooper +# +# Based on sheevaplug/kwbimage.cfg originally written by +# Prafulla Wadaskar +# (C) Copyright 2009 +# Marvell Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000d # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index 8309d06882..0329963dc3 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -1,4 +1,7 @@ /* + * Copyright (C) 2014 bodhi + * + * Base on: * Copyright (C) 2012 * David Purdy * @@ -15,6 +18,7 @@ #include #include #include +#include #include "pogo_e02.h" DECLARE_GLOBAL_DATA_PTR; @@ -102,3 +106,33 @@ void reset_phy(void) debug("88E1116 Initialized on %s\n", name); } #endif /* CONFIG_RESET_PHY_R */ + +#define GREEN_LED (1 << 16) +#define ORANGE_LED (1 << 17) +#define BOTH_LEDS (GREEN_LED | ORANGE_LED) +#define NEITHER_LED 0 + +static void set_leds(u32 leds, u32 blinking) +{ + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 oe = readl(&r->oe) | BOTH_LEDS; + writel(oe & ~leds, &r->oe); /* active low */ + u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; + writel(bl | blinking, &r->blink_en); +} + +void show_boot_progress(int val) +{ + switch (val) { + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ + set_leds(BOTH_LEDS, NEITHER_LED); + break; + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ + set_leds(GREEN_LED, GREEN_LED); + break; + default: + if (val < 0) /* error */ + set_leds(ORANGE_LED, ORANGE_LED); + break; + } +} diff --git a/board/cloudengines/pogo_v4/Kconfig b/board/cloudengines/pogo_v4/Kconfig new file mode 100644 index 0000000000..1ccc161ce1 --- /dev/null +++ b/board/cloudengines/pogo_v4/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POGO_V4 + +config SYS_BOARD + default "pogo_v4" + +config SYS_VENDOR + default "cloudengines" + +config SYS_CONFIG_NAME + default "pogo_v4" + +endif diff --git a/board/cloudengines/pogo_v4/MAINTAINERS b/board/cloudengines/pogo_v4/MAINTAINERS new file mode 100644 index 0000000000..b3e0b14af7 --- /dev/null +++ b/board/cloudengines/pogo_v4/MAINTAINERS @@ -0,0 +1,6 @@ +POGO_V4 BOARD +M: bodhi +S: Maintained +F: board/cloudengines/pogo_v4/ +F: include/configs/pogo_v4.h +F: configs/pogo_v4_defconfig diff --git a/board/cloudengines/pogo_v4/Makefile b/board/cloudengines/pogo_v4/Makefile new file mode 100644 index 0000000000..44a3688e13 --- /dev/null +++ b/board/cloudengines/pogo_v4/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2009 bodhi +# +# Based on +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pogo_v4.o diff --git a/board/cloudengines/pogo_v4/kwbimage.cfg b/board/cloudengines/pogo_v4/kwbimage.cfg new file mode 100644 index 0000000000..be4a7b19d3 --- /dev/null +++ b/board/cloudengines/pogo_v4/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# Copyright (C) 2012 +# David Purdy +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see . +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations (DONE) +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME) +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?) +DATA 0xffd01400 0x43000618 # DDR Configuration register +# bit13-0: 0x200 (200 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x34143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000819 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals) +# bit1-0: 00, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 (<===== change to CL=3 ?) +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xffd01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 0 , no sample stage +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE) +DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE) +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/cloudengines/pogo_v4/pogo_v4.c b/board/cloudengines/pogo_v4/pogo_v4.c new file mode 100644 index 0000000000..6bc932eee1 --- /dev/null +++ b/board/cloudengines/pogo_v4/pogo_v4.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2014-2017 bodhi + * + * Based on + * + * Copyright (C) 2014 + * + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include "pogo_v4.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(POGO_V4_OE_VAL_LOW, + POGO_V4_OE_VAL_HIGH, + POGO_V4_OE_LOW, POGO_V4_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* Green LED */ + MPP23_GPIO, + MPP24_GPIO, /* Red LED */ + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, /* Eject button */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, /* FR6192 has only 36 GPIOs */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Boot parameters address */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + kw_gpio_set_valid(20, 1); + kw_gpio_set_valid(21, 1); + kw_gpio_set_valid(22, 1); + kw_gpio_set_valid(24, 1); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + debug("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + +#define GREEN_LED (1 << 22) +#define RED_LED (1 << 24) +#define BOTH_LEDS (GREEN_LED | RED_LED) +#define NEITHER_LED 0 + +static void set_leds(u32 leds, u32 blinking) +{ + struct kwgpio_registers *r; + u32 oe; + u32 bl; + + r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + oe = readl(&r->oe) | BOTH_LEDS; + writel(oe & ~leds, &r->oe); /* active low */ + bl = readl(&r->blink_en) & ~BOTH_LEDS; + writel(bl | blinking, &r->blink_en); +} + +void show_boot_progress(int val) +{ + switch (val) { + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ + set_leds(BOTH_LEDS, NEITHER_LED); + break; + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ + set_leds(GREEN_LED, GREEN_LED); + break; + default: + if (val < 0) /* error */ + set_leds(RED_LED, RED_LED); + break; + } +} + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO button status */ +/* +un-pressed: + gpio-29 (Eject Button ) in hi (act lo) - IRQ edge (clear ) +pressed + gpio-29 (Eject Button ) in lo (act hi) - IRQ edge (clear ) +*/ + +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "eject") == 0) { + kw_gpio_set_valid(BTN_EJECT, GPIO_INPUT_OK); + kw_gpio_direction_input(BTN_EJECT); + return kw_gpio_get_value(BTN_EJECT); + } + else + return -1; +} + + +U_BOOT_CMD(button, 2, 0, do_read_button, + "Return GPIO button status 0=off 1=on", + "- button eject: test buttons states\n" +); + +#endif + diff --git a/board/cloudengines/pogo_v4/pogo_v4.h b/board/cloudengines/pogo_v4/pogo_v4.h new file mode 100644 index 0000000000..3cae984c87 --- /dev/null +++ b/board/cloudengines/pogo_v4/pogo_v4.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 + * bodhi + * + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#ifndef __POGO_V4_H +#define __POGO_V4_H + +/* GPIO configuration */ +#define POGO_V4_OE_LOW (~(0)) +#define POGO_V4_OE_HIGH (~(0)) +#define POGO_V4_OE_VAL_LOW (1 << 29) +#define POGO_V4_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +/* button */ +#define BTN_EJECT 29 + +#endif /* __POGO_V4_H */ diff --git a/board/hp/t5325/Kconfig b/board/hp/t5325/Kconfig new file mode 100644 index 0000000000..14bb3a5d9e --- /dev/null +++ b/board/hp/t5325/Kconfig @@ -0,0 +1,16 @@ +# +# (C) Copyright 2016 bodhi +# +# +if TARGET_T5325 + +config SYS_BOARD + default "t5325" + +config SYS_VENDOR + default "hp" + +config SYS_CONFIG_NAME + default "t5325" + +endif diff --git a/board/hp/t5325/MAINTAINERS b/board/hp/t5325/MAINTAINERS new file mode 100644 index 0000000000..5ecf299d95 --- /dev/null +++ b/board/hp/t5325/MAINTAINERS @@ -0,0 +1,6 @@ +T5325 BOARD +M: bodhi +S: Maintained +F: board/hp/t5325/ +F: include/configs/t5325.h +F: configs/t5325_defconfig diff --git a/board/hp/t5325/Makefile b/board/hp/t5325/Makefile new file mode 100644 index 0000000000..0d9848ef63 --- /dev/null +++ b/board/hp/t5325/Makefile @@ -0,0 +1,11 @@ +# (C) Copyright 2016 bodhi +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := t5325.o diff --git a/board/hp/t5325/kwbimage.cfg b/board/hp/t5325/kwbimage.cfg new file mode 100644 index 0000000000..8bc26f5524 --- /dev/null +++ b/board/hp/t5325/kwbimage.cfg @@ -0,0 +1,149 @@ +# +# (C) Copyright 2016 bodhi +# +# Based on +# (C) Copyright 2009 Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer to doc/README.kwbimage for more details about how-to +# configure and create kirkwood boot images. +# + +# Boot Media configurations +BOOT_FROM spi +#BOOT_FROM uart +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/hp/t5325/t5325.c b/board/hp/t5325/t5325.c new file mode 100644 index 0000000000..a68eacc586 --- /dev/null +++ b/board/hp/t5325/t5325.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2016-2017 bodhi + * + * Based on + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "t5325.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(T5325_OE_VAL_LOW, + T5325_OE_VAL_HIGH, + T5325_OE_LOW, + T5325_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_GPIO, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_SPI_SCn, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, /* USB HDD Power */ + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_T5325; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + kw_gpio_set_valid(47, 1); + kw_gpio_direction_output(47, 0); + kw_gpio_set_value(47, 1); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E3016 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* Set RGMII (RX) delay and copper mode */ + miiphy_read(name, devadr, 28, ®); + reg &= ~( (1<<3) | (1<<10) | (1<<11) ); + reg |= (1<<10); + miiphy_write(name, devadr, 28, reg); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E3016 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO button status */ +/* +un-pressed: + gpio-45 (Power Button ) in hi (act lo) - IRQ edge (clear ) +pressed + gpio-45 (Power Button ) in lo (act hi) - IRQ edge (clear ) +*/ + + + + +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "power") == 0) { + kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK); + kw_gpio_direction_input(BTN_POWER); + return kw_gpio_get_value(BTN_POWER); + } + else + return -1; +} + + +U_BOOT_CMD(button, 2, 0, do_read_button, + "Return GPIO button status 0=off 1=on", + "- button power: test buttons states\n" +); + +#endif + diff --git a/board/hp/t5325/t5325.h b/board/hp/t5325/t5325.h new file mode 100644 index 0000000000..7691b8bf56 --- /dev/null +++ b/board/hp/t5325/t5325.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2016 bodhi + * + * Based on + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T5325_H +#define __T5325_H + +/* low GPIO's */ +#define SYS_GREEN_LED (1 << 21) + +#define T5325_OE_LOW (~(0)) +#define T5325_OE_VAL_LOW (SYS_GREEN_LED) + +/* high GPIO's */ + +#define USB_HDD_POWER (1 << 15) + +#define T5325_OE_HIGH (~(0)) +#define T5325_OE_VAL_HIGH (USB_HDD_POWER) + +/* PHY related */ +#define MV88E3016_LED_FCTRL_REG 24 //??? +#define MV88E3016_MAC_CTRL_REG 28 +#define MV88E3016_PGADR_REG 22 +#define MV88E3016_RGMII_TXTM_CTRL (1 << 4) //??? +#define MV88E3016_RGMII_RXTM_CTRL (1 << 5) //??? + +#define BTN_POWER 45 + +#endif /* __T5325_H */ diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 086a473e88..68dd3f6b6f 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "iconnect.h" DECLARE_GLOBAL_DATA_PTR; @@ -91,3 +92,33 @@ int board_init(void) return 0; } + +#define BLUE_LED (1 << 10) /* BLUE 42 */ +#define RED_LED (1 << 11) /* RED 43 */ +#define BOTH_LEDS (BLUE_LED | RED_LED) +#define NEITHER_LED 0 + +static void set_leds(u32 leds, u32 blinking) +{ + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 oe = readl(&r->oe) | BOTH_LEDS; + writel(oe & ~leds, &r->oe); /* active low */ + u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; + writel(bl | blinking, &r->blink_en); +} + +void show_boot_progress(int val) +{ + switch (val) { + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ + set_leds(BOTH_LEDS, NEITHER_LED); + break; + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ + set_leds(BLUE_LED, BLUE_LED); + break; + default: + if (val < 0) /* error */ + set_leds(RED_LED, RED_LED); + break; + } +} diff --git a/board/zyxel/nsa310/Kconfig b/board/zyxel/nsa310/Kconfig new file mode 100644 index 0000000000..145ade6122 --- /dev/null +++ b/board/zyxel/nsa310/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NSA310 + +config SYS_BOARD + default "nsa310" + +config SYS_VENDOR + default "zyxel" + +config SYS_CONFIG_NAME + default "nsa310" + +endif diff --git a/board/zyxel/nsa310/MAINTAINERS b/board/zyxel/nsa310/MAINTAINERS new file mode 100644 index 0000000000..d66730b0a9 --- /dev/null +++ b/board/zyxel/nsa310/MAINTAINERS @@ -0,0 +1,6 @@ +NSA310 BOARD +M: bodhi +S: Maintained +F: board/zyxel/nsa310/ +F: include/configs/nsa310.h +F: configs/nsa310_defconfig diff --git a/board/zyxel/nsa310/Makefile b/board/zyxel/nsa310/Makefile new file mode 100644 index 0000000000..dfe93cca48 --- /dev/null +++ b/board/zyxel/nsa310/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2015 bodhi +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nsa310.o diff --git a/board/zyxel/nsa310/kwbimage.cfg b/board/zyxel/nsa310/kwbimage.cfg new file mode 100644 index 0000000000..f60e1d2f9a --- /dev/null +++ b/board/zyxel/nsa310/kwbimage.cfg @@ -0,0 +1,166 @@ +# +# Copyright (C) 2013 Rafal Kazmierowski +# +# Based on guruplug.c originally written by +# Siddarth Gore +# (C) Copyright 2009 +# Marvell Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +#BOOT_FROM uart +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43010c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000c # DDR Address Control +# bit1-0: 01, Cs0width=x8 +# bit3-2: 10, Cs0size=1Gb +# bit5-4: 01, Cs1width=x8 +# bit7-6: 10, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db +DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low) +DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI +DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/zyxel/nsa310/nsa310.c b/board/zyxel/nsa310/nsa310.c new file mode 100644 index 0000000000..672b8fda05 --- /dev/null +++ b/board/zyxel/nsa310/nsa310.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2013 Rafal Kazmierowski + * + * Based on NSA320.c Peter Schildmann + * originally written by + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "nsa310.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH, + NSA310_OE_LOW, NSA310_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + /* (all LEDs & power off active high) */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, /* PCF8563 RTC chip */ + MPP9_TW_SCK, /* connected to TWSI */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* SATA2 LED (green) */ + MPP13_GPIO, /* SATA2 LED (red) */ + MPP14_GPIO, /* MCU DATA pin (in) */ + MPP15_GPIO, /* USB LED (green) */ + MPP16_GPIO, /* MCU CLK pin (out) */ + MPP17_GPIO, /* MCU ACT pin (out) */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, /* USB LED (red)-Power*/ + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, /* SYS LED (green) */ + MPP29_GPIO, /* SYS LED (red) */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* Reset button */ + MPP37_GPIO, /* Copy button */ + MPP38_GPIO, /* VID B0 */ + MPP39_GPIO, /* COPY LED (green) */ + MPP40_GPIO, /* COPY LED (red) */ + MPP41_GPIO, /* SATA1 LED (green) */ + MPP42_GPIO, /* SATA1 LED (red) */ + MPP43_GPIO, /* HTP pin */ + MPP44_GPIO, /* Buzzer */ + MPP45_GPIO, /* VID B1 */ + MPP46_GPIO, /* Power button */ + MPP47_GPIO, /* Power resume data */ + MPP48_GPIO, /* Power off */ + MPP49_GPIO, /* Power resume clock */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config,NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NSA310; + + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1318 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* Set RGMII delay */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®); + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("MV88E1318 PHY initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int val) +{ + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + u32 dout0 = readl(&gpio0->dout); + u32 blen0 = readl(&gpio0->blink_en); + + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 dout1 = readl(&gpio1->dout); + u32 blen1 = readl(&gpio1->blink_en); + + switch (val) { + case BOOTSTAGE_ID_DECOMP_IMAGE: + writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en); + writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout); + break; + case BOOTSTAGE_ID_RUN_OS: + writel(dout0 & ~SYS_RED_LED, &gpio0->dout); + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); + break; + case BOOTSTAGE_ID_NET_START: + writel(dout1 & ~COPY_RED_LED, &gpio1->dout); + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en); + break; + case BOOTSTAGE_ID_NET_LOADED: + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en); + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout); + break; + case -BOOTSTAGE_ID_NET_NETLOOP_OK: + case -BOOTSTAGE_ID_NET_LOADED: + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout); + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en); + break; + default: + if (val < 0) { + /* error */ + printf("Error occured, error code = %d\n", -val); + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); + writel(blen0 | SYS_RED_LED, &gpio0->blink_en); + } + break; + } +} +#endif diff --git a/board/zyxel/nsa310/nsa310.h b/board/zyxel/nsa310/nsa310.h new file mode 100644 index 0000000000..6634a4fe8e --- /dev/null +++ b/board/zyxel/nsa310/nsa310.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Rafal Kazmierowski + * + * Based on Peter Schildmann + * and guruplug.h originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __NSA310_H +#define __NSA310_H + +/* GPIO's */ +#define SYS_GREEN_LED (1 << 28) +#define SYS_RED_LED (1 << 29) +#define SATA1_GREEN_LED (1 << 41) +#define SATA1_RED_LED (1 << 42) +#define SATA2_GREEN_LED (1 << 12) +#define SATA2_RED_LED (1 << 13) +#define USB_GREEN_LED (1 << 15) +#define USB_RED_LED (1 << 21) +#define COPY_GREEN_LED (1 << 39) +#define COPY_RED_LED (1 << 40) + +#define NSA310_OE_LOW (0) +#define NSA310_VAL_LOW (SYS_GREEN_LED) +#define NSA310_OE_HIGH ((COPY_GREEN_LED | COPY_RED_LED | \ + SATA1_GREEN_LED | SATA1_RED_LED)) +#define NSA310_VAL_HIGH (0) + +/* PHY related */ +#define MV88E1318_MAC_CTRL_REG 21 +#define MV88E1318_PGADR_REG 22 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __NSA310_H */ diff --git a/board/zyxel/nsa310s/Kconfig b/board/zyxel/nsa310s/Kconfig index 77e734d0e2..20954bd426 100644 --- a/board/zyxel/nsa310s/Kconfig +++ b/board/zyxel/nsa310s/Kconfig @@ -1,7 +1,5 @@ # -# Copyright (C) 2015 -# Gerald Kerma -# Tony Dinh +# Copyright (C) 2016 bodhi # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS index d153758c21..285dd4ca02 100644 --- a/board/zyxel/nsa310s/MAINTAINERS +++ b/board/zyxel/nsa310s/MAINTAINERS @@ -1,7 +1,5 @@ NSA310S BOARD -M: Gerald Kerma -M: Tony Dinh -M: Luka Perkov +M: bodhi S: Maintained F: board/zyxel/nsa310s/ F: include/configs/nsa310s.h diff --git a/board/zyxel/nsa310s/Makefile b/board/zyxel/nsa310s/Makefile index 43cdb86c20..92829ea0f2 100644 --- a/board/zyxel/nsa310s/Makefile +++ b/board/zyxel/nsa310s/Makefile @@ -1,7 +1,5 @@ # -# Copyright (C) 2015 -# Gerald Kerma -# Tony Dinh +# Copyright (C) 2016 bodhi # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/zyxel/nsa310s/kwbimage.cfg b/board/zyxel/nsa310s/kwbimage.cfg index e8f4b8a69f..d3716ac5e5 100644 --- a/board/zyxel/nsa310s/kwbimage.cfg +++ b/board/zyxel/nsa310s/kwbimage.cfg @@ -1,7 +1,5 @@ # -# Copyright (C) 2015 -# Gerald Kerma -# Tony Dinh +# Copyright (C) 2016 bodhi # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c index aab33cfa2a..eeab4b4cb5 100644 --- a/board/zyxel/nsa310s/nsa310s.c +++ b/board/zyxel/nsa310s/nsa310s.c @@ -1,18 +1,20 @@ /* - * Copyright (C) 2015 - * Gerald Kerma - * Tony Dinh + * Copyright (C) 2016-2017 bodhi * * SPDX-License-Identifier: GPL-2.0+ + * */ #include #include -#include #include #include +#include +#include #include #include "nsa310s.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -23,12 +25,13 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ + mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH, - NSA310S_OE_LOW, NSA310S_OE_HIGH); + NSA310S_OE_LOW, NSA310S_OE_HIGH); - /* (all LEDs & power off active high) */ /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { + /* (all LEDs & power off active high) */ + u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, @@ -49,8 +52,8 @@ int board_early_init_f(void) MPP17_GPIO, MPP18_NF_IO0, MPP19_NF_IO1, - MPP20_GPIO, - MPP21_GPIO, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, MPP22_GPIO, MPP23_GPIO, MPP24_GPIO, @@ -62,7 +65,7 @@ int board_early_init_f(void) MPP30_GPIO, MPP31_GPIO, MPP32_GPIO, - MPP33_GPIO, + MPP33_GPIO, MPP34_GPIO, MPP35_GPIO, 0 @@ -73,61 +76,164 @@ int board_early_init_f(void) int board_init(void) { + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NSA310S; + /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + kw_gpio_set_valid(33, 1); + kw_gpio_direction_output(33, 0); + kw_gpio_set_value(33, 1); + + /* + kw_gpio_set_valid(34, 1); + kw_gpio_direction_output(34, 0); + kw_gpio_set_value(34, 1); + + kw_gpio_set_valid(36, 1); + kw_gpio_direction_output(36, 0); + kw_gpio_set_value(36, 1); + */ + return 0; } #ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1318 PHY */ void reset_phy(void) { u16 reg; - u16 phyaddr; + u16 devadr; char *name = "egiga0"; if (miiphy_set_current_dev(name)) return; - /* read PHY dev address */ - if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) { - printf("could not read PHY dev address\n"); + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); return; } - /* set RGMII delay */ - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); - miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®); - reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL); - miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); - - /* reset PHY */ - if (miiphy_reset(name, phyaddr)) - return; - - /* - * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318) - * and has an MCU attached to the LED[2] via tristate interrupt - */ + /* Set RGMII delay */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®); + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + /* The ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318) */ + /* and has an MCU attached to the LED[2] via tristate interrupt */ + reg = 0; /* switch to LED register page */ - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); /* read out LED polarity register */ - miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®); + miiphy_read(name, devadr, MV88E1318_LED_POL_REG, ®); /* clear 4, set 5 - LED2 low, tri-state */ reg &= ~(MV88E1318_LED2_4); reg |= (MV88E1318_LED2_5); /* write back LED polarity register */ - miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg); + miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg); /* jump back to page 0, per the PHY chip documenation. */ - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); - - /* set PHY back to auto-negotiation mode */ - miiphy_write(name, phyaddr, 0x4, 0x1e1); - miiphy_write(name, phyaddr, 0x9, 0x300); - /* downshift */ - miiphy_write(name, phyaddr, 0x10, 0x3860); - miiphy_write(name, phyaddr, 0x0, 0x9140); + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* Set the phy back to auto-negotiation mode */ + miiphy_write(name, devadr, 0x4, 0x1e1); + miiphy_write(name, devadr, 0x9, 0x300); + /* Downshift */ + miiphy_write(name, devadr, 0x10, 0x3860); + miiphy_write(name, devadr, 0x0, 0x9140); + + printf("MV88E1318 PHY initialized on %s\n", name); + } #endif /* CONFIG_RESET_PHY_R */ + + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int val) +{ + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + u32 dout0 = readl(&gpio0->dout); + u32 blen0 = readl(&gpio0->blink_en); + + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + + switch (val) { + case BOOTSTAGE_ID_DECOMP_IMAGE: + writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en); + writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout); + break; + case BOOTSTAGE_ID_RUN_OS: + writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout); + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); + break; + case BOOTSTAGE_ID_NET_START: + writel(dout0 & ~COPY_RED_LED, &gpio0->dout); + writel((blen0 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio0->blink_en); + break; + case BOOTSTAGE_ID_NET_LOADED: + writel(blen0 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio0->blink_en); + writel((dout0 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio0->dout); + break; + case -BOOTSTAGE_ID_NET_NETLOOP_OK: + case -BOOTSTAGE_ID_NET_LOADED: + writel(dout0 & ~COPY_GREEN_LED, &gpio0->dout); + writel((blen0 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio0->blink_en); + break; + default: + if (val < 0) { + /* error */ + printf("Error occured, error code = %d\n", -val); + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); + writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en); + } + break; + } +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO button status */ +/* +un-pressed: + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear ) + gpio-37 (Copy Button ) in hi (act lo) - IRQ edge (clear ) + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear ) +pressed + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear ) + gpio-37 (Copy Button ) in lo (act hi) - IRQ edge (clear ) + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear ) +*/ + +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "power") == 0) { + kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK); + kw_gpio_direction_input(BTN_POWER); + return !kw_gpio_get_value(BTN_POWER); + } + else if (strcmp(argv[1], "reset") == 0) + return kw_gpio_get_value(BTN_RESET); + else if (strcmp(argv[1], "copy") == 0) + return kw_gpio_get_value(BTN_COPY); + else + return -1; +} + + +U_BOOT_CMD(button, 2, 0, do_read_button, + "Return GPIO button status 0=off 1=on", + "- button power|reset|copy: test buttons states\n" +); + +#endif + diff --git a/board/zyxel/nsa310s/nsa310s.h b/board/zyxel/nsa310s/nsa310s.h index 1ea110560f..06268d75d1 100644 --- a/board/zyxel/nsa310s/nsa310s.h +++ b/board/zyxel/nsa310s/nsa310s.h @@ -1,9 +1,8 @@ /* - * Copyright (C) 2015 - * Gerald Kerma - * Tony Dinh + * Copyright (C) 2016 bodhi * * SPDX-License-Identifier: GPL-2.0+ + * */ #ifndef __NSA310S_H @@ -13,7 +12,7 @@ #define HDD1_GREEN_LED (1 << 16) #define HDD1_RED_LED (1 << 13) #define USB_GREEN_LED (1 << 15) -#define USB_POWER (1 << 21) +#define USB_POWER (1 << 21) #define SYS_GREEN_LED (1 << 28) #define SYS_ORANGE_LED (1 << 29) @@ -23,25 +22,32 @@ #define PIN_USB_GREEN_LED 15 #define PIN_USB_POWER 21 -#define NSA310S_OE_LOW (~(0)) +#define NSA310S_OE_LOW (~(HDD1_GREEN_LED | HDD1_RED_LED | \ + USB_GREEN_LED | USB_POWER | \ + SYS_GREEN_LED | SYS_ORANGE_LED)) + #define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER) /* high GPIO's */ #define HDD2_GREEN_LED (1 << 2) -#define HDD2_POWER (1 << 1) +#define HDD2_POWER (1 << 1) -#define NSA310S_OE_HIGH (~(0)) -#define NSA310S_VAL_HIGH (HDD2_POWER) +#define NSA310S_OE_HIGH (~(HDD2_GREEN_LED | HDD2_POWER )) +#define NSA310S_VAL_HIGH (HDD2_POWER) /* PHY related */ #define MV88E1318_PGADR_REG 22 #define MV88E1318_MAC_CTRL_PG 2 #define MV88E1318_MAC_CTRL_REG 21 -#define MV88E1318_RGMII_TX_CTRL (1 << 4) -#define MV88E1318_RGMII_RX_CTRL (1 << 5) -#define MV88E1318_LED_PG 3 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1318_LED_PG 3 #define MV88E1318_LED_POL_REG 17 -#define MV88E1318_LED2_4 (1 << 4) -#define MV88E1318_LED2_5 (1 << 5) +#define MV88E1318_LED2_4 (1 << 4) +#define MV88E1318_LED2_5 (1 << 5) + +#define BTN_POWER 26 +#define BTN_RESET 24 +#define BTN_COPY 25 #endif /* __NSA310S_H */ diff --git a/board/zyxel/nsa320/Kconfig b/board/zyxel/nsa320/Kconfig new file mode 100644 index 0000000000..33dc203082 --- /dev/null +++ b/board/zyxel/nsa320/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NSA320 + +config SYS_BOARD + default "nsa320" + +config SYS_VENDOR + default "zyxel" + +config SYS_CONFIG_NAME + default "nsa320" + +endif diff --git a/board/zyxel/nsa320/MAINTAINERS b/board/zyxel/nsa320/MAINTAINERS new file mode 100644 index 0000000000..d58a084bea --- /dev/null +++ b/board/zyxel/nsa320/MAINTAINERS @@ -0,0 +1,6 @@ +NSA320 BOARD +M: Jason Plum +S: Maintained +F: board/zyxel/nsa320/ +F: include/configs/nsa320.h +F: configs/nsa320_defconfig diff --git a/board/zyxel/nsa320/Makefile b/board/zyxel/nsa320/Makefile new file mode 100644 index 0000000000..335c1a12bb --- /dev/null +++ b/board/zyxel/nsa320/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2015 bodhi +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nsa320.o + + diff --git a/board/zyxel/nsa320/kwbimage.cfg b/board/zyxel/nsa320/kwbimage.cfg new file mode 100644 index 0000000000..ff5664b2f6 --- /dev/null +++ b/board/zyxel/nsa320/kwbimage.cfg @@ -0,0 +1,164 @@ +# +# Based on guruplug.c originally written by +# Siddarth Gore +# (C) Copyright 2009 +# Marvell Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +# BOOT_FROM uart +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 01, Cs0width=x8 +# bit3-2: 10, Cs0size=1Gb +# bit5-4: 01, Cs1width=x8 +# bit7-6: 10, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/zyxel/nsa320/nsa320.c b/board/zyxel/nsa320/nsa320.c new file mode 100644 index 0000000000..c9ebe0eaea --- /dev/null +++ b/board/zyxel/nsa320/nsa320.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2015-2017 bodhi + * + * Based on + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.c originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "nsa320.h" +#include + + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NSA320_VAL_LOW, NSA320_VAL_HIGH, + NSA320_OE_LOW, NSA320_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + /* (all LEDs & power off active high) */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, /* PCF8563 RTC chip */ + MPP9_TW_SCK, /* connected to TWSI */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* HDD2 LED (green) */ + MPP13_GPIO, /* HDD2 LED (red) */ + MPP14_GPIO, /* MCU DATA pin (in) */ + MPP15_GPIO, /* USB LED (green) */ + MPP16_GPIO, /* MCU CLK pin (out) */ + MPP17_GPIO, /* MCU ACT pin (out) */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, /* USB power */ + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, /* SYS LED (green) */ + MPP29_GPIO, /* SYS LED (orange) */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* reset button */ + MPP37_GPIO, /* copy button */ + MPP38_GPIO, /* VID B0 */ + MPP39_GPIO, /* COPY LED (green) */ + MPP40_GPIO, /* COPY LED (red) */ + MPP41_GPIO, /* HDD1 LED (green) */ + MPP42_GPIO, /* HDD1 LED (red) */ + MPP43_GPIO, /* HTP pin */ + MPP44_GPIO, /* buzzer */ + MPP45_GPIO, /* VID B1 */ + MPP46_GPIO, /* power button */ + MPP47_GPIO, /* power resume data */ + MPP48_GPIO, /* power off */ + MPP49_GPIO, /* power resume clock */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NSA320; + + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1318 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* Set RGMII delay */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®); + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + /* The ZyXEL NSA320 uses the 88E1310 Alaska */ + /* and has an MCU attached to the LED[2] via tristate interrupt */ + reg = 0; + + /* switch to LED register page */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); + /* read out LED polarity register */ + miiphy_read(name, devadr, MV88E1318_LED_POL_REG, ®); + /* clear 4, set 5 - LED2 low, tri-state */ + reg &= ~(MV88E1318_LED2_4); + reg |= (MV88E1318_LED2_5); + /* write back LED polarity register */ + miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg); + /* jump back to page 0, per the PHY chip documenation. */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* Set the phy back to auto-negotiation mode */ + miiphy_write(name, devadr, 0x4, 0x1e1); + miiphy_write(name, devadr, 0x9, 0x300); + /* Downshift */ + miiphy_write(name, devadr, 0x10, 0x3860); + miiphy_write(name, devadr, 0x0, 0x9140); + + printf("MV88E1318 PHY initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int val) +{ + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + u32 dout0 = readl(&gpio0->dout); + u32 blen0 = readl(&gpio0->blink_en); + + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 dout1 = readl(&gpio1->dout); + u32 blen1 = readl(&gpio1->blink_en); + + switch (val) { + case BOOTSTAGE_ID_DECOMP_IMAGE: + writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en); + writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout); + break; + case BOOTSTAGE_ID_RUN_OS: + writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout); + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); + break; + case BOOTSTAGE_ID_NET_START: + writel(dout1 & ~COPY_RED_LED, &gpio1->dout); + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en); + break; + case BOOTSTAGE_ID_NET_LOADED: + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en); + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout); + break; + case -BOOTSTAGE_ID_NET_NETLOOP_OK: + case -BOOTSTAGE_ID_NET_LOADED: + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout); + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en); + break; + default: + if (val < 0) { + /* error */ + printf("Error occured, error code = %d\n", -val); + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); + writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en); + } + break; + } +} +#endif diff --git a/board/zyxel/nsa320/nsa320.h b/board/zyxel/nsa320/nsa320.h new file mode 100644 index 0000000000..e400638c5c --- /dev/null +++ b/board/zyxel/nsa320/nsa320.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.h originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __NSA320_H +#define __NSA320_H + +/* low GPIO's */ +#define HDD2_GREEN_LED (1 << 12) +#define HDD2_RED_LED (1 << 13) +#define USB_GREEN_LED (1 << 15) +#define USB_POWER (1 << 21) +#define SYS_GREEN_LED (1 << 28) +#define SYS_ORANGE_LED (1 << 29) + +#define PIN_USB_GREEN_LED 15 +#define PIN_USB_POWER 21 + +#define NSA320_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \ + USB_GREEN_LED | USB_POWER | \ + SYS_GREEN_LED | SYS_ORANGE_LED)) +#define NSA320_VAL_LOW (SYS_GREEN_LED | USB_POWER) + +/* high GPIO's */ +#define COPY_GREEN_LED (1 << 7) +#define COPY_RED_LED (1 << 8) +#define HDD1_GREEN_LED (1 << 9) +#define HDD1_RED_LED (1 << 10) + +#define NSA320_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \ + HDD1_GREEN_LED | HDD1_RED_LED)) +#define NSA320_VAL_HIGH (0) + +/* PHY related */ +#define MV88E1318_PGADR_REG 22 +#define MV88E1318_MAC_CTRL_REG 21 +#define MV88E1318_MAC_CTRL_PG 2 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1318_LED_PG 3 +#define MV88E1318_LED_POL_REG 17 +#define MV88E1318_LED2_4 (1 << 4) +#define MV88E1318_LED2_5 (1 << 5) + + +#endif /* __NSA320_H */ diff --git a/board/zyxel/nsa325/Kconfig b/board/zyxel/nsa325/Kconfig new file mode 100644 index 0000000000..1fe5ead76e --- /dev/null +++ b/board/zyxel/nsa325/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NSA325 + +config SYS_BOARD + default "nsa325" + +config SYS_VENDOR + default "zyxel" + +config SYS_CONFIG_NAME + default "nsa325" + +endif diff --git a/board/zyxel/nsa325/MAINTAINERS b/board/zyxel/nsa325/MAINTAINERS new file mode 100644 index 0000000000..665ffb0dd0 --- /dev/null +++ b/board/zyxel/nsa325/MAINTAINERS @@ -0,0 +1,6 @@ +NSA325 BOARD +M: Jason Plum +S: Maintained +F: board/zyxel/nsa325/ +F: include/configs/nsa325.h +F: configs/nsa325_defconfig diff --git a/board/zyxel/nsa325/Makefile b/board/zyxel/nsa325/Makefile new file mode 100644 index 0000000000..4ee953be32 --- /dev/null +++ b/board/zyxel/nsa325/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2015 bodhi +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nsa325.o + diff --git a/board/zyxel/nsa325/kwbimage.cfg b/board/zyxel/nsa325/kwbimage.cfg new file mode 100644 index 0000000000..5a27d38cbc --- /dev/null +++ b/board/zyxel/nsa325/kwbimage.cfg @@ -0,0 +1,77 @@ +# Copyright (C) 2015 bodhi +# +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +#BOOT_FROM uart +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization +DATA 0xFFD01400 0x4301503E # DDR Configuration register +DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low +DATA 0xFFD01408 0x33137777 # DDR Timing (Low) +DATA 0xFFD0140C 0x16000C55 # DDR Timing (High) +DATA 0xFFD01410 0x04000000 # DDR Address Control +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +DATA 0xFFD01418 0x00000000 # DDR Operation +DATA 0xFFD0141C 0x00000672 # DDR Mode +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +DATA 0xFFD01424 0x0000F14F # DDR Controller Control High +DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing +DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb +DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1 +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control + +DATA 0xFFD015D0 0x00000630 +DATA 0xFFD015D4 0x00000046 +DATA 0xFFD015D8 0x00000008 +DATA 0xFFD015DC 0x00000000 +DATA 0xFFD015E0 0x00000023 +DATA 0xFFD015E4 0x00203C18 +DATA 0xFFD01620 0x00384800 +DATA 0xFFD01480 0x00000001 +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x00066666 + +DATA 0xFFD10100 0x00004000 +DATA 0xFFD10104 0xFFFFBFFF + +# End of Header extension +DATA 0x0 0x0 + diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c new file mode 100644 index 0000000000..a9d76f9cbc --- /dev/null +++ b/board/zyxel/nsa325/nsa325.c @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2015-2017 bodhi + * + * Based on + * Copyright (C) 2014 Jason Plum + * + * Based on nsa320.c originall written by + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.c originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "nsa325.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH, + NSA325_OE_LOW, NSA325_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + /* (all LEDs & power off active high) */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, /* PCF8563 RTC chip */ + MPP9_TW_SCK, /* connected to TWSI */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* HDD2 LED (green) */ + MPP13_GPIO, /* HDD2 LED (red) */ + MPP14_GPIO, /* MCU DATA pin (in) */ + MPP15_GPIO, /* USB LED (green) */ + MPP16_GPIO, /* MCU CLK pin (out) */ + MPP17_GPIO, /* MCU ACT pin (out) */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, /* USB power */ + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, /* SYS LED (green) */ + MPP29_GPIO, /* SYS LED (orange) */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* reset button */ + MPP37_GPIO, /* copy button */ + MPP38_GPIO, /* VID B0 */ + MPP39_GPIO, /* COPY LED (green) */ + MPP40_GPIO, /* COPY LED (red) */ + MPP41_GPIO, /* HDD1 LED (green) */ + MPP42_GPIO, /* HDD1 LED (red) */ + MPP43_GPIO, /* HTP pin */ + MPP44_GPIO, /* buzzer */ + MPP45_GPIO, /* VID B1 */ + MPP46_GPIO, /* power button */ + MPP47_GPIO, /* HDD2 power */ + MPP48_GPIO, /* power off */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NSA325; + + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + kw_gpio_set_valid(14, 1); + kw_gpio_direction_output(14, 0); + kw_gpio_set_value(14, 1); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1318 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* Set RGMII delay */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®); + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */ + /* and has an MCU attached to the LED[2] via tristate interrupt */ + reg = 0; + + /* switch to LED register page */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); + /* read out LED polarity register */ + miiphy_read(name, devadr, MV88E1318_LED_POL_REG, ®); + /* clear 4, set 5 - LED2 low, tri-state */ + reg &= ~(MV88E1318_LED2_4); + reg |= (MV88E1318_LED2_5); + /* write back LED polarity register */ + miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg); + /* jump back to page 0, per the PHY chip documenation. */ + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); + + /* Set the phy back to auto-negotiation mode */ + miiphy_write(name, devadr, 0x4, 0x1e1); + miiphy_write(name, devadr, 0x9, 0x300); + /* Downshift */ + miiphy_write(name, devadr, 0x10, 0x3860); + miiphy_write(name, devadr, 0x0, 0x9140); + + printf("MV88E1318 PHY initialized on %s\n", name); + +} +#endif /* CONFIG_RESET_PHY_R */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int val) +{ + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + u32 dout0 = readl(&gpio0->dout); + u32 blen0 = readl(&gpio0->blink_en); + + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 dout1 = readl(&gpio1->dout); + u32 blen1 = readl(&gpio1->blink_en); + + switch (val) { + case BOOTSTAGE_ID_DECOMP_IMAGE: + writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en); + writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout); + break; + case BOOTSTAGE_ID_RUN_OS: + writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout); + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); + break; + case BOOTSTAGE_ID_NET_START: + writel(dout1 & ~COPY_RED_LED, &gpio1->dout); + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en); + break; + case BOOTSTAGE_ID_NET_LOADED: + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en); + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout); + break; + case -BOOTSTAGE_ID_NET_NETLOOP_OK: + case -BOOTSTAGE_ID_NET_LOADED: + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout); + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en); + break; + default: + if (val < 0) { + /* error */ + printf("Error occured, error code = %d\n", -val); + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); + writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en); + } + break; + } +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO button status */ +/* +un-pressed: + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear ) + gpio-37 (Copy Button ) in hi (act lo) - IRQ edge (clear ) + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear ) +pressed + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear ) + gpio-37 (Copy Button ) in lo (act hi) - IRQ edge (clear ) + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear ) +*/ + +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "power") == 0) { + kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK); + kw_gpio_direction_input(BTN_POWER); + return !kw_gpio_get_value(BTN_POWER); + } + else if (strcmp(argv[1], "reset") == 0) + return kw_gpio_get_value(BTN_RESET); + else if (strcmp(argv[1], "copy") == 0) + return kw_gpio_get_value(BTN_COPY); + else + return -1; +} + + +U_BOOT_CMD(button, 2, 0, do_read_button, + "Return GPIO button status 0=off 1=on", + "- button power|reset|copy: test buttons states\n" +); + +#endif + diff --git a/board/zyxel/nsa325/nsa325.h b/board/zyxel/nsa325/nsa325.h new file mode 100644 index 0000000000..996653e234 --- /dev/null +++ b/board/zyxel/nsa325/nsa325.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Jason Plum + * + * Based on nsa320.h originall written by + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.h originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __NSA325_H +#define __NSA325_H + +/* low GPIO's */ +#define HDD2_GREEN_LED (1 << 12) +#define HDD2_RED_LED (1 << 13) +#define USB_GREEN_LED (1 << 15) +#define USB_POWER (1 << 21) +#define SYS_GREEN_LED (1 << 28) +#define SYS_ORANGE_LED (1 << 29) + +#define PIN_USB_GREEN_LED 15 +#define PIN_USB_POWER 21 + +#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \ + USB_GREEN_LED | USB_POWER | \ + SYS_GREEN_LED | SYS_ORANGE_LED)) +#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER) + +/* high GPIO's */ +#define COPY_GREEN_LED (1 << 7) +#define COPY_RED_LED (1 << 8) +#define HDD1_GREEN_LED (1 << 9) +#define HDD1_RED_LED (1 << 10) +#define HDD2_POWER (1 << 15) +#define WATCHDOG_SIGNAL (1 << 14) + +#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \ + HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL )) +#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER) + +/* PHY related */ +#define MV88E1318_PGADR_REG 22 +#define MV88E1318_MAC_CTRL_PG 2 +#define MV88E1318_MAC_CTRL_REG 21 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1318_LED_PG 3 +#define MV88E1318_LED_POL_REG 17 +#define MV88E1318_LED2_4 (1 << 4) +#define MV88E1318_LED2_5 (1 << 5) + +#define BTN_POWER 46 +#define BTN_RESET 36 +#define BTN_COPY 37 + +#endif /* __NSA325_H */ diff --git a/cmd/jffs2.c b/cmd/jffs2.c index 9be198eddc..2bf4d04f18 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -456,7 +456,7 @@ static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int pa } /***************************************************/ -/* U-Boot commands */ +/* U-boot commands */ /***************************************************/ /** @@ -600,20 +600,21 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /***************************************************/ U_BOOT_CMD( fsload, 3, 0, do_jffs2_fsload, - "load binary file from a filesystem image", + "load binary file from a jffs filesystem image", "[ off ] [ filename ]\n" " - load binary file from flash bank\n" " with offset 'off'" ); U_BOOT_CMD( - fsls, 2, 1, do_jffs2_ls, - "list files in a directory (default /)", + fsls, 2, 1, do_jffs2_ls, + "list jffs files in a directory (default /)", "[ directory ]" ); U_BOOT_CMD( fsinfo, 1, 1, do_jffs2_fsinfo, - "print information about filesystems", + "print information about jffs filesystems", "" ); /***************************************************/ + diff --git a/cmd/mmc.c b/cmd/mmc.c index f83032ec45..9f0ee7fd70 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -362,6 +362,9 @@ static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag, if (!mmc) return CMD_RET_FAILURE; + printf("\nMMC rescan: current device # %d initialized OK\n", + curr_device); + return CMD_RET_SUCCESS; } static int do_mmc_part(cmd_tbl_t *cmdtp, int flag, diff --git a/cmd/usb.c b/cmd/usb.c index 4fa456e318..5f4c507c6c 100644 --- a/cmd/usb.c +++ b/cmd/usb.c @@ -755,9 +755,10 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) " ... ", usb_stor_curr_dev, blk, cnt); stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, usb_stor_curr_dev); + i = get_timer(0); n = blk_dread(stor_dev, blk, cnt, (ulong *)addr); - printf("%ld blocks read: %s\n", n, - (n == cnt) ? "OK" : "ERROR"); + printf("%5ld blocks read: %s in %5lu ms\n", n, + (n == cnt) ? "OK " : "ERROR", get_timer(i)); if (n == cnt) return 0; return 1; diff --git a/common/board_r.c b/common/board_r.c index 3341a528b0..10aaf0ac49 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -629,12 +629,10 @@ static int initr_pcmcia(void) #if defined(CONFIG_IDE) static int initr_ide(void) { - puts("IDE: "); #if defined(CONFIG_START_IDE) + puts("IDE: "); if (board_start_ide()) ide_init(); -#else - ide_init(); #endif return 0; } diff --git a/common/bootm.c b/common/bootm.c index b2c09126ce..9e8c076e94 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -238,6 +238,7 @@ int bootm_find_images(int flag, int argc, char * const argv[]) #if IMAGE_ENABLE_OF_LIBFDT /* find flattened device tree */ + ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images, &images.ft_addr, &images.ft_len); if (ret) { @@ -259,6 +260,7 @@ int bootm_find_images(int flag, int argc, char * const argv[]) #endif /* find all of the loadables */ + ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT, NULL, NULL); if (ret) { @@ -494,6 +496,12 @@ ulong bootm_disable_interrupts(void) iflag = disable_interrupts(); #ifdef CONFIG_NETCONSOLE /* Stop the ethernet stack if NetConsole could have left it up */ + /* and make sure that the starting kernel message printed out first */ + char *s; + s = getenv ("stdout"); + if (strcmp(s, "nc") == 0) { + printf("\n\nStarting kernel ...\n"); + } eth_halt(); # ifndef CONFIG_DM_ETH eth_unregister(eth_get_dev()); diff --git a/common/usb.c b/common/usb.c index 0904259757..0eb5171e2c 100644 --- a/common/usb.c +++ b/common/usb.c @@ -921,14 +921,19 @@ static int get_descriptor_len(struct usb_device *dev, int len, int expect_len) __maybe_unused struct usb_device_descriptor *desc; ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ); int err; + int retry = 5; desc = (struct usb_device_descriptor *)tmpbuf; +again: err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, len); if (err < expect_len) { if (err < 0) { - printf("unable to get device descriptor (error=%d)\n", - err); + printf("unable to get device descriptor (error=%d) retry: %d\n", + err, retry); + mdelay(50); + if (--retry >= 0) + goto again; /* Some drives are just slow to wake up. */ return err; } else { printf("USB device descriptor short read (expected %i, got %i)\n", diff --git a/common/usb_storage.c b/common/usb_storage.c index 03171f74cb..33e62ef5ae 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -111,6 +111,8 @@ struct us_data { #define USB_MAX_XFER_BLK 20 #endif +int usb_max_xfer_blk = USB_MAX_XFER_BLK; + #ifndef CONFIG_BLK static struct us_data usb_stor[USB_MAX_STOR_DEV]; #endif @@ -314,7 +316,7 @@ int usb_stor_scan(int mode) printf(" scanning usb for storage devices... "); #ifndef CONFIG_DM_USB - unsigned char i; + int i; usb_disable_asynch(1); /* asynch transfer not allowed */ @@ -743,6 +745,7 @@ static int usb_stor_BBB_transport(ccb *srb, struct us_data *us) pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out); /* DATA phase + error handling */ data_actlen = 0; + mdelay(10); /* Like linux does. */ /* no data, go immediately to the STATUS phase */ if (srb->datalen == 0) goto st; @@ -754,6 +757,13 @@ static int usb_stor_BBB_transport(ccb *srb, struct us_data *us) result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT * 5); + /* special handling of XACTERR in DATA phase */ + if ((result < 0) && (us->pusb_dev->status & USB_ST_XACTERR)) { + debug("XACTERR in data phase. Clear, reset, and return fail.\n"); + usb_stor_BBB_clear_endpt_stall(us, dir_in ? us->ep_in : us->ep_out); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } /* special handling of STALL in DATA phase */ if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { debug("DATA:stall\n"); @@ -994,9 +1004,40 @@ static int usb_request_sense(ccb *srb, struct us_data *ss) return 0; } +/* This spins up the disk and also consumes the time that the + * disk takes to become active and ready to read data. + * Some drives (like Western Digital) can take more than 5 seconds. + * The delay occurs on the 1st data read from the disk. + * Extending the timeout here works better than handling the timeout + * as an error on a "real" read operation. */ +static int usb_spinup(ccb *srb, struct us_data *ss) +{ + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_START_STP; + srb->cmd[1] = srb->lun << 5; + srb->cmd[4] = 1; /* Start spinup. */ + srb->datalen = 0; + srb->cmdlen = 6; + ss->pusb_dev->extra_timout = 9876; + ss->transport(srb, ss); + ss->pusb_dev->extra_timout = 0; + return 0; +} + + + static int usb_test_unit_ready(ccb *srb, struct us_data *ss) { int retries = 10; + int gave_extra_time = 0; + + /* increase the retry period if env was defined */ + unsigned long usb_ready_retry = 0; + usb_ready_retry = getenv_ulong("usb_ready_retry", 10, 0); + if (usb_ready_retry) { + retries *= usb_ready_retry; + printf ("\nUse USB retry period from the environment: %ld second(s)\n", usb_ready_retry); + } do { memset(&srb->cmd[0], 0, 12); @@ -1019,6 +1060,13 @@ static int usb_test_unit_ready(ccb *srb, struct us_data *ss) if ((srb->sense_buf[2] == 0x02) && (srb->sense_buf[12] == 0x3a)) return -1; + /* If the status is "Not Ready - becoming ready", give it + * more time. Linux issues a spinup command (once) and gives + * it 100 seconds. */ + if (srb->sense_buf[2] == 0x02 && srb->sense_buf[12] == 0x04 && + gave_extra_time == 0) + gave_extra_time = retries; /* Allow a retry period from 1 second to the env usb_ready_retry*/ + mdelay(100); } while (retries--); @@ -1122,6 +1170,7 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr, if (blkcnt == 0) return 0; + usb_max_xfer_blk = getenv_ulong("usb_max_blk", 10, USB_MAX_XFER_BLK); /* Setup device */ #ifdef CONFIG_BLK block_dev = dev_get_uclass_platdata(dev); @@ -1147,21 +1196,50 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr, PRIxPTR "\n", block_dev->devnum, start, blks, buf_addr); do { - /* XXX need some comment here */ + /* Probably most errors are USB errors, not hard disk error. + * Many disks use a USB chip that is flaky when doing large transfers. The workaround + * is to dynamically reduce the transfer size and allow an additional try. + * This should pick up flaky disks. Linux uses a quirks table. We'll use observation. + * Give it 1 try very large, 1 try large, 2 tries medium and 2 tries small(ish). + * On a solid fail (actual disk error)(which should be rare), this will give us 6 tries max, + * and only that many if the read is quite large. + * A fail on a very short read obviously doesn't have a too-large max_blks. Timeout + * due to Spinup being a case in point. + */ retry = 2; srb->pdata = (unsigned char *)buf_addr; - if (blks > USB_MAX_XFER_BLK) - smallblks = USB_MAX_XFER_BLK; +retry_it: + if (blks > usb_max_xfer_blk) + smallblks = usb_max_xfer_blk; else smallblks = (unsigned short) blks; -retry_it: - if (smallblks == USB_MAX_XFER_BLK) + if (smallblks == usb_max_xfer_blk) usb_show_progress(); srb->datalen = block_dev->blksz * smallblks; srb->pdata = (unsigned char *)buf_addr; if (usb_read_10(srb, ss, start, smallblks)) { debug("Read ERROR\n"); usb_request_sense(srb, ss); + if (smallblks > 2047) { /* Dynamically reduce the I/O size. */ + usb_max_xfer_blk = 2047; + debug("step down usb_max_xfer_blk to %d\n", usb_max_xfer_blk); + ++retry; + } + else if (smallblks > 512) { + usb_max_xfer_blk = 512; + debug("step down usb_max_xfer_blk to %d\n", usb_max_xfer_blk); + ++retry; + } + else if (smallblks > 511) { + usb_max_xfer_blk = 511; + debug("step down usb_max_xfer_blk to %d\n", usb_max_xfer_blk); + ++retry; + } + else if (smallblks > 63) { + usb_max_xfer_blk = 63; + debug("step down usb_max_xfer_blk to %d\n", usb_max_xfer_blk); + retry += 2; + } if (retry--) goto retry_it; blkcnt -= blks; @@ -1178,8 +1256,6 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr, start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ - if (blkcnt >= USB_MAX_XFER_BLK) - debug("\n"); return blkcnt; } @@ -1205,13 +1281,14 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr, if (blkcnt == 0) return 0; + usb_max_xfer_blk = getenv_ulong("usb_max_blk", 10, USB_MAX_XFER_BLK); /* Setup device */ #ifdef CONFIG_BLK block_dev = dev_get_uclass_platdata(dev); udev = dev_get_parent_priv(dev_get_parent(dev)); - debug("\nusb_read: udev %d\n", block_dev->devnum); + debug("\nusb_write: udev %d\n", block_dev->devnum); #else - debug("\nusb_read: udev %d\n", block_dev->devnum); + debug("\nusb_write: udev %d\n", block_dev->devnum); udev = usb_dev_desc[block_dev->devnum].priv; if (!udev) { debug("%s: No device\n", __func__); @@ -1236,12 +1313,12 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr, */ retry = 2; srb->pdata = (unsigned char *)buf_addr; - if (blks > USB_MAX_XFER_BLK) - smallblks = USB_MAX_XFER_BLK; + if (blks > usb_max_xfer_blk) + smallblks = usb_max_xfer_blk; else smallblks = (unsigned short) blks; retry_it: - if (smallblks == USB_MAX_XFER_BLK) + if (smallblks == usb_max_xfer_blk) usb_show_progress(); srb->datalen = block_dev->blksz * smallblks; srb->pdata = (unsigned char *)buf_addr; @@ -1263,8 +1340,6 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr, PRIxPTR "\n", start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ - if (blkcnt >= USB_MAX_XFER_BLK) - debug("\n"); return blkcnt; } @@ -1470,6 +1545,7 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, dev_desc->log2blksz = LOG2(dev_desc->blksz); dev_desc->type = perq; debug(" address %d\n", dev_desc->target); + usb_spinup(pccb, ss); return 1; } diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index a70458872d..06db95863c 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -1,25 +1,35 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_DOCKSTAR=y CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="DockStar> " +CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_SETEXPR=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y +CONFIG_CMD_BOOTZ=y + diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 8f3ffcf5ba..d3e004f41d 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -1,8 +1,11 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_DREAMPLUG=y CONFIG_IDENT_STRING="\nMarvell-DreamPlug" -CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="Dreamplug> " # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set @@ -10,20 +13,29 @@ CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SPI=y CONFIG_SYS_NS16550=y -CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y +CONFIG_CMD_BOOTZ=y + + + diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 4dfb895351..1ee4cf35a9 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -1,3 +1,6 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_GOFLEXHOME=y @@ -10,7 +13,7 @@ CONFIG_SYS_PROMPT="GoFlexHome> " CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -20,10 +23,17 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y diff --git a/configs/goflexnet_defconfig b/configs/goflexnet_defconfig new file mode 100644 index 0000000000..db1b9aad25 --- /dev/null +++ b/configs/goflexnet_defconfig @@ -0,0 +1,38 @@ +# +# (C) Copyright 2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_GOFLEXNET=y +CONFIG_IDENT_STRING="\nSeagate GoFlex Net" +CONFIG_CONSOLE_MUX=y +CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="GoFlexNet> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_USB=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +# CONFIG_MMC is not set +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + + diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 3e48380bc7..72096465c8 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -1,14 +1,19 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_ICONNECT=y -CONFIG_IDENT_STRING=" Iomega iConnect" -CONFIG_BOOTDELAY=3 +CONFIG_IDENT_STRING="\nIomega iConnect" +CONFIG_HUSH_PARSER=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="iconnect => " +CONFIG_SYS_PROMPT="iConnect> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -16,6 +21,9 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y @@ -23,3 +31,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/netgear_ms2110_defconfig b/configs/netgear_ms2110_defconfig new file mode 100644 index 0000000000..92c4bda107 --- /dev/null +++ b/configs/netgear_ms2110_defconfig @@ -0,0 +1,35 @@ +# +# (C) Copyright 2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETGEAR_MS2110=y +CONFIG_IDENT_STRING="\nNetgear Stora MS2110" +CONFIG_SYS_PROMPT="Stora> " +CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_USB=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +# CONFIG_MMC is not set +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y diff --git a/configs/nsa310_defconfig b/configs/nsa310_defconfig new file mode 100644 index 0000000000..d1667065eb --- /dev/null +++ b/configs/nsa310_defconfig @@ -0,0 +1,36 @@ +# +# (C) Copyright 2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NSA310=y +CONFIG_SYS_PROMPT="NSA310> " +CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server \n" +CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_USB=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +# CONFIG_MMC is not set +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index ae39818e4b..3c64bb15ec 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -1,17 +1,20 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NSA310S=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="NSA3x0S> " +CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="nsa310s => " +CONFIG_CONSOLE_MUX=y CONFIG_CMD_BOOTZ=y +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set -CONFIG_CMD_NAND=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -20,6 +23,9 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y @@ -27,3 +33,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/nsa320_defconfig b/configs/nsa320_defconfig new file mode 100644 index 0000000000..238c1df9f1 --- /dev/null +++ b/configs/nsa320_defconfig @@ -0,0 +1,35 @@ +# +# (C) Copyright 2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NSA320=y +CONFIG_SYS_PROMPT="NSA320> " +CONFIG_IDENT_STRING="\nZyXEL NSA320 2-Bay Power Media Server" +CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_USB=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +# CONFIG_MMC is not set +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig new file mode 100644 index 0000000000..7d0723e5a8 --- /dev/null +++ b/configs/nsa325_defconfig @@ -0,0 +1,36 @@ +# +# (C) Copyright 2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NSA325=y +CONFIG_SYS_PROMPT="NSA325> " +CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server" +CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_USB=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +# CONFIG_MMC is not set +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 57ebc0694c..14ad4cf61e 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -1,25 +1,35 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_POGO_E02=y CONFIG_IDENT_STRING="\nPogo E02" -CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="PogoE02> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig new file mode 100644 index 0000000000..d03b1f6ada --- /dev/null +++ b/configs/pogo_v4_defconfig @@ -0,0 +1,35 @@ +# +# (C) Copyright 2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_POGO_V4=y +CONFIG_SYS_PROMPT="Pogo_V4> " +CONFIG_IDENT_STRING="\nPogoplug V4" +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SETEXPR=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index ac7217dcba..bbc21a3afc 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -1,8 +1,11 @@ +# +# (C) Copyright 2017 bodhi +# CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_SHEEVAPLUG=y CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" -CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="Sheevaplug> " # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -10,22 +13,24 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_LZMA=y CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + diff --git a/configs/t5325_defconfig b/configs/t5325_defconfig new file mode 100644 index 0000000000..cfb533add2 --- /dev/null +++ b/configs/t5325_defconfig @@ -0,0 +1,46 @@ +# +# (C) Copyright 2016-2017 bodhi +# +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_T5325=y +CONFIG_SYS_PROMPT="T5325> " +CONFIG_IDENT_STRING="\nHP Thin Client T5325" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_USB=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPT=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CMD_SPI=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_FDT=y + + diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c index 43b27e3fea..3d230f0887 100644 --- a/drivers/gpio/kw_gpio.c +++ b/drivers/gpio/kw_gpio.c @@ -62,6 +62,7 @@ static void __set_blinking(unsigned pin, int blink) int kw_gpio_is_valid(unsigned pin, int mode) { + if (pin < GPIO_MAX) { if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input)) goto err_out; @@ -80,14 +81,20 @@ void kw_gpio_set_valid(unsigned pin, int mode) { if (mode == 1) mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; - if (mode & GPIO_INPUT_OK) + + if (mode & GPIO_INPUT_OK) { __set_bit(pin, gpio_valid_input); - else + } + else { __clear_bit(pin, gpio_valid_input); - if (mode & GPIO_OUTPUT_OK) + } + if (mode & GPIO_OUTPUT_OK) { __set_bit(pin, gpio_valid_output); - else + } + else { __clear_bit(pin, gpio_valid_output); + } + } /* * GENERIC_GPIO primitives. @@ -148,3 +155,35 @@ void kw_gpio_set_blink(unsigned pin, int blink) /* Set blinking. */ __set_blinking(pin, blink); } + +/* + * Hooks to GENERIC_GPIO primitives + */ + +int gpio_direction_input(unsigned pin) +{ + return kw_gpio_direction_input(pin); +} + +int gpio_direction_output(unsigned pin, int value) +{ + return kw_gpio_direction_output(pin, value); +} + +void gpio_set_value(unsigned pin, int value) { + kw_gpio_set_value(pin, value); +} + +int gpio_get_value(unsigned pin) { + return kw_gpio_get_value(pin); +} + +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} diff --git a/drivers/mmc/kirkwood_mmc.c b/drivers/mmc/kirkwood_mmc.c new file mode 100644 index 0000000000..db47ccfa46 --- /dev/null +++ b/drivers/mmc/kirkwood_mmc.c @@ -0,0 +1,480 @@ +/* + * (C) Copyright 2014 bodhi + * + * Based on + * + * (C) Copyright 2014 + * + * Based on + * + * Driver for Marvell SDIO/MMC controller + * + * (C) Copyright 2012 + * Marvell Semiconductor + * Written-by: Gérald Kerma + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "kwsdio" + +static int kw_mmc_setup_data(struct mmc_data *data) +{ + u32 ctrl_reg; + +#ifdef DEBUG + printf("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME, + (data->flags & MMC_DATA_READ) ? "read" : "write", + data->blocks, data->blocksize); +#endif + + /* default to maximum timeout */ + ctrl_reg = kwsd_read(SDIO_HOST_CTRL); + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); + kwsd_write(SDIO_HOST_CTRL, ctrl_reg); + + if (data->flags & MMC_DATA_READ) { + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->dest & 0xffff); + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->dest >> 16); + } else { + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->src & 0xffff); + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->src >> 16); + } + + kwsd_write(SDIO_BLK_COUNT, data->blocks); + kwsd_write(SDIO_BLK_SIZE, data->blocksize); + + return 0; +} + +static int kw_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + int timeout = 10; + int err; + ushort waittype = 0; + ushort resptype = 0; + ushort xfertype = 0; + ushort resp_indx = 0; + +#ifdef CONFIG_MMC_DEBUG + printf("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg); +#endif + + udelay(10000); + +#ifdef CONFIG_MMC_DEBUG + printf("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, cmd->cmdidx, kwsd_read(SDIO_HW_STATE)); +#endif + + /* Checking if card is busy */ + while ((kwsd_read(SDIO_HW_STATE) & CARD_BUSY)) { + if (timeout == 0) { + printf("%s: card busy!\n", DRIVER_NAME); + return -1; + } + timeout--; + udelay(1000); + } + + /* Set up for a data transfer if we have one */ + if (data) { + if ((err = kw_mmc_setup_data(data))) + return err; + } + + resptype = SDIO_CMD_INDEX(cmd->cmdidx); + + /* Analyzing resptype/xfertype/waittype for the command */ + if (cmd->resp_type & MMC_RSP_BUSY) + resptype |= SDIO_CMD_RSP_48BUSY; + else if (cmd->resp_type & MMC_RSP_136) + resptype |= SDIO_CMD_RSP_136; + else if (cmd->resp_type & MMC_RSP_PRESENT) + resptype |= SDIO_CMD_RSP_48; + else + resptype |= SDIO_CMD_RSP_NONE; + + if (cmd->resp_type & MMC_RSP_CRC) + resptype |= SDIO_CMD_CHECK_CMDCRC; + + if (cmd->resp_type & MMC_RSP_OPCODE) + resptype |= SDIO_CMD_INDX_CHECK; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + resptype |= SDIO_UNEXPECTED_RESP; + waittype |= SDIO_NOR_UNEXP_RSP; + } + + if (data) { + resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16; + xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN; + if (data->flags & MMC_DATA_READ) { + xfertype |= SDIO_XFER_MODE_TO_HOST; + waittype = SDIO_NOR_DMA_INI; + } else + waittype |= SDIO_NOR_XFER_DONE; + } else + waittype |= SDIO_NOR_CMD_DONE; + + /* Setting cmd arguments */ + kwsd_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff); + kwsd_write(SDIO_ARG_HI, cmd->cmdarg >> 16); + + /* Setting Xfer mode */ + kwsd_write(SDIO_XFER_MODE, xfertype); + + kwsd_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT); + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); + + /* Sending command */ + kwsd_write(SDIO_CMD, resptype); +/* + kwsd_write(SDIO_CMD, KW_MMC_MAKE_CMD(cmd->cmdidx, resptype)); +*/ + + kwsd_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK); + kwsd_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK); + + /* Waiting for completion */ + timeout = 1000000; + + while (!((kwsd_read(SDIO_NOR_INTR_STATUS)) & waittype)) { + if (kwsd_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) { +#ifdef DEBUG + printf("%s: kw_mmc_send_cmd: error! cmdidx : %d, err reg: %04x\n", DRIVER_NAME, cmd->cmdidx, kwsd_read(SDIO_ERR_INTR_STATUS)); +#endif + if (kwsd_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) { + return TIMEOUT; + } + return COMM_ERR; + } + + timeout--; + udelay(1); + if (timeout <= 0) { + printf("%s: command timed out\n", DRIVER_NAME); + return TIMEOUT; + } + } + + /* Handling response */ + if (cmd->resp_type & MMC_RSP_136) { + uint response[8]; + for (resp_indx = 0; resp_indx < 8; resp_indx++) + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx)); + + cmd->response[0] = ((response[0] & 0x03ff) << 22) | + ((response[1] & 0xffff) << 6) | + ((response[2] & 0xfc00) >> 10); + cmd->response[1] = ((response[2] & 0x03ff) << 22) | + ((response[3] & 0xffff) << 6) | + ((response[4] & 0xfc00) >> 10); + cmd->response[2] = ((response[4] & 0x03ff) << 22) | + ((response[5] & 0xffff) << 6) | + ((response[6] & 0xfc00) >> 10); + cmd->response[3] = ((response[6] & 0x03ff) << 22) | + ((response[7] & 0x3fff) << 8); + } else if (cmd->resp_type & MMC_RSP_PRESENT) { + uint response[3]; + for (resp_indx = 0; resp_indx < 3; resp_indx++) + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx)); + + cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) | + ((response[1] & 0xffff) << (14 - 8)) | + ((response[0] & 0x03ff) << (30 - 8)); + cmd->response[1] = ((response[0] & 0xfc00) >> 10); + cmd->response[2] = 0; + cmd->response[3] = 0; + } + +#ifdef CONFIG_MMC_DEBUG + printf("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type); + printf("[0x%x] ", cmd->response[0]); + printf("[0x%x] ", cmd->response[1]); + printf("[0x%x] ", cmd->response[2]); + printf("[0x%x] ", cmd->response[3]); + printf("\n"); +#endif + + return 0; +} + +#if 0 +/* Disable these three functions as they are not used anyway */ + +static void kwsd_power_up(void) +{ +#ifdef DEBUG + printf("%s: power up\n", DRIVER_NAME); +#endif + /* disable interrupts */ + kwsd_write(SDIO_NOR_INTR_EN, 0); + kwsd_write(SDIO_ERR_INTR_EN, 0); + + /* SW reset */ + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); + + kwsd_write(SDIO_XFER_MODE, 0); + + /* enable status */ + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); + + /* enable interrupts status */ + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); +} + +static void kwsd_power_down(void) +{ +#ifdef DEBUG + printf("%s: power down\n", DRIVER_NAME); +#endif + /* disable interrupts */ + kwsd_write(SDIO_NOR_INTR_EN, 0); + kwsd_write(SDIO_ERR_INTR_EN, 0); + + /* SW reset */ + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); + + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); + + /* disable status */ + kwsd_write(SDIO_NOR_STATUS_EN, 0); + kwsd_write(SDIO_ERR_STATUS_EN, 0); + + /* enable interrupts status */ + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); +} + +static u32 kw_mmc_get_base_clock(void) +{ + /* Original version did a check for board device id and revision id + * and assigned one of these clocks: + * KW_MMC_BASE_FAST_CLK_100 (revid == 0 && devid != MV88F6282_DEV_ID) + * KW_MMC_BASE_FAST_CLK_200 (revid != 0 || devid == MV88F6282_DEV_ID) + * However, this check was disabled and + * KW_MMC_BASE_FAST_CLOCK + * was returned in every case. + * Therefore, all of the dead logic was removed. */ + return KW_MMC_BASE_FAST_CLOCK; +} +#endif /* #if 0 */ + +static inline u32 kw_mmc_get_base_clock(void) +{ + /* get MMC base clock. If any logic other than just returning + * a fixed value is ever used, remove inline modifier. */ + + /* Possible values: + * - KW_MMC_BASE_FAST_CLOCK (166 MHz) + * - KW_MMC_BASE_FAST_CLK_100 (100 MHz) + * - KW_MMC_BASE_FAST_CLK_200 (200 MHz) + * + * Tests have shown that 200 MHz is more reliable than + * 166 MHz, so this value is used. */ + return KW_MMC_BASE_FAST_CLK_200; +} + +static void kw_mmc_set_clk(unsigned int clock) +{ + unsigned int m; + + if (clock == 0) { +#ifdef DEBUG + printf("%s: clock off\n", DRIVER_NAME); +#endif + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); + kwsd_write(SDIO_CLK_DIV, KW_MMC_BASE_DIV_MAX); + } else { + m = kw_mmc_get_base_clock() / (2 * clock) - 1; + if (m > KW_MMC_BASE_DIV_MAX) + m = KW_MMC_BASE_DIV_MAX; +#ifdef DEBUG + printf("%s: kw_mmc_set_clk: base = %d dividor = 0x%x clock=%d\n", DRIVER_NAME, kw_mmc_get_base_clock(), m, clock); +#endif + kwsd_write(SDIO_CLK_DIV, m & KW_MMC_BASE_DIV_MAX); + } + udelay(10000); +} + +static void kw_mmc_set_bus(unsigned int bus) +{ + u32 ctrl_reg = 0; + + ctrl_reg = kwsd_read(SDIO_HOST_CTRL); + ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; + + switch (bus) { + case 4: + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; + break; + case 1: + default: + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; + } + /* default transfer mode */ + ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN; + ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST; + + /* default to maximum timeout */ + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); + + ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN; + + ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY; + + /* + * The HI_SPEED_EN bit is causing trouble with many (but not all) + * high speed SD, SDHC and SDIO cards. Not enabling that bit + * makes all cards work. So let's just ignore that bit for now + * and revisit this issue if problems for not enabling this bit + * are ever reported. + */ +#if 0 + if (ios->timing == MMC_TIMING_MMC_HS || + ios->timing == MMC_TIMING_SD_HS) + ctrl_reg |= SDIO_HOST_CTRL_HI_SPEED_EN; +#endif + +#ifdef DEBUG + printf("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg, + (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ? + "push-pull" : "open-drain", + (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ? + "4bit-width" : "1bit-width", + (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ? + "high-speed" : ""); +#endif + + kwsd_write(SDIO_HOST_CTRL, ctrl_reg); + udelay(10000); +} + +static void kw_mmc_set_ios(struct mmc *mmc) +{ +#ifdef DEBUG + printf("%s: bus[%d] clock[%d]\n", DRIVER_NAME, mmc->bus_width, mmc->clock); +#endif + kw_mmc_set_bus(mmc->bus_width); + kw_mmc_set_clk(mmc->clock); +} + +static int kw_mmc_init(struct mmc *mmc) +{ +#ifdef DEBUG + printf("%s: kw_mmc_init\n", DRIVER_NAME); +#endif + + /* + * Setting host parameters + * Initial Host Ctrl : Timeout : max , Normal Speed mode, 4-bit data mode + * Big Endian, SD memory Card, Push_pull CMD Line + */ + kwsd_write(SDIO_HOST_CTRL, + SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) | + SDIO_HOST_CTRL_DATA_WIDTH_4_BITS | + SDIO_HOST_CTRL_BIG_ENDIAN | + SDIO_HOST_CTRL_PUSH_PULL_EN | + SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY); + + kwsd_write(SDIO_CLK_CTRL, 0); + + /* enable status */ + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); + + /* disable interrupts */ + kwsd_write(SDIO_NOR_INTR_EN, 0); + kwsd_write(SDIO_ERR_INTR_EN, 0); + + /* SW reset */ + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); + + udelay(10000); + return 0; +} + +int kw_mmc_initialize(bd_t *bis) +{ + struct mmc *mmc = NULL; + struct mmc_config *cfg = NULL; + struct mmc_ops *ops = NULL; + char *name = NULL; + +#ifdef DEBUG + printf("%s: %s base_clock = %d\n", DRIVER_NAME, kirkwood_id(), kw_mmc_get_base_clock()); +#endif + mmc = malloc(sizeof(struct mmc)); + if (!mmc) + return -1; + memset(mmc, 0, sizeof(*mmc)); + + cfg = malloc(sizeof(*cfg)); + if (cfg == NULL) + return -1; + memset(cfg, 0, sizeof(*cfg)); + mmc->cfg = cfg; /* provided configuration */ + + ops = malloc(sizeof(*ops)); + if (ops == NULL) + return -1; + memset(ops, 0, sizeof(*ops)); + cfg->ops = ops; + + name = malloc(sizeof(DRIVER_NAME)+1); + if (name == NULL) + return -1; + cfg->name = name; + + sprintf(cfg->name, DRIVER_NAME); + + ops->send_cmd = kw_mmc_send_cmd; + ops->set_ios = kw_mmc_set_ios; + ops->init = kw_mmc_init; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS; + + cfg->f_min = kw_mmc_get_base_clock()/KW_MMC_BASE_DIV_MAX; + cfg->f_max = KW_MMC_CLOCKRATE_MAX; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create (cfg, NULL); + + if (mmc == NULL) { + free(name); + free(ops); + free(cfg); + printf("\nFailed to Initialize MMC\n"); + return -1; + } + + return 0; +} diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 3500047577..c67e0e0e54 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -17,11 +17,11 @@ DECLARE_GLOBAL_DATA_PTR; #endif static char input_buffer[CONFIG_NETCONSOLE_BUFFER_SIZE]; -static int input_size; /* char count in input buffer */ -static int input_offset; /* offset to valid chars in input buffer */ +static int input_size = 0; /* char count in input buffer */ +static int input_offset = 0; /* offset to valid chars in input buffer */ static int input_recursion; static int output_recursion; -static int net_timeout; +static int net_timeout = 50; static uchar nc_ether[6]; /* server enet address */ static struct in_addr nc_ip; /* server ip */ static short nc_out_port; /* target output port */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 13aa70d606..1bc2afcc66 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -313,7 +313,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int timeout; int ret = 0; struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); + int trynum; + debug("\n***** ehci_submit_async ****\n"); debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, buffer, length, req); if (req != NULL) @@ -552,6 +554,15 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); /* Enable async. schedule. */ + trynum = 1; /* No more than 2 tries, in case of XACTERR. */ + /* When the 1st try gets xacterr, + * 2nd try gets xacterr and often babble and/or halted. + * 3rd try times out. + * After the 2nd try, the disk has recovered, so we need to clear and + * reset the USB port, then return fail so the upper layer can retry. + */ + retry_xacterr:; + vtd = &qtd[qtd_counter - 1]; cmd = ehci_readl(&ctrl->hcor->or_usbcmd); cmd |= CMD_ASE; ehci_writel(&ctrl->hcor->or_usbcmd, cmd); @@ -565,8 +576,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, /* Wait for TDs to be processed. */ ts = get_timer(0); - vtd = &qtd[qtd_counter - 1]; timeout = USB_TIMEOUT_MS(pipe); + timeout += dev->extra_timout; do { /* Invalidate dcache */ invalidate_dcache_range((unsigned long)&ctrl->qh_list, @@ -581,7 +592,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, break; WATCHDOG_RESET(); } while (get_timer(ts) < timeout); - + debug("took %4lu ms of %4d\n", get_timer(ts), timeout); + /* * Invalidate the memory area occupied by buffer * Don't try to fix the buffer alignment, if it isn't properly @@ -613,6 +625,20 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, token = hc32_to_cpu(qh->qh_overlay.qt_token); if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { debug("TOKEN=%#x\n", token); + if (token & QT_TOKEN_STATUS_XACTERR) { + if (--trynum >= 0) { /* It is necessary to do this, otherwise the disk is clagged. */ + debug("reset the TD and redo, because of XACTERR\n"); + token &= ~QT_TOKEN_STATUS_HALTED; + token |= QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_CERR(2); + vtd->qt_token = cpu_to_hc32(token); + qh->qh_overlay.qt_token = cpu_to_hc32(token); + goto retry_xacterr; + } + dev->status = USB_ST_XACTERR; + dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); + goto fail; + } + switch (QT_TOKEN_GET_STATUS(token) & ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { case 0: diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 3201177476..7c177d7458 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -668,12 +668,14 @@ static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, uint32_t reg; volatile uint32_t *status_reg; struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); + struct xhci_hccr *hccr = ctrl->hccr; struct xhci_hcor *hcor = ctrl->hcor; + int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1)); if ((req->requesttype & USB_RT_PORT) && - le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) { - printf("The request port(%d) is not configured\n", - le16_to_cpu(req->index) - 1); + le16_to_cpu(req->index) > max_ports) { + printf("The request port(%d) exceeds maximum port number\n", + le16_to_cpu(req->index) - 1); return -EINVAL; } diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 2afa38694b..18ec3ca989 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -171,9 +171,7 @@ struct xhci_hcor { volatile uint64_t or_dcbaap; volatile uint32_t or_config; volatile uint32_t reserved_2[241]; - struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS]; - - uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254]; + struct xhci_hcor_port_regs portregs[MAX_HC_PORTS]; }; /* USBCMD - USB command - command bitmasks */ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 3b56fd6739..4986fa7d15 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2014-2017 bodhi + * Based on + * * Copyright (C) 2010 Eric C. Cooper * * Based on sheevaplug.h originally written by @@ -16,6 +19,7 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_DOCKSTAR /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -24,6 +28,15 @@ * Commands configuration */ #define CONFIG_CMD_NAND +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -44,29 +57,60 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x80000 -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + /* * Default environment variables */ #define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:root; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x1100000 ${initrd}; " \ - "bootm 0x800000 0x1100000" - -#define CONFIG_MTDPARTS "mtdparts=orion_nand:1m(uboot),-(root)\0" + "run bootcmd_uenv; run bootcmd_usb; reset" #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ + "arcNumber=2998\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-dockstar.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS \ - "kernel=/boot/uImage\0" \ - "initrd=/boot/uInitrd\0" \ - "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" /* * Ethernet Driver configuration @@ -85,5 +129,16 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS #define CONFIG_LZO +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO + +/* + * Date Time + * */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ #endif /* _CONFIG_DOCKSTAR_H */ diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 003cf0e1f3..2e6b96f6ce 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2017 bodhi + * + * Based on: * (C) Copyright 2011 * Jason Cooper * @@ -22,6 +25,23 @@ * Commands configuration */ +/* + * Misc Configuration Options + */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + /* * mv-plug-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -47,28 +67,60 @@ #endif /* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size + * ENV in SPI flash + * */ -#define CONFIG_ENV_SIZE 0x1000 /* 4k */ -#define CONFIG_ENV_ADDR 0x100000 -#define CONFIG_ENV_OFFSET 0x100000 /* env starts here */ +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_ADDR 0xC0000 +#define CONFIG_ENV_OFFSET 0xC0000 /* env starts here */ /* * Default environment variables */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.2.1\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=3550\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=b6:d0:5e:0f:a1:17\0" \ + "eth1addr=7e:16:30:7e:c8:ac\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-dreamplug.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdparts=mtdparts=spi0.0:0x80000@0(u-boot),0x10000@0xC0000(u-boot-env),0x10000@0x100000(u-boot-env-stock),0x80000@0x180000(u-boot-stock)\0"\ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" \ /* * Ethernet Driver configuration @@ -76,6 +128,7 @@ #ifdef CONFIG_CMD_NET #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 +#define CONFIG_NETCONSOLE #endif /* CONFIG_CMD_NET */ /* @@ -85,4 +138,27 @@ #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #endif /*CONFIG_MVSATA_IDE*/ +/* + * File system + */ +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_SPI_FLASH_MTD + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +/* + * Kirkwood GPIO + */ +#define CONFIG_KIRKWOOD_GPIO + #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index d1635b098e..6c81e2742d 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2014-2017 bodhi + * Based on + * * Copyright (C) 2013 Suriyan Ramasami * * Based on dockstar.h originally written by @@ -42,9 +45,12 @@ /* * Commands configuration */ - #define CONFIG_CMD_NAND #define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* * mv-common.h should be defined after CMD configs since it used them @@ -72,22 +78,66 @@ /* * Default environment variables */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:root; " \ - "ubifsload 0x800000 ${kernel}; " \ - "bootm 0x800000" -#define CONFIG_MTDPARTS \ - "mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)\0" +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; reset" #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ + "arcNumber=3338\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-goflexhome.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS \ - "kernel=/boot/uImage\0" \ - "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO /* * Ethernet Driver configuration @@ -105,10 +155,13 @@ #endif /*CONFIG_MVSATA_IDE*/ /* - * * RTC driver configuration - * */ + * Date Time + * +*/ #ifdef CONFIG_CMD_DATE #define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS #endif /* CONFIG_CMD_DATE */ #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/goflexnet.h b/include/configs/goflexnet.h new file mode 100644 index 0000000000..b6c99e7b0a --- /dev/null +++ b/include/configs/goflexnet.h @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2014-2017 bodhi + * Based on + * + * Copyright (C) 2010 Eric C. Cooper + * + * Based on sheevaplug.h originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_GOFLEXNET_H +#define _CONFIG_GOFLEXNET_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nSeagate GoFlex Net" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_GOFLEXNET /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "GoFlexNet> " /* Command Prompt */ + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ + +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=3089\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-goflexnet.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + +/* + * Date Time + * */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_GOFLEXNET_H */ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index 63e50606d7..49341b2085 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2014-2017 bodhi + * Based on + * * (C) Copyright 2009-2012 * Wojciech Dubowik * Luka Perkov @@ -9,6 +12,8 @@ #ifndef _CONFIG_ICONNECT_H #define _CONFIG_ICONNECT_H +#define CONFIG_IDENT_STRING "\nIomega iConnect" + /* * High level configuration options */ @@ -32,6 +37,12 @@ */ #define CONFIG_SYS_MVFS #define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* * mv-common.h should be defined after CMD configs since it used them @@ -48,31 +59,60 @@ #else #define CONFIG_ENV_IS_NOWHERE #endif -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ /* * Default environment variables */ #define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part rootfs; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "bootm 0x800000" - -#define CONFIG_MTDPARTS \ - "mtdparts=orion_nand:" \ - "0x80000@0x0(uboot)," \ - "0x20000@0x80000(uboot_env)," \ - "-@0xa0000(rootfs)\0" + "run bootcmd_uenv; run bootcmd_usb; reset" #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS \ - "kernel=/boot/uImage\0" \ - "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" + "arcNumber=2870\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-iconnect.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" /* * Ethernet driver configuration @@ -86,10 +126,22 @@ /* * File system */ +#define CONFIG_CMD_EXT4 #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ #endif /* _CONFIG_ICONNECT_H */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 13bd6cff3d..63391246ac 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -134,6 +134,12 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS #define CONFIG_LZO +#define CONFIG_CMD_FS_GENERIC #endif +/* + * GPIO command for all Kirkwood boxes + */ +#define CONFIG_CMD_GPIO + #endif /* _MV_COMMON_H */ diff --git a/include/configs/netgear_ms2110.h b/include/configs/netgear_ms2110.h new file mode 100644 index 0000000000..cdd27ea081 --- /dev/null +++ b/include/configs/netgear_ms2110.h @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2014-2017 bodhi + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_NGMS2110_H +#define _CONFIG_NGMS2110_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_NETGEAR_MS2110 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* #define CONFIG_CMD_AUTOSCRIPT */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "Netgear Stora> " + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=2743\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-netgear_stora_ms2000\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:1m(uboot),4m@1m(kernel),251m@5m(rootfs) rw\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable first port */ +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ +#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x0A +#define CONFIG_RESET_PHY_R /* use reset_phy() to init PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * SATA + */ + +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + +/* + * Date Time + * */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NGMS2110_H */ diff --git a/include/configs/nsa310.h b/include/configs/nsa310.h new file mode 100644 index 0000000000..c0caa55409 --- /dev/null +++ b/include/configs/nsa310.h @@ -0,0 +1,181 @@ +/* Copyright (C) 2015-2017 bodhi + * + * Based on + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.h originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_NSA310_H +#define _CONFIG_NSA310_H + +#define CONFIG_IDENT_STRING "\nZyXEL NSA310 1-Bay Power Media Server \n" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_MACH_NSA310 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Misc Configuration Options + */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "NSA310> " /* Command Prompt */ + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif + +/* max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; usb stop; run bootcmd_sata; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=4022\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-nsa310.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store)," \ + "0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)\0"\ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x1 +#define CONFIG_PHY_GIGE +#define CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NSA310_H */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index bc67270af7..64cfdc8850 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -1,29 +1,41 @@ /* - * Copyright (C) 2015 - * Gerald Kerma - * Tony Dinh - * Luka Perkov + * Copyright (C) 2016-2017 bodhi * * SPDX-License-Identifier: GPL-2.0+ + * */ #ifndef _CONFIG_NSA310S_H #define _CONFIG_NSA310S_H -/* high level configuration options */ +/* + * High Level Configuration Options (easy to change) + */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6192 1 /* SOC Name */ -#define CONFIG_KW88F6702 1 /* SOC Name */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6192 1 /* Compatible SOC Name */ +#define CONFIG_KW88F6702 1 /* SOC Name */ +#define CONFIG_MACH_NSA310S /* Machine type */ +#define CONFIG_MACH_TYPE MACH_TYPE_NSA310S #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -/* add target to build it automatically upon "make" */ -#define CONFIG_BUILD_TARGET "u-boot.kwb" - -/* compression configuration */ -#define CONFIG_BZIP2 +/* + * Misc Configuration Options + */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ -/* commands configuration */ -#define CONFIG_SYS_MVFS +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* * mv-common.h should be defined after CMD configs since it used them @@ -31,63 +43,115 @@ */ #include "mv-common.h" -/* environment variables configuration */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "NSA3x0S> " /* Command Prompt */ + +/* + * Environment variables configurations + */ #ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ #else -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ #endif -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0xe0000 +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ -/* default environment variables */ +/* + * Default environment variables + */ #define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x700000 ${fdt}; " \ - "ubifsumount; " \ - "fdt addr 0x700000; fdt resize; fdt chosen; " \ - "bootz 0x800000 - 0x700000" - -#define CONFIG_MTDPARTS \ - "mtdparts=orion_nand:" \ - "0xe0000@0x0(uboot)," \ - "0x20000@0xe0000(uboot_env)," \ - "0x100000@0x100000(second_stage_uboot)," \ - "-@0x200000(root)\0" + "run bootcmd_uenv; run bootcmd_usb; usb stop; run bootcmd_sata; reset" #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ + "arcNumber=4931\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-nsa310s.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS \ - "kernel=/boot/zImage\0" \ - "fdt=/boot/nsa310s.dtb\0" \ - "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" + "mtdparts=mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store)," \ + "0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)\0"\ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" -/* Ethernet driver configuration */ +/* + * Ethernet Driver configuration + */ #ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 1 +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x1 #define CONFIG_PHY_GIGE -#define CONFIG_RESET_PHY_R +#define CONFIG_NETCONSOLE #endif /* CONFIG_CMD_NET */ -/* SATA driver configuration */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /* CONFIG_IDE */ +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO -/* RTC driver configuration */ +/* + * Date Time + */ #ifdef CONFIG_CMD_DATE #define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS #endif /* CONFIG_CMD_DATE */ #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nsa320.h b/include/configs/nsa320.h new file mode 100644 index 0000000000..7522545b6a --- /dev/null +++ b/include/configs/nsa320.h @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2015-2017 bodhi + * + * Based on + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.h originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_NSA320_H +#define _CONFIG_NSA320_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_NSA320 /* Machine type */ +#define CONFIG_MACH_TYPE MACH_TYPE_NSA320 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Misc Configuration Options + */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "NSA320> " /* Command Prompt */ + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; usb stop; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=3956\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-nsa320.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store)," \ + "0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)\0"\ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x1 +#define CONFIG_PHY_GIGE +#define CONFIG_NETCONSOLE +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NSA320_H */ diff --git a/include/configs/nsa325.h b/include/configs/nsa325.h new file mode 100644 index 0000000000..3043dd6ce3 --- /dev/null +++ b/include/configs/nsa325.h @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2016-2017 bodhi + * + * Based on + * Copyright (C) 2014 Jason Plum + * Based on + * Copyright (C) 2012 Peter Schildmann + * + * Based on guruplug.h originally written by + * Siddarth Gore + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_NSA325_H +#define _CONFIG_NSA325_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_NSA325 /* Machine type */ +#define CONFIG_MACH_TYPE MACH_TYPE_NSA325 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Misc Configuration Options + */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "NSA325> " /* Command Prompt */ + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; usb stop; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=4495\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-nsa325.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store)," \ + "0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)\0"\ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x1 +#define CONFIG_PHY_GIGE +#define CONFIG_NETCONSOLE +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NSA325_H */ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index f94e74f0fc..aebe0397b1 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2014-2017 bodhi + * Based on + * * Copyright (C) 2012 * David Purdy * @@ -17,6 +20,7 @@ * Machine type definition and ID */ #define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 +#define CONFIG_IDENT_STRING "\nPogo E02" /* * High Level Configuration Options (easy to change) @@ -30,7 +34,14 @@ */ #define CONFIG_SYS_MVFS #define CONFIG_CMD_NAND - +#define CONFIG_CMD_DATE +/* + Hush parser + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -48,23 +59,59 @@ #endif #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_OFFSET 0xC0000 /* env starts here */ /* * Default environment variables */ + #define CONFIG_BOOTCOMMAND \ - "setenv bootargs $(bootargs_console); " \ - "run bootcmd_usb; " \ - "bootm 0x00800000 0x01100000" + "run bootcmd_uenv; run bootcmd_usb; reset" #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ - "32M(rootfs),-(data)\0"\ - "mtdids=nand0=orion_nand\0"\ - "bootargs_console=console=ttyS0,115200\0" \ - "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ - "ext2load usb 0:1 0x01100000 /uInitrd\0" + "arcNumber=2097\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=console=ttyS0,115200\0" \ + "device=0:1\0" \ + "devices=usb\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-pogo_e02.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" /* * Ethernet Driver configuration @@ -77,6 +124,8 @@ /* * File system */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ @@ -84,4 +133,13 @@ #define CONFIG_CMD_MTDPARTS #define CONFIG_LZO +/* + * Date Time + * */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + #endif /* _CONFIG_POGO_E02_H */ diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h new file mode 100644 index 0000000000..2157db4626 --- /dev/null +++ b/include/configs/pogo_v4.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2014-2017 bodhi + * Based on + * + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#ifndef _CONFIG_POGO_V4_H +#define _CONFIG_POGO_V4_H + +/* + * Machine type definition and ID + */ +#define MACH_TYPE_POGO_V4 3960 +#define CONFIG_MACH_TYPE MACH_TYPE_POGO_V4 + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ +#define CONFIG_KW88F6192 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "Pogov4> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=3960\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=ttyS0,115200\0"\ + "device=0:1\0" \ + "devices=usb ide mmc\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-pogoplug_v4\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)\0"\ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * SATA + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +/* + * Kirkwood GPIO + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * SDIO/MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + +#endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 9d2c106d46..96c9120e3e 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -1,6 +1,7 @@ -/* - * (C) Copyright 2009-2014 - * Gerald Kerma +/* Copyright (C) 2015-2017 bodhi + * + * Based on + * (C) Copyright 2009 * Marvell Semiconductor * Written-by: Prafulla Wadaskar * @@ -14,22 +15,28 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * Commands configuration */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* - * Standard filesystems - */ -#define CONFIG_SYS_MVFS - -/* - * mv-plug-common.h should be defined after CMD configs since it used them + * mv-common.h should be defined after CMD configs since it used them * to enable certain macros */ -#include "mv-plug-common.h" +#include "mv-common.h" /* * Environment variables configurations @@ -45,31 +52,60 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x80000 -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ +#define CONFIG_ENV_ADDR 0xC0000 +#define CONFIG_ENV_OFFSET 0xC0000 /* env starts here */ /* * Default environment variables */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_MTDPARTS \ - "orion_nand:512K(uboot)," \ - "512K(env),4M(kernel)," \ - "-(rootfs)\0" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" -#define MTDIDS_DEFAULT "nand0=orion_nand" +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; reset" -#define MTDPARTS_DEFAULT \ - "mtdparts="CONFIG_MTDPARTS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=2097\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=ttyS0,115200\0"\ + "device=0:1\0" \ + "devices=usb ide mmc\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-sheevaplug.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)\0" \ + "partition=nand0,2\0" \ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" /* * Ethernet Driver configuration @@ -79,6 +115,27 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * Date Time + * */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + /* * SDIO/MMC Card Configuration */ @@ -100,3 +157,4 @@ #endif /* CONFIG_IDE */ #endif /* _CONFIG_SHEEVAPLUG_H */ + diff --git a/include/configs/t5325.h b/include/configs/t5325.h new file mode 100644 index 0000000000..ba9a3377cd --- /dev/null +++ b/include/configs/t5325.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2016-2017 bodhi + * + * Based on sheevaplug.h originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_T5325_H +#define _CONFIG_T5325_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_T5325 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#undef CONFIG_ENV_SPI_MAX_HZ +#define CONFIG_ENV_SPI_MAX_HZ 86000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH_MTD +#define CONFIG_CMD_SF + +#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DATE +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_ADDR 0xC0000 +#define CONFIG_ENV_OFFSET 0xC0000 /* env starts here */ + +/* + * + * Default environment variables + */ + +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_uenv; run bootcmd_usb; reset" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=2846\0" \ + "bootcmd_exec=run load_uimage; if run load_initrd; then if run load_dtb; then bootm $load_uimage_addr $load_initrd_addr $load_dtb_addr; else bootm $load_uimage_addr $load_initrd_addr; fi; else if run load_dtb; then bootm $load_uimage_addr - $load_dtb_addr; else bootm$load_uimage_addr; fi; fi\0" \ + "bootcmd=run bootcmd_uenv; run scan_disk; run set_bootargs; run bootcmd_exec; reset\0" \ + "bootcmd_uenv=run uenv_load; if test $uenv_loaded -eq 1; then run uenv_import; fi\0" \ + "bootdelay=10\0" \ + "bootdev=usb\0" \ + "console=ttyS0,115200\0"\ + "device=0:1\0" \ + "devices=usb ide\0" \ + "disks=0 1 2 3\0" \ + "ethact=egiga0\0" \ + "ethaddr=52:3b:20:9c:11:51\0" \ + "if_netconsole=ping $serverip\0" \ + "ipaddr=192.168.0.231\0" \ + "led_error=orange blinking\0" \ + "led_exit=green off\0" \ + "led_init=green blinking\0" \ + "dtb_file=/boot/dts/kirkwood-t5325.dtb\0" \ + "load_dtb_addr=0x1c00000\0" \ + "load_initrd_addr=0x1100000\0" \ + "load_uimage_addr=0x800000\0" \ + "load_dtb=echo loading DTB $dtb_file ...; load $bootdev $device $load_dtb_addr $dtb_file\0" \ + "load_initrd=echo loading uInitrd ...; load $bootdev $device $load_initrd_addr /boot/uInitrd\0" \ + "load_uimage=echo loading uImage ...; load $bootdev $device $load_uimage_addr /boot/uImage\0" \ + "mainlineLinux=yes\0" \ + "mtdparts=mtdparts=spi0.0:512K(uboot),256K(sdd_firmware),64K(uboot_env),64K(permanent_uboot_env),64K(hp_env)\0"\ + "preboot_nc=run if_netconsole start_netconsole\0" \ + "scan_disk=echo running scan_disk ...; scan_done=0; setenv scan_usb \"usb start\"; setenv scan_ide \"ide reset\"; setenv scan_mmc \"mmc rescan\"; for dev in $devices; do if test $scan_done -eq 0; then echo Scan device $dev; run scan_$dev; for disknum in $disks; do if test $scan_done -eq 0; then echo device $dev $disknum:1; if load $dev $disknum:1 $load_uimage_addr /boot/uImage 1; then scan_done=1; echo Found bootable drive on $dev $disknum; setenv device $disknum:1; setenv bootdev $dev; fi; fi; done; fi; done\0" \ + "serverip=192.168.0.220\0" \ + "set_bootargs=setenv bootargs console=ttyS0,115200 root=LABEL=rootfs rootdelay=10 $mtdparts $custom_params\0" \ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10; setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "uenv_addr=0x810000\0" \ + "uenv_import=echo importing envs ...; env import -t $uenv_addr $filesize\0" \ + "uenv_init_devices=setenv init_usb \"usb start\"; setenv init_ide \"ide reset\"; setenv init_mmc \"mmc rescan\"; for devtype in $devices; do run init_$devtype; done;\0" \ + "uenv_load=run uenv_init_devices; setenv uenv_loaded 0; for devtype in $devices; do for disknum in 0; do run uenv_read_disk; done; done;\0" \ + "uenv_read_disk=if test $devtype -eq mmc; then if $devtype part; then run uenv_read; fi; else if $devtype part $disknum; then run uenv_read; fi; fi\0" \ + "uenv_read=echo loading envs from $devtype $disknum ...; if load $devtype $disknum:1 $uenv_addr /boot/uEnv.txt; then setenv uenv_loaded 1; fi\0" \ + "usb_ready_retry=15\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x08 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + + +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + +/* + * Date Time + * + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_T5325_H */ diff --git a/include/kirkwood_mmc.h b/include/kirkwood_mmc.h new file mode 100644 index 0000000000..4f0d80406c --- /dev/null +++ b/include/kirkwood_mmc.h @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2014 + * + * Based on + * + * (C) Copyright 2012 + * Marvell Semiconductor + * Written-by: Gérald Kerma + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KIRKWOOD_MMC_H__ +#define __KIRKWOOD_MMC_H__ + +/* + * Clock rates + */ + +#define KW_MMC_CLOCKRATE_MAX 50000000 +#define KW_MMC_BASE_DIV_MAX 0x7ff +#define KW_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK +#define KW_MMC_BASE_FAST_CLK_100 100000000 +#define KW_MMC_BASE_FAST_CLK_200 200000000 + +/* + * Macros + */ +#define kwsd_write(offs, val) writel(val, CONFIG_SYS_MMC_BASE + (offs)) +#define kwsd_read(offs) readl(CONFIG_SYS_MMC_BASE + (offs)) + +#define KW_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) + +/* SDIO register */ +#define SDIO_SYS_ADDR_LOW 0x000 +#define SDIO_SYS_ADDR_HI 0x004 +#define SDIO_BLK_SIZE 0x008 +#define SDIO_BLK_COUNT 0x00c +#define SDIO_ARG_LOW 0x010 +#define SDIO_ARG_HI 0x014 +#define SDIO_XFER_MODE 0x018 +#define SDIO_CMD 0x01c +#define SDIO_RSP(i) (0x020 + ((i)<<2)) +#define SDIO_RSP0 0x020 +#define SDIO_RSP1 0x024 +#define SDIO_RSP2 0x028 +#define SDIO_RSP3 0x02c +#define SDIO_RSP4 0x030 +#define SDIO_RSP5 0x034 +#define SDIO_RSP6 0x038 +#define SDIO_RSP7 0x03c +#define SDIO_BUF_DATA_PORT 0x040 +#define SDIO_RSVED 0x044 +#define SDIO_HW_STATE 0x048 +#define SDIO_PRESENT_STATE0 0x048 +#define SDIO_PRESENT_STATE1 0x04c +#define SDIO_HOST_CTRL 0x050 +#define SDIO_BLK_GAP_CTRL 0x054 +#define SDIO_CLK_CTRL 0x058 +#define SDIO_SW_RESET 0x05c +#define SDIO_NOR_INTR_STATUS 0x060 +#define SDIO_ERR_INTR_STATUS 0x064 +#define SDIO_NOR_STATUS_EN 0x068 +#define SDIO_ERR_STATUS_EN 0x06c +#define SDIO_NOR_INTR_EN 0x070 +#define SDIO_ERR_INTR_EN 0x074 +#define SDIO_AUTOCMD12_ERR_STATUS 0x078 +#define SDIO_CURR_BYTE_LEFT 0x07c +#define SDIO_CURR_BLK_LEFT 0x080 +#define SDIO_AUTOCMD12_ARG_LOW 0x084 +#define SDIO_AUTOCMD12_ARG_HI 0x088 +#define SDIO_AUTOCMD12_INDEX 0x08c +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) +#define SDIO_AUTO_RSP0 0x090 +#define SDIO_AUTO_RSP1 0x094 +#define SDIO_AUTO_RSP2 0x098 +#define SDIO_CLK_DIV 0x128 + +#define WINDOW_CTRL(i) (0x108 + ((i) << 3)) +#define WINDOW_BASE(i) (0x10c + ((i) << 3)) + +/* SDIO_PRESENT_STATE */ +#define CARD_BUSY (1 << 1) +#define CMD_INHIBIT (1 << 0) +#define CMD_TXACTIVE (1 << 8) +#define CMD_RXACTIVE (1 << 9) +#define CMD_AUTOCMD12ACTIVE (1 << 14) +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ + CMD_RXACTIVE | \ + CMD_TXACTIVE | \ + CMD_INHIBIT | \ + CARD_BUSY) + +/* + * SDIO_CMD + */ + +#define SDIO_CMD_RSP_NONE (0 << 0) +#define SDIO_CMD_RSP_136 (1 << 0) +#define SDIO_CMD_RSP_48 (2 << 0) +#define SDIO_CMD_RSP_48BUSY (3 << 0) + +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2) +#define SDIO_CMD_CHECK_CMDCRC (1 << 3) +#define SDIO_CMD_INDX_CHECK (1 << 4) +#define SDIO_CMD_DATA_PRESENT (1 << 5) +#define SDIO_UNEXPECTED_RESP (1 << 7) + +#define SDIO_CMD_INDEX(x) ((x) << 8) + +/* + * SDIO_XFER_MODE + */ + +#define SDIO_XFER_MODE_STOP_CLK (1 << 5) +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) +#define SDIO_XFER_MODE_TO_HOST (1 << 4) +#define SDIO_XFER_MODE_DMA (0 << 6) + +/* + * SDIO_HOST_CTRL + */ + +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) + +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) + +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) +#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) + +#define SDIO_HOST_CTRL_TMOUT_MAX 0xf +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) + +/* + * SDIO_SW_RESET + */ + +#define SDIO_SW_RESET_NOW (1 << 8) + +/* + * Normal interrupt status bits + */ + +#define SDIO_NOR_ERROR (1 << 15) +#define SDIO_NOR_UNEXP_RSP (1 << 14) +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13) +#define SDIO_NOR_SUSPEND_ON (1 << 12) +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) +#define SDIO_NOR_READ_WAIT_ON (1 << 9) +#define SDIO_NOR_CARD_INT (1 << 8) +#define SDIO_NOR_READ_READY (1 << 5) +#define SDIO_NOR_WRITE_READY (1 << 4) +#define SDIO_NOR_DMA_INI (1 << 3) +#define SDIO_NOR_BLK_GAP_EVT (1 << 2) +#define SDIO_NOR_XFER_DONE (1 << 1) +#define SDIO_NOR_CMD_DONE (1 << 0) + +/* + * Error status bits + */ + +#define SDIO_ERR_CRC_STATUS (1 << 14) +#define SDIO_ERR_CRC_STARTBIT (1 << 13) +#define SDIO_ERR_CRC_ENDBIT (1 << 12) +#define SDIO_ERR_RESP_TBIT (1 << 11) +#define SDIO_ERR_XFER_SIZE (1 << 10) +#define SDIO_ERR_CMD_STARTBIT (1 << 9) +#define SDIO_ERR_AUTOCMD12 (1 << 8) +#define SDIO_ERR_DATA_ENDBIT (1 << 6) +#define SDIO_ERR_DATA_CRC (1 << 5) +#define SDIO_ERR_DATA_TIMEOUT (1 << 4) +#define SDIO_ERR_CMD_INDEX (1 << 3) +#define SDIO_ERR_CMD_ENDBIT (1 << 2) +#define SDIO_ERR_CMD_CRC (1 << 1) +#define SDIO_ERR_CMD_TIMEOUT (1 << 0) +#define SDIO_POLL_MASK 0xffff /* enable all for polling */ + +#define MMC_BLOCK_SIZE 512 + +/* + * CMD12 error status bits + */ + +#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) +#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) +#define SDIO_AUTOCMD12_ERR_CRC (1 << 2) +#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) +#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_BUSMODE_OPENDRAIN 1 +#define MMC_BUSMODE_PUSHPULL 2 + +#define MMC_BUS_WIDTH_1 0 +#define MMC_BUS_WIDTH_4 2 +#define MMC_BUS_WIDTH_8 3 + +#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ +#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ +#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ +#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ +#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ +#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ + +#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ +#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ +#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ + /* DDR mode at 1.8V */ +#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ + /* DDR mode at 1.2V */ +#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ +#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ +#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ +#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ +#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ +#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ +#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ +#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ +#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ +#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ +#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ + +/* + * Functions prototypes + * + * Original patch had static function declarations in this header file. + * Those should rather not be declared in the header as they only cause compiler warnings. + */ +int kw_mmc_initialize(bd_t *bis); + +#endif /* __KIRKWOOD_MMC_H__ */ diff --git a/include/usb.h b/include/usb.h index 62f051fe53..a697eb019b 100644 --- a/include/usb.h +++ b/include/usb.h @@ -141,6 +141,7 @@ struct usb_device { int act_len; /* transferred bytes */ int maxchild; /* Number of ports if hub */ int portnr; /* Port number, 1=first */ + int extra_timout; /* add to timeout in ehci_submit_async */ #ifndef CONFIG_DM_USB /* parent hub, or NULL if this is the root hub */ struct usb_device *parent; diff --git a/include/usb_defs.h b/include/usb_defs.h index 8214ba9bf5..e09a7e64e4 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -197,6 +197,7 @@ #define USB_ST_NAK_REC 0x10 /* NAK Received*/ #define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */ #define USB_ST_BIT_ERR 0x40 /* Bitstuff error */ +#define USB_ST_XACTERR 0x80 /* XACTERR error */ #define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */