ALU-Verification-using-Systemverilog

ITI Digital IC Verification Graduation Project This repo includes the ALU design , Verification plan, Testbench and coverage reports

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
ALU.v		ALU.v
ALU_Verification_Plan.xlsx		ALU_Verification_Plan.xlsx
ALU_tb.sv		ALU_tb.sv
README.md		README.md
coverage.svh		coverage.svh
dashboard.txt		dashboard.txt
driver.svh		driver.svh
environment.svh		environment.svh
generator.svh		generator.svh
groups.txt		groups.txt
grpinfo.txt		grpinfo.txt
monitor.svh		monitor.svh
scoreboard.svh		scoreboard.svh
test.svh		test.svh
test_pkg.sv		test_pkg.sv
transaction.svh		transaction.svh

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