From 31ddb4738863aa420e2f95c87ce97b937a3a46e1 Mon Sep 17 00:00:00 2001
From: Kunyan Liu <116126768+kliuMsft@users.noreply.github.com>
Date: Sun, 15 Oct 2023 12:24:54 -0700
Subject: [PATCH] Update Readme.md

---
 sim/verilator/Readme.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/verilator/Readme.md b/sim/verilator/Readme.md
index c66f8db..31a8f5a 100644
--- a/sim/verilator/Readme.md
+++ b/sim/verilator/Readme.md
@@ -7,7 +7,7 @@ Steps to run a verilog simulation:
 You can run the scripts from any where as long as the $DesignRoot in vgen script points to the right locaiton of verilog files. 
 
 The verilog wrapper (swci_vtb) takes care of printing out UART messages. 
-To stop simulation, write any value >= 0x80 to UART (0x8f00b000). The C++ wrapper (swci_main) exits value is the lower 7-bit of the byte written to UART. There is also a timeout (defined MAX_SIM_TIME in swci_main.cc) which defaults to 100M cycles, the exit code for timeout is 0xfe. 
+To stop simulation, write any value >= 0x80 to UART (0x8f00b000). The C++ wrapper (swci_main) exit value is the lower 7-bit of the byte written to UART. There is also a timeout (defined MAX_SIM_TIME in swci_main.cc) which defaults to 100M cycles, the exit code for timeout is 0xfe. 
 
 To enable ibex traces, insert a "+define+RVFI=1" in all.f (above line 11).