From 9d8226478d6cf317dd3e524c099141a1c6eb0816 Mon Sep 17 00:00:00 2001
From: fox8091 <bfox200012@gmail.com>
Date: Tue, 16 Feb 2016 03:09:38 -0600
Subject: [PATCH] Update start.s

---
 source/start.s | 56 +++++++++++++++++++-------------------------------
 1 file changed, 21 insertions(+), 35 deletions(-)

diff --git a/source/start.s b/source/start.s
index 70015b0..6633f9c 100644
--- a/source/start.s
+++ b/source/start.s
@@ -5,42 +5,28 @@ _start:
     @ Change the stack pointer
     mov sp, #0x27000000
 
-    @ Sets MPU permissions and cache settings
-    ldr r0, =0xFFFF001D			@ ffff0000 32k
-    ldr r1, =0x01FF801D			@ 01ff8000 32k
-    ldr r2, =0x08000027			@ 08000000 1M
-    ldr r3, =0x10000021			@ 10000000 128k
-    ldr r4, =0x10100025			@ 10100000 512k
-    ldr r5, =0x20000035			@ 20000000 128M
-    ldr r6, =0x2800801B			@ 28008000 16k
-    ldr r7, =0x1800002D			@ 18000000 8M
-    ldr r8, =0x33333336
-    ldr r9, =0x60600666
-    mov r10, #0x25
-    mov r11, #0x25
-    mov r12, #0x25
-    mcr p15, 0, r0, c6, c0, 0
-    mcr p15, 0, r1, c6, c1, 0
-    mcr p15, 0, r2, c6, c2, 0
-    mcr p15, 0, r3, c6, c3, 0
-    mcr p15, 0, r4, c6, c4, 0
-    mcr p15, 0, r5, c6, c5, 0
-    mcr p15, 0, r6, c6, c6, 0
-    mcr p15, 0, r7, c6, c7, 0
-    mcr p15, 0, r8, c5, c0, 2	@ Enable data r/w for all regions
-    mcr p15, 0, r9, c5, c0, 3	@ Enable inst read for 0, 1, 2, 5, 7
-    mcr p15, 0, r10, c3, c0, 0	@ Write bufferable 0, 2, 5
-    mcr p15, 0, r11, c2, c0, 0	@ Data cacheable 0, 2, 5
-    mcr p15, 0, r12, c2, c0, 1	@ Inst cacheable 0, 2, 5
+    @ Give read/write access to all the memory regions
+    ldr r5, =0x33333333
+    mcr p15, 0, r5, c5, c0, 2 @ write data access
+    mcr p15, 0, r5, c5, c0, 3 @ write instruction access
+    
+    @ Enable caches
+    mrc p15, 0, r4, c1, c0, 0  @ read control register
+    orr r4, r4, #(1<<12)       @ - instruction cache enable
+    orr r4, r4, #(1<<2)        @ - data cache enable
+    orr r4, r4, #(1<<0)        @ - mpu enable
+    mcr p15, 0, r4, c1, c0, 0  @ write control register
+    
+    @ Flush caches
+    mov r5, #0
+    mcr p15, 0, r5, c7, c5, 0  @ flush I-cache
+    mcr p15, 0, r5, c7, c6, 0  @ flush D-cache
+    mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
 
-    @ Enables all the settings we specified above
-    ldr r0, =0x5307D
-    mcr p15, 0, r0, c1, c0, 0	@ cp15 ctl register enable mpu, enable cache and use alt vector table
-
-    @ Undocumented: Fixes mounting of SDMC
-    ldr r0, =0x10000020
-    mov r1, #0x340
-    str r1, [r0]
+    @ Fixes mounting of SDMC
+	ldr r0, =0x10000020
+	mov r1, #0x340
+	str r1, [r0]
 
     bl main