Verilog Experiments
Verilog
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README.md
adder.v
addsub.v
alu.v
alu_tb.v
binenc.v
binenc_tb.v
defines.v
divider.v
divider_tb.v
generic_n_way_cache.v
generic_n_way_cache_tb.v
multiplier.v
multiplier_tb.v
regfile.v
register.v
shifter.v
shifter_tb.v