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Commits on Jul 7, 2019
  1. Improve OS X compatibility

    mjg59 committed Jul 7, 2019
    OS X makes assumptions about ACPI naming and also likes to have various
    device properties present. Add some quick hacks to make it happier.
    
    Change-Id: I7f5b108b4f8ccb600defe986ebf16b68a5d7cc78
  2. Add support for AppleSMC to the X210 platform

    mjg59 committed Jul 5, 2019
    Enabling the Apple SMC emulation requires chipset-specific configuration
    for the I/O traps and mainboard-specific integration of the ACPI support.
    Add these to the X210 mainboard code.
    
    Change-Id: I812a4d68a661a512fe682e7775ab820f104ba8ac
  3. Add support for the 51nb X210

    mjg59 committed Jul 24, 2018
    The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
    based on a modern Kabylake CPU. It also ships with no firmware protection,
    (IFD is fully unlocked, no protected regions are set, no Bootguard),
    making it an ideal coreboot target. This port is based on the support for
    the Skylake-based Purism Librem 13v3, with the following significant
    changes:
    
    * EC firmware is contained within the system SPI flash, and so a blob of
      EC firmware must be injected to a defined location during image build.
    * GPIO layout is different - this is currently just a raw import of the
      GPIO configuration from the vendor firmware
    * The system has two DIMMs, so an additional SPD address has been added
    * The USB port layout is different
    * The EC must be enabled at boot time through SuperIO-style logical device
      configuration
    * EC register layout is different, necessitating changes in the ACPI tables
    * The HDA pins are different
    * The genx_dec config is different
    
    All hardware appears to work as expected, although the SD reader is
    untested.
    
    Signed-off-by: Matthew Garrett <mjg59@google.com>
    Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
  4. Enable SMM-based AppleSMC

    mjg59 committed Jul 5, 2019
    Add an SMI handler that can deal with the AppleSMC driver, and assume that
    any accesses to IOTRAP(2) are intended for it. Add MONITOR_STS_BIT to the
    mask of SMIs we're interested in even after we've transitioned to ACPI mode
    in order to receive these events at runtime.
    
    Change-Id: I21ab566a4831ef4339cb8aafe26d0bda59627445
  5. smm: rework find_save_state()

    mjg59 committed Jul 5, 2019
    find_save_state() currently assumes that all accesses will be writes to the
    APM_CNT port. Generalise it so we can find reads or writes to any port.
    
    Change-Id: Ie4b6be6f7ea305d330f469f83e4af9d984824cf1
  6. Add AppleSMC emulation driver.

    mjg59 committed Jul 3, 2019
    OS X assumes the presence of an Apple System Management Controller, but
    non-Apple hardware doesn't have one. Add code for emulating one, along with
    the ACPI glue that OS X needs in order to detect its presence. This will
    then be hooked up into System Management Mode for transparent emulation.
    
    Change-Id: Ib7dd7bf8ec2cd86a07769911ae08fc8d8e5611f7
  7. Fix build failure in the smmstore code

    mjg59 committed Jul 7, 2019
    Change-Id: I2aba4452768da8ed2a62655f683bfbf026d75612
  8. drivers/smmstore: Fix some issues

    ArthurHeymans authored and mjg59 committed Dec 26, 2018
    This fixes the following:
    - Fix smmstore_read_region to actually read stuff
    - Make the API ARCH independent (no dependency on size_t)
    - clean up the code a little
    - Change the loglevel for non error messages to BIOS_DEBUG
    
    Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
    Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
  9. sb/intel/common/smihandler: Hook up smmstore

    ArthurHeymans authored and mjg59 committed Dec 3, 2018
    TESTED on Asus P5QC
    
    Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2
    Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Commits on Jul 3, 2019
  1. soc/amd/common/lpc: Add Picasso ID

    Marshall Dawson authored and martinlroth committed Jun 20, 2019
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33758
    Reviewed-by: Martin Roth <martinroth@google.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  2. soc/amd/common/iommu: Add Picasso ID

    Marshall Dawson authored and martinlroth committed Jun 20, 2019
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33757
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
  3. soc/amd/common/hda: Add Picasso IDs

    Marshall Dawson authored and martinlroth committed Jun 20, 2019
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33756
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
  4. soc/amd/picasso: Remove all PSP runtime functions

    Marshall Dawson authored and martinlroth committed Jun 13, 2019
    Remove the mailbox call to notify the PSP that DRAM is ready.  This
    is not supported on Family 17h.
    
    Remove the selectable SMU firmware.  This is a feature of the PSP
    bootloader and the standard bootloader doesn't contain the ability.
    
    Clean up additional mentions of PSP within picasso.
    
    Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
  5. soc/amd/picasso: Remove fanless SKU option

    Marshall Dawson authored and martinlroth committed Jun 11, 2019
    The command line options for picasso will look different than
    stoneyridge.  Remove the fanned/fanless distinction to simplify
    the makefile.
    
    Picasso will use subprograms instead of fanned/fanless SKUs.
    
    Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753
    Reviewed-by: Martin Roth <martinroth@google.com>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  6. soc/amd/picasso: Remove SD controller

    Marshall Dawson authored and martinlroth committed Jul 1, 2019
    Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Martin Roth <martinroth@google.com>
  7. soc/amd/picasso: Add xhci1 and remove ehci

    Marshall Dawson authored and martinlroth committed Jun 30, 2019
    Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33987
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Martin Roth <martinroth@google.com>
  8. soc/amd/picasso: Remove most stoneyridge USB

    Marshall Dawson authored and martinlroth committed Jun 11, 2019
    Picasso doesn't implement the AcpiMmio XHCI_PM registers.  Remove
    source that uses these.  Remove USB devices from the AOAC registers.
    Remove the D0/D3 support from ASL, including all supporting xHCI
    firmware loading support.  Remove xHCI firmware from amdfw.rom.
    
    Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
  9. soc/amd/picasso: Remove stoneyridge GEC

    Marshall Dawson authored and martinlroth committed Jun 11, 2019
    Remove the hudson-style support for the Gigabit Ethernet Controller.
    
    Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
  10. soc/amd/picasso: Change all remaining soc names

    Marshall Dawson authored and martinlroth committed Jun 11, 2019
    Convert all remaining stoneyridge names to picasso.
    
    Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
  11. util/cbfstool: Add AMD BIOS compression tool for PSP

    Marshall Dawson authored and martinlroth committed Mar 19, 2019
    Add a utility to generate a compressed BIOS image for AMD Family 17h.
    
    If the input is an elf file, the utility extracts the program portion
    for compression.  Otherwise the file is compressed as-is.
    
    In modern AMD systems, the PSP brings up DRAM then uncompresses the
    BIOS image into memory prior to x86 beginning execution.  The PSP
    supports a zlib engine, and interprets the first 256 bytes as a
    header, where offset 0x14 containing the uncompressed size.  For
    further details, see AMD Platform Security Processor BIOS Architecture
    Design Guide for AMD Family 17h Processors (NDA only, #55758).
    
    BUG=b:127766506
    TEST=Use with WIP Picasso
    
    Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Raul Rangel <rrangel@chromium.org>
    Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
  12. aopen/dxplplusu: Replace use of dev_find_slot()

    kmalkki committed Jul 3, 2019
    To use fixed PCI bus numbers is always invalid.
    
    Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/34002
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
  13. aopen/dxplplusu: Remove PIRQ table

    kmalkki committed Jul 3, 2019
    It was never tested or injected.
    
    Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  14. intel/e7505: Drop debug code

    kmalkki committed Jul 2, 2019
    Only (conditionally) used part was dump_pci_device()
    and that was never particularly useful either.
    
    Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33958
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
  15. soc/intel/skylake: Add Kabylake-R microcode update files

    ArthurHeymans authored and i-c-o-n committed Jul 3, 2019
    This also corrects some CPU naming in comments.
    
    Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8
    Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/34000
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  16. mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMI

    Kevin Chiu authored and furquan-goog committed Jun 17, 2019
    garg 2A2C DB: SKU ID - 1
    garg HDMI DB: SKU ID - 9
    garg LTE  DB: SKU ID - 17
    
    For HDMI SKU9, GPIO needs to be overriden to enable
    DDI1 DDC SDA/SCL.
    
    BUG=b:134912735
    BRANCH=octopus
    TEST=emerge-octopus coreboot chromeos-bootimage
    Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061
    Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33552
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Reviewed-by: Justin TerAvest <teravest@chromium.org>
  17. mb/google/octopus/variants/fleex: Enable EMR function for Grob360S

    Chris Zhou authored and furquan-goog committed Jun 26, 2019
    Enable EMR Pen Stylus function for Grob360S
    
    BUG=b:135968368
    BRANCH=octopus
    TEST=EMR function working normally with HW reworked Fleex.
    
    Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478
    Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33802
    Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  18. mb/google/octopus: Add custom SAR values for Blooguard

    Tony Huang authored and furquan-goog committed Jul 1, 2019
    Google project name is Bloog.
    Bloog is 12-inch LCD.
    Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
    Use sku-id to load the SAR values.
    
    BUG=b:135078377
    BRANCH=octopus
    TEST=build and verify SAR load by sku-id
    
    Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
    Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
  19. vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platforms

    jwerner-chromium committed Jul 1, 2019
    When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on
    some Arm platforms the original working data buffer was in SRAM, which
    stays accessbile for the whole runtime of the system. There is no reason
    to migrate it into CBMEM on those platforms because ramstage and the
    payload could continue to access it in SRAM.
    
    Now that we've had a couple of months of experience with this option, we
    found that most of our Arm platforms have some issue that requires
    migrating anyway, because BL31 often claims SRAM for itself and makes it
    inaccessible to the payload. On the remaining platforms, accessing SRAM
    from the payload is possible but still an issue, because libpayload
    doesn't have enough memory layout information to set up proper page
    tables for it, so we're accessing it uncached and at risk of alignment
    errors.
    
    Rather than having to figure out how to map the right SRAM range for
    every platform in the payload, let's just get rid of the option.
    memcpy()ing 12KB isn't worth this much hassle.
    
    Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Joel Kitching <kitching@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commits on Jul 2, 2019
  1. sdm845: Update macro definition in CB clock driver

    Akash Asthana authored and jwerner-chromium committed Jun 24, 2019
    Use literals KHz & MHz for kilohertz and megahertz frequency usages
    in macro definition.
    
    Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba
    Signed-off-by: Akash Asthana <akashast@codeaurora.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
  2. arch/x86: Fix spelling error in BERT comment

    Marshall Dawson Idwer Vollering
    Marshall Dawson authored and Idwer Vollering committed Jul 2, 2019
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965
    Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  3. cbfstool: show "preserved" flag in cbfstool layout output

    pgeorgi committed Jun 18, 2019
    The flag is useful for updaters to determine which areas to leave
    alone, such as VPD (vital product data) regions that are set in
    factory and might contain unique (MAC addresses) or hard to obtain
    (calibration output) data.
    
    It's also useful to see which regions are marked as such.
    
    Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6
    Signed-off-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth@google.com>
  4. cpu/amd/msr: Clarify MMIO_CONF shift value

    Marshall Dawson
    Marshall Dawson committed Jul 1, 2019
    MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field.
    Change it to simply 2.  Otherwise its usage winds up evaluating
    to BusRange << (1 << 1).
    
    Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
    Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
    Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
  5. libpayload/usb: Increase USB request timeout to 5 s

    Keith Short Duncan Laurie
    Keith Short authored and Duncan Laurie committed Jun 21, 2019
    Increase the timeout for USB requests to 5 seconds for all USB host
    controllers.
    
    Prior to this fix, the xCHI driver was detecting false timeouts during
    SET ADDRESS requests when nested downstream hubs were connected to the
    xHCI root hub.
    
    BUG=b:124730179
    BRANCH=sarien
    TEST=Build libpayload and depthcharge on sarien/arcada.
    TEST=Without change replicate USB set address timeouts in depthcharge
    when dock and 4K monitor connected (which includes a total of 4 USB
    hubs).  With timeout fix, depthcharge boots OS with no USB errors and
    the same USB topology.  Note that this tests xHCI operation only.
    
    Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468
    Signed-off-by: Keith Short <keithshort@chromium.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Julius Werner <jwerner@chromium.org>
  6. arch/riscv: Make RISCV specific options depend on ARCH_RISCV

    ArthurHeymans authored and martinlroth committed Feb 10, 2019
    Also don't define the default as this results in spurious lines in the
    .config.
    
    The only difference in the generated config.h is that for most board
    ARCH_RISCV_M goes from 1 to 0. This should not matter.
    
    Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688
    Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311
    Reviewed-by: Patrick Rudolph <siro@das-labor.org>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  7. drivers/pc80/rtc/mc146818rtc_boot: Use size_t for length

    ElyesH authored and martinlroth committed Jun 26, 2019
    Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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