diff --git a/moPsy_CapBoard/fp-lib-table b/moPsy_CapBoard/fp-lib-table
new file mode 100644
index 0000000..6861554
--- /dev/null
+++ b/moPsy_CapBoard/fp-lib-table
@@ -0,0 +1,4 @@
+(fp_lib_table
+  (lib (name moPsy)(type KiCad)(uri ${KIPRJMOD}/../moPsy.pretty)(options "")(descr ""))
+  (lib (name moPsy_KiCad)(type KiCad)(uri /home/tux/moPsy/resources/moPsy_KiCad)(options "")(descr ""))
+)
diff --git a/moPsy_CapBoard/moPsy_CapBoard-cache.lib b/moPsy_CapBoard/moPsy_CapBoard-cache.lib
new file mode 100644
index 0000000..f77fc06
--- /dev/null
+++ b/moPsy_CapBoard/moPsy_CapBoard-cache.lib
@@ -0,0 +1,70 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Connector_Conn_01x01_Male
+#
+DEF Connector_Conn_01x01_Male J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Connector_Conn_01x01_Male" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*
+$ENDFPLIST
+DRAW
+S 34 5 0 -5 1 1 6 F
+P 2 1 1 6 50 0 34 0 N
+X Pin_1 1 200 0 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_CP
+#
+DEF Device_CP C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "Device_CP" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+S -90 20 90 40 0 1 0 N
+S 90 -20 -90 -40 0 1 0 F
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 110 -50 70 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power_VCC
+#
+DEF power_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_VEE
+#
+DEF power_VEE #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_VEE" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 0 0 0 100 N
+P 4 0 1 0 30 50 -30 50 0 100 30 50 F
+X VEE 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/moPsy_CapBoard/moPsy_CapBoard.kicad_pcb b/moPsy_CapBoard/moPsy_CapBoard.kicad_pcb
new file mode 100644
index 0000000..5d6c033
--- /dev/null
+++ b/moPsy_CapBoard/moPsy_CapBoard.kicad_pcb
@@ -0,0 +1,1680 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.1.9+dfsg1-1)
+
+  (general
+    (thickness 1.6)
+    (drawings 16)
+    (tracks 0)
+    (zones 0)
+    (modules 11)
+    (nets 3)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal hide)
+    (31 B.Cu signal hide)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 4 4)
+    (pad_drill 2)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (grid_origin 119.38 63.5)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 VCC)
+  (net 2 VEE)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net VCC)
+    (add_net VEE)
+  )
+
+  (module moPsy_KiCad:moPsy_logo_kicad_20x09_FSilk (layer B.Cu) (tedit 0) (tstamp 60CB3C53)
+    (at 118.88 63 180)
+    (fp_text reference Ref** (at 0 0) (layer B.SilkS) hide
+      (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value Val** (at 0 0) (layer B.SilkS) hide
+      (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror))
+    )
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+  )
+
+  (module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60CB39B5)
+    (at 145.38 54.5)
+    (descr "Mounting Hole 3.2mm, no annular, M3")
+    (tags "mounting hole 3.2mm no annular m3")
+    (attr virtual)
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+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value MountingHole_3.2mm_M3 (at 0 4.2) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
+    (fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0.3 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
+  )
+
+  (module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60CB39A7)
+    (at 145.38 72.5)
+    (descr "Mounting Hole 3.2mm, no annular, M3")
+    (tags "mounting hole 3.2mm no annular m3")
+    (attr virtual)
+    (fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value MountingHole_3.2mm_M3 (at 0 4.2) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
+    (fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
+    (fp_text user %R (at 0.3 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
+  )
+
+  (module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60CB3999)
+    (at 92.38 72.5)
+    (descr "Mounting Hole 3.2mm, no annular, M3")
+    (tags "mounting hole 3.2mm no annular m3")
+    (attr virtual)
+    (fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value MountingHole_3.2mm_M3 (at 0 4.2) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
+    (fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0.3 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
+  )
+
+  (module MountingHole:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 60CB3915)
+    (at 92.48 54.7)
+    (descr "Mounting Hole 3.2mm, no annular, M3")
+    (tags "mounting hole 3.2mm no annular m3")
+    (attr virtual)
+    (fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value MountingHole_3.2mm_M3 (at 0 4.2) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
+    (fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
+    (fp_text user %R (at 0.3 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
+  )
+
+  (module Capacitor_THT:CP_Radial_D22.0mm_P10.00mm_SnapIn (layer F.Cu) (tedit 60CA60F4) (tstamp 60CABF7E)
+    (at 105.959338 58.42 270)
+    (descr "CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf")
+    (tags "CP Radial series Radial pin pitch 10.00mm  diameter 22mm Electrolytic Capacitor")
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+    (fp_line (start -5.799337 -7.335) (end -5.799337 -5.135) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 5 0 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0 270) (size 4 4) (drill 2) (layers *.Cu *.Mask)
+      (net 1 VCC) (zone_connect 2))
+    (pad 2 thru_hole circle (at 10 0 270) (size 4 4) (drill 2) (layers *.Cu *.Mask)
+      (net 2 VEE) (zone_connect 2))
+    (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D22.0mm_P10.00mm_SnapIn.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_THT:CP_Radial_D22.0mm_P10.00mm_SnapIn (layer F.Cu) (tedit 60CA6100) (tstamp 60CB17B9)
+    (at 132.08 58.42 270)
+    (descr "CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf")
+    (tags "CP Radial series Radial pin pitch 10.00mm  diameter 22mm Electrolytic Capacitor")
+    (path /60CA5AA7)
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+      (effects (font (size 1 1) (thickness 0.15)))
+    )
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+      (effects (font (size 1 1) (thickness 0.15)))
+    )
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+    (fp_line (start -4.461475 -4.8275) (end -2.261475 -4.8275) (layer F.Fab) (width 0.1))
+    (fp_circle (center 5 0) (end 16.25 0) (layer F.CrtYd) (width 0.05))
+    (fp_circle (center 5 0) (end 16.12 0) (layer F.SilkS) (width 0.12))
+    (fp_circle (center 5 0) (end 16 0) (layer F.Fab) (width 0.1))
+    (fp_text user %R (at 5 0 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 2 thru_hole circle (at 10 0 270) (size 4 4) (drill 2) (layers *.Cu *.Mask)
+      (net 2 VEE) (zone_connect 2))
+    (pad 1 thru_hole rect (at 0 0 270) (size 4 4) (drill 2) (layers *.Cu *.Mask)
+      (net 1 VCC) (zone_connect 2))
+    (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D22.0mm_P10.00mm_SnapIn.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module "moPsy:Connector FS-P475" (layer F.Cu) (tedit 60CA60E9) (tstamp 60CB3940)
+    (at 86.36 55.88 90)
+    (path /60CA92D8)
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+      (effects (font (size 1 1) (thickness 0.15)))
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+    (fp_line (start 4 -1.5) (end 4 1.5) (layer F.SilkS) (width 0.15))
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+    (fp_line (start -4 1.5) (end -4 -1.5) (layer F.SilkS) (width 0.15))
+    (fp_line (start -1 0) (end 1 0) (layer F.SilkS) (width 0.15))
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+    (fp_line (start -4.5 2) (end -4.5 -2) (layer F.CrtYd) (width 0.15))
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+    (pad 1 thru_hole circle (at -2.5 0 90) (size 2.5 2.5) (drill 1.3) (layers *.Cu *.Mask)
+      (net 1 VCC) (zone_connect 2))
+  )
+
+  (module "moPsy:Connector FS-P475" (layer F.Cu) (tedit 60CA60DD) (tstamp 60CAC131)
+    (at 86.36 71.12 90)
+    (path /60CA964A)
+    (fp_text reference J2 (at 7 0 90) (layer F.SilkS) hide
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+    (fp_line (start 4 1.5) (end -4 1.5) (layer F.SilkS) (width 0.15))
+    (fp_line (start 4 -1.5) (end 4 1.5) (layer F.SilkS) (width 0.15))
+    (fp_line (start -4 -1.5) (end 4 -1.5) (layer F.SilkS) (width 0.15))
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+      (net 2 VEE) (zone_connect 2))
+    (pad 1 thru_hole circle (at 2.5 0 90) (size 2.5 2.5) (drill 1.3) (layers *.Cu *.Mask)
+      (net 2 VEE) (zone_connect 2))
+  )
+
+  (module "moPsy:Connector FS-P475" (layer F.Cu) (tedit 60CA6084) (tstamp 60CB2463)
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+    (path /60CA99C3)
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+
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diff --git a/moPsy_CapBoard/moPsy_CapBoard.pro b/moPsy_CapBoard/moPsy_CapBoard.pro
new file mode 100644
index 0000000..724289e
--- /dev/null
+++ b/moPsy_CapBoard/moPsy_CapBoard.pro
@@ -0,0 +1,248 @@
+update=Wed Jun 16 22:16:26 2021
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
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+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=moPsy_CapBoard.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
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+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
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+Name=In1.Cu
+Type=0
+Enabled=0
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+Type=0
+Enabled=0
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+Name=In3.Cu
+Type=0
+Enabled=0
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+Name=In4.Cu
+Type=0
+Enabled=0
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+Name=In10.Cu
+Type=0
+Enabled=0
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+Name=In11.Cu
+Type=0
+Enabled=0
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+Name=In12.Cu
+Type=0
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+Name=In13.Cu
+Type=0
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+Name=In14.Cu
+Type=0
+Enabled=0
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+Name=In15.Cu
+Type=0
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+Type=0
+Enabled=0
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+Name=In26.Cu
+Type=0
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+Name=In27.Cu
+Type=0
+Enabled=0
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+Name=In28.Cu
+Type=0
+Enabled=0
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+Name=In29.Cu
+Type=0
+Enabled=0
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+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
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+[pcbnew/Layer.Cmts.User]
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+Enabled=1
+[pcbnew/Layer.Eco2.User]
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+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=1
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
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+dPairGap=0.25
+dPairViaGap=0.25
diff --git a/moPsy_CapBoard/moPsy_CapBoard.sch b/moPsy_CapBoard/moPsy_CapBoard.sch
new file mode 100644
index 0000000..9831948
--- /dev/null
+++ b/moPsy_CapBoard/moPsy_CapBoard.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Device:CP C1
+U 1 1 60CA55EA
+P 3000 2350
+F 0 "C1" H 3118 2396 50  0000 L CNN
+F 1 "CP" H 3118 2305 50  0000 L CNN
+F 2 "Capacitor_THT:CP_Radial_D22.0mm_P10.00mm_SnapIn" H 3038 2200 50  0001 C CNN
+F 3 "~" H 3000 2350 50  0001 C CNN
+	1    3000 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:CP C2
+U 1 1 60CA5AA7
+P 3500 2350
+F 0 "C2" H 3618 2396 50  0000 L CNN
+F 1 "CP" H 3618 2305 50  0000 L CNN
+F 2 "Capacitor_THT:CP_Radial_D22.0mm_P10.00mm_SnapIn" H 3538 2200 50  0001 C CNN
+F 3 "~" H 3500 2350 50  0001 C CNN
+	1    3500 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:VCC #PWR0101
+U 1 1 60CA6F03
+P 2800 2000
+F 0 "#PWR0101" H 2800 1850 50  0001 C CNN
+F 1 "VCC" H 2815 2173 50  0000 C CNN
+F 2 "" H 2800 2000 50  0001 C CNN
+F 3 "" H 2800 2000 50  0001 C CNN
+	1    2800 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:VEE #PWR0102
+U 1 1 60CA79AB
+P 2800 2700
+F 0 "#PWR0102" H 2800 2550 50  0001 C CNN
+F 1 "VEE" H 2815 2873 50  0000 C CNN
+F 2 "" H 2800 2700 50  0001 C CNN
+F 3 "" H 2800 2700 50  0001 C CNN
+	1    2800 2700
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	3500 2200 3000 2200
+Wire Wire Line
+	3000 2200 2800 2200
+Wire Wire Line
+	2800 2200 2800 2000
+Connection ~ 3000 2200
+Wire Wire Line
+	3000 2500 2800 2500
+Wire Wire Line
+	2800 2500 2800 2700
+Wire Wire Line
+	3000 2500 3500 2500
+Connection ~ 3000 2500
+$Comp
+L Connector:Conn_01x01_Male J1
+U 1 1 60CA92D8
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+F 0 "J1" H 2208 2381 50  0000 C CNN
+F 1 "Conn_01x01_Male" H 2208 2290 50  0000 C CNN
+F 2 "moPsy:Connector FS-P475" H 2100 2200 50  0001 C CNN
+F 3 "~" H 2100 2200 50  0001 C CNN
+	1    2100 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L Connector:Conn_01x01_Male J2
+U 1 1 60CA964A
+P 2100 2500
+F 0 "J2" H 2208 2681 50  0000 C CNN
+F 1 "Conn_01x01_Male" H 2208 2590 50  0000 C CNN
+F 2 "moPsy:Connector FS-P475" H 2100 2500 50  0001 C CNN
+F 3 "~" H 2100 2500 50  0001 C CNN
+	1    2100 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L Connector:Conn_01x01_Male J3
+U 1 1 60CA99C3
+P 4150 2200
+F 0 "J3" H 4122 2132 50  0000 R CNN
+F 1 "Conn_01x01_Male" H 4122 2223 50  0000 R CNN
+F 2 "moPsy:Connector FS-P475" H 4150 2200 50  0001 C CNN
+F 3 "~" H 4150 2200 50  0001 C CNN
+	1    4150 2200
+	-1   0    0    1   
+$EndComp
+$Comp
+L Connector:Conn_01x01_Male J4
+U 1 1 60CA9CC5
+P 4150 2500
+F 0 "J4" H 4122 2432 50  0000 R CNN
+F 1 "Conn_01x01_Male" H 4122 2523 50  0000 R CNN
+F 2 "moPsy:Connector FS-P475" H 4150 2500 50  0001 C CNN
+F 3 "~" H 4150 2500 50  0001 C CNN
+	1    4150 2500
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2800 2200 2300 2200
+Connection ~ 2800 2200
+Wire Wire Line
+	2800 2500 2300 2500
+Connection ~ 2800 2500
+Wire Wire Line
+	3500 2500 3950 2500
+Connection ~ 3500 2500
+Wire Wire Line
+	3500 2200 3950 2200
+Connection ~ 3500 2200
+$EndSCHEMATC