{"payload":{"header_redesign_enabled":false,"results":[{"id":"401692201","archived":false,"color":"#555555","followers":0,"has_funding_file":false,"hl_name":"mohammadasim98/MIPS-Pipeline-Processor","hl_trunc_description":"A single cycle pipeline processor based on MIPS instruction set architecture (ISA)","language":"C","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":401692201,"name":"MIPS-Pipeline-Processor","owner_id":70431980,"owner_login":"mohammadasim98","updated_at":"2021-09-01T05:15:32.679Z","has_issues":true}},"sponsorable":false,"topics":["mips-assembly","pipeline-processor","mips-architecture","computer-organization","single-cycle-processor","mips-pipline-processor-verilog"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":63,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amohammadasim98%252FMIPS-Pipeline-Processor%2B%2Blanguage%253AC","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/mohammadasim98/MIPS-Pipeline-Processor/star":{"post":"i9Y3CvmdR5sI8xktjKcEHGpqcyS31AaSapPF_gjSgigaXqYwOO4emGEyDaMtb775LI1vWiyNfdG3XePvDOa4Gw"},"/mohammadasim98/MIPS-Pipeline-Processor/unstar":{"post":"3cNNaQY73RUwqLvKhMJYSd3m5d8YSB_SUkJw1I6BEqK2fPz3rCi3j4gdpEAXMUxRqVuMGS0uZ_JZIajt5HZ21Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"nyBqS1hU3lZhS0afZaeJr9fmx4DX6W83IFg4Sx-GFE667OAJ3LqUY5YojCOal7-8pT7nH3qV3hdThoGAi5MpIg"}}},"title":"Repository search results"}