{"payload":{"header_redesign_enabled":false,"results":[{"id":"605360704","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"mohdfahad12328/scpu","hl_trunc_description":"a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works ","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":605360704,"name":"scpu","owner_id":68467301,"owner_login":"mohdfahad12328","updated_at":"2023-05-04T16:53:54.412Z","has_issues":true}},"sponsorable":false,"topics":["cpu","fpga","verilog","instruction-set-architecture","cpu-architecture"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":50,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amohdfahad12328%252Fscpu%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/mohdfahad12328/scpu/star":{"post":"T9gtLmg0yAwqIEdiWSZHlJuJOuiABjMeQ4GEFAjd0snC7mBrfU2TlOrqUUwPVhrAjk_s0ozLkzf7GW9sRPpVIA"},"/mohdfahad12328/scpu/unstar":{"post":"U35GhJznqDIDQqzd0qopPgNc66Z8fzPblFG1Bf0rHTtAvzYs42RdUTlDmA0OyT_uqZQUOVucuovX9H_1Qcuvuw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"9dTladIQk2N3EYyogQSDgkj36DJOGuKuy68MBUUpbDZ8GpigYv-pfVBkYnNuoQiqJssUw936fkVuc12f2ns9Mw"}}},"title":"Repository search results"}