From 9d24fa6e5d39f934623220953caecc080f93e964 Mon Sep 17 00:00:00 2001
From: Fan Ni <nifan.cxl@gmail.com>
Date: Mon, 12 Feb 2024 09:15:17 -0800
Subject: [PATCH] small fix: pmem/ram mess and dcd extent list size bug

---
 drivers/cxl/core/hdm.c  | 4 ++--
 drivers/cxl/core/mbox.c | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 4341a2785363..36ebd22d0ef2 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -560,14 +560,14 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
 	 * configuration
 	 */
 	switch (mode) {
-	case CXL_DECODER_RAM:
+	case CXL_DECODER_PMEM:
 		if (resource_size(&cxlds->pmem_res) == 0) {
 			dev_dbg(dev, "no available pmem capacity\n");
 			rc = -ENXIO;
 			goto out;
 		}
 		break;
-	case CXL_DECODER_PMEM:
+	case CXL_DECODER_RAM:
 		if (resource_size(&cxlds->ram_res) == 0) {
 			dev_dbg(dev, "no available ram capacity\n");
 			rc = -ENXIO;
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index bbec44f3b9f3..ca9c2d05f6e7 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1102,9 +1102,11 @@ static int cxl_send_dc_cap_response(struct cxl_memdev_state *mds,
 		dc_res->extent_list[0].dpa_start = cpu_to_le64(extent->start);
 		memset(dc_res->extent_list[0].reserved, 0, 8);
 		dc_res->extent_list[0].length = cpu_to_le64(range_len(extent));
-	}
+        dc_res->extent_list_size = cpu_to_le32(1);
+	} else {
+        dc_res->extent_list_size = cpu_to_le32(0);
+    }
 
-	dc_res->extent_list_size = cpu_to_le32(1);
 	mbox_cmd = (struct cxl_mbox_cmd) {
 		.opcode = opcode,
 		.size_in = size,