diff --git a/headers/avr32/abdac_101.h b/headers/avr32/abdac_101.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Model        : AP7000
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $ 
+ *
+ ****************************************************************************/
+#ifndef AVR32_ABDAC_101_H_INCLUDED
+#define AVR32_ABDAC_101_H_INCLUDED
+
+#include "avr32/abi.h"
+
+
+/*
+ Note to user:
+
+ The following defines are always generated:
+ - Register offset: AVR32_ABDAC_<register>
+ - Bitfield mask:   AVR32_ABDAC_<register>_<bitfield>
+ - Bitfield offset: AVR32_ABDAC_<register>_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_ABDAC_<register>_<bitfield>_SIZE
+ - Bitfield values: AVR32_ABDAC_<register>_<bitfield>_<value name>
+
+ The following defines are generated if they don't cause ambiguities,
+ i.e. the name is unique, or all values with that name are the same.
+ - Bitfield mask:   AVR32_ABDAC_<bitfield>
+ - Bitfield offset: AVR32_ABDAC_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_ABDAC_<bitfield>_SIZE
+ - Bitfield values: AVR32_ABDAC_<bitfield>_<value name>
+ - Bitfield values: AVR32_ABDAC_<value name>
+
+ All defines are sorted alphabetically.
+*/
+
+
+#define AVR32_ABDAC_CHANNEL0                                          0
+#define AVR32_ABDAC_CHANNEL0_MASK                            0x0000ffff
+#define AVR32_ABDAC_CHANNEL0_OFFSET                                   0
+#define AVR32_ABDAC_CHANNEL0_SIZE                                    16
+#define AVR32_ABDAC_CHANNEL1                                         16
+#define AVR32_ABDAC_CHANNEL1_MASK                            0xffff0000
+#define AVR32_ABDAC_CHANNEL1_OFFSET                                  16
+#define AVR32_ABDAC_CHANNEL1_SIZE                                    16
+#define AVR32_ABDAC_CR                                       0x00000008
+#define AVR32_ABDAC_CR_EN                                            31
+#define AVR32_ABDAC_CR_EN_MASK                               0x80000000
+#define AVR32_ABDAC_CR_EN_OFFSET                                     31
+#define AVR32_ABDAC_CR_EN_SIZE                                        1
+#define AVR32_ABDAC_CR_SWAP                                          30
+#define AVR32_ABDAC_CR_SWAP_MASK                             0x40000000
+#define AVR32_ABDAC_CR_SWAP_OFFSET                                   30
+#define AVR32_ABDAC_CR_SWAP_SIZE                                      1
+#define AVR32_ABDAC_EN                                               31
+#define AVR32_ABDAC_EN_MASK                                  0x80000000
+#define AVR32_ABDAC_EN_OFFSET                                        31
+#define AVR32_ABDAC_EN_SIZE                                           1
+#define AVR32_ABDAC_ICR                                      0x00000018
+#define AVR32_ABDAC_ICR_UNDERRUN                                     28
+#define AVR32_ABDAC_ICR_UNDERRUN_MASK                        0x10000000
+#define AVR32_ABDAC_ICR_UNDERRUN_OFFSET                              28
+#define AVR32_ABDAC_ICR_UNDERRUN_SIZE                                 1
+#define AVR32_ABDAC_IDR                                      0x00000014
+#define AVR32_ABDAC_IDR_TX_READY                                     29
+#define AVR32_ABDAC_IDR_TX_READY_MASK                        0x20000000
+#define AVR32_ABDAC_IDR_TX_READY_OFFSET                              29
+#define AVR32_ABDAC_IDR_TX_READY_SIZE                                 1
+#define AVR32_ABDAC_IDR_UNDERRUN                                     28
+#define AVR32_ABDAC_IDR_UNDERRUN_MASK                        0x10000000
+#define AVR32_ABDAC_IDR_UNDERRUN_OFFSET                              28
+#define AVR32_ABDAC_IDR_UNDERRUN_SIZE                                 1
+#define AVR32_ABDAC_IER                                      0x00000010
+#define AVR32_ABDAC_IER_TX_READY                                     29
+#define AVR32_ABDAC_IER_TX_READY_MASK                        0x20000000
+#define AVR32_ABDAC_IER_TX_READY_OFFSET                              29
+#define AVR32_ABDAC_IER_TX_READY_SIZE                                 1
+#define AVR32_ABDAC_IER_UNDERRUN                                     28
+#define AVR32_ABDAC_IER_UNDERRUN_MASK                        0x10000000
+#define AVR32_ABDAC_IER_UNDERRUN_OFFSET                              28
+#define AVR32_ABDAC_IER_UNDERRUN_SIZE                                 1
+#define AVR32_ABDAC_IMR                                      0x0000000c
+#define AVR32_ABDAC_IMR_TX_READY                                     29
+#define AVR32_ABDAC_IMR_TX_READY_MASK                        0x20000000
+#define AVR32_ABDAC_IMR_TX_READY_OFFSET                              29
+#define AVR32_ABDAC_IMR_TX_READY_SIZE                                 1
+#define AVR32_ABDAC_IMR_UNDERRUN                                     28
+#define AVR32_ABDAC_IMR_UNDERRUN_MASK                        0x10000000
+#define AVR32_ABDAC_IMR_UNDERRUN_OFFSET                              28
+#define AVR32_ABDAC_IMR_UNDERRUN_SIZE                                 1
+#define AVR32_ABDAC_ISR                                      0x0000001c
+#define AVR32_ABDAC_ISR_TX_READY                                     29
+#define AVR32_ABDAC_ISR_TX_READY_MASK                        0x20000000
+#define AVR32_ABDAC_ISR_TX_READY_OFFSET                              29
+#define AVR32_ABDAC_ISR_TX_READY_SIZE                                 1
+#define AVR32_ABDAC_ISR_UNDERRUN                                     28
+#define AVR32_ABDAC_ISR_UNDERRUN_MASK                        0x10000000
+#define AVR32_ABDAC_ISR_UNDERRUN_OFFSET                              28
+#define AVR32_ABDAC_ISR_UNDERRUN_SIZE                                 1
+#define AVR32_ABDAC_SDR                                      0x00000000
+#define AVR32_ABDAC_SDR_CHANNEL0                                      0
+#define AVR32_ABDAC_SDR_CHANNEL0_MASK                        0x0000ffff
+#define AVR32_ABDAC_SDR_CHANNEL0_OFFSET                               0
+#define AVR32_ABDAC_SDR_CHANNEL0_SIZE                                16
+#define AVR32_ABDAC_SDR_CHANNEL1                                     16
+#define AVR32_ABDAC_SDR_CHANNEL1_MASK                        0xffff0000
+#define AVR32_ABDAC_SDR_CHANNEL1_OFFSET                              16
+#define AVR32_ABDAC_SDR_CHANNEL1_SIZE                                16
+#define AVR32_ABDAC_SWAP                                             30
+#define AVR32_ABDAC_SWAP_MASK                                0x40000000
+#define AVR32_ABDAC_SWAP_OFFSET                                      30
+#define AVR32_ABDAC_SWAP_SIZE                                         1
+#define AVR32_ABDAC_TX_READY                                         29
+#define AVR32_ABDAC_TX_READY_MASK                            0x20000000
+#define AVR32_ABDAC_TX_READY_OFFSET                                  29
+#define AVR32_ABDAC_TX_READY_SIZE                                     1
+#define AVR32_ABDAC_UNDERRUN                                         28
+#define AVR32_ABDAC_UNDERRUN_MASK                            0x10000000
+#define AVR32_ABDAC_UNDERRUN_OFFSET                                  28
+#define AVR32_ABDAC_UNDERRUN_SIZE                                     1
+
+
+
+
+#ifdef __AVR32_ABI_COMPILER__
+
+
+typedef struct avr32_abdac_sdr_t {
+    unsigned int channel1        :16;
+    unsigned int channel0        :16;
+} avr32_abdac_sdr_t;
+
+
+
+typedef struct avr32_abdac_cr_t {
+    unsigned int en              : 1;
+    unsigned int swap            : 1;
+    unsigned int                 :30;
+} avr32_abdac_cr_t;
+
+
+
+typedef struct avr32_abdac_imr_t {
+    unsigned int                 : 2;
+    unsigned int tx_ready        : 1;
+    unsigned int underrun        : 1;
+    unsigned int                 :28;
+} avr32_abdac_imr_t;
+
+
+
+typedef struct avr32_abdac_ier_t {
+    unsigned int                 : 2;
+    unsigned int tx_ready        : 1;
+    unsigned int underrun        : 1;
+    unsigned int                 :28;
+} avr32_abdac_ier_t;
+
+
+
+typedef struct avr32_abdac_idr_t {
+    unsigned int                 : 2;
+    unsigned int tx_ready        : 1;
+    unsigned int underrun        : 1;
+    unsigned int                 :28;
+} avr32_abdac_idr_t;
+
+
+
+typedef struct avr32_abdac_icr_t {
+    unsigned int                 : 3;
+    unsigned int underrun        : 1;
+    unsigned int                 :28;
+} avr32_abdac_icr_t;
+
+
+
+typedef struct avr32_abdac_isr_t {
+    unsigned int                 : 2;
+    unsigned int tx_ready        : 1;
+    unsigned int underrun        : 1;
+    unsigned int                 :28;
+} avr32_abdac_isr_t;
+
+
+
+typedef struct avr32_abdac_t {
+  union {
+          unsigned long                  sdr       ;//0x0000
+          avr32_abdac_sdr_t              SDR       ;
+  };
+          unsigned int                   :32       ;//0x0004
+  union {
+          unsigned long                  cr        ;//0x0008
+          avr32_abdac_cr_t               CR        ;
+  };
+  union {
+    const unsigned long                  imr       ;//0x000c
+    const avr32_abdac_imr_t              IMR       ;
+  };
+  union {
+          unsigned long                  ier       ;//0x0010
+          avr32_abdac_ier_t              IER       ;
+  };
+  union {
+          unsigned long                  idr       ;//0x0014
+          avr32_abdac_idr_t              IDR       ;
+  };
+  union {
+          unsigned long                  icr       ;//0x0018
+          avr32_abdac_icr_t              ICR       ;
+  };
+  union {
+    const unsigned long                  isr       ;//0x001c
+    const avr32_abdac_isr_t              ISR       ;
+  };
+} avr32_abdac_t;
+
+
+
+/*#ifdef __AVR32_ABI_COMPILER__*/
+#endif
+
+/*#ifdef AVR32_ABDAC_101_H_INCLUDED*/
+#endif
+
diff --git a/headers/avr32/abi.h b/headers/avr32/abi.h
@@ -0,0 +1,78 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $
+ *
+ ****************************************************************************/
+#ifndef AVR32_ABI_H_INCLUDED
+#define AVR32_ABI_H_INCLUDED
+
+
+/* The GNU assembler is ABI compliant*/
+#ifndef __AVR32_ABI_ASSEMBLER__
+# ifdef __GNUC__
+#  ifdef __ASSEMBLER__
+#   define __AVR32_ABI_ASSEMBLER__
+#  endif
+# endif
+#endif
+
+/* The GNU C/C++ compiler is ABI compliant */
+#ifndef __AVR32_ABI_COMPILER__
+# ifdef __GNUC__
+#  ifndef __ASSEMBLER__
+#   define __AVR32_ABI_COMPILER__
+#  endif
+# endif
+#endif
+
+
+/* The IAR Systems C/C++ Compiler is ABI compliant */
+#ifndef __AVR32_ABI_COMPILER__
+# ifdef __ICCAVR32__
+#  define __AVR32_ABI_COMPILER__
+# endif
+#endif
+
+/* The IAR Systems Assembler is ABI compliant */
+#ifndef __AVR32_ABI_ASSEMBLER__
+# ifdef __AAVR32__
+#  define __AVR32_ABI_ASSEMBLER__
+# endif
+#endif
+
+
+
+/*#ifndef AVR32_ABI_H_INCLUDED*/
+#endif
+
diff --git a/headers/avr32/ac97c_210.h b/headers/avr32/ac97c_210.h
diff --git a/headers/avr32/ac97c_220.h b/headers/avr32/ac97c_220.h
diff --git a/headers/avr32/acifa_100.h b/headers/avr32/acifa_100.h
diff --git a/headers/avr32/acifb_201.h b/headers/avr32/acifb_201.h
diff --git a/headers/avr32/acifb_202.h b/headers/avr32/acifb_202.h
diff --git a/headers/avr32/adc_102.h b/headers/avr32/adc_102.h
diff --git a/headers/avr32/adc_110.h b/headers/avr32/adc_110.h
diff --git a/headers/avr32/adc_200.h b/headers/avr32/adc_200.h
diff --git a/headers/avr32/adcifa_100.h b/headers/avr32/adcifa_100.h
diff --git a/headers/avr32/adcifb_100.h b/headers/avr32/adcifb_100.h
diff --git a/headers/avr32/adcifb_101.h b/headers/avr32/adcifb_101.h
diff --git a/headers/avr32/aes_1231.h b/headers/avr32/aes_1231.h
diff --git a/headers/avr32/ap7000.h b/headers/avr32/ap7000.h
diff --git a/headers/avr32/ap7001.h b/headers/avr32/ap7001.h
diff --git a/headers/avr32/ap7002.h b/headers/avr32/ap7002.h
diff --git a/headers/avr32/ap7200.h b/headers/avr32/ap7200.h
diff --git a/headers/avr32/ast_100.h b/headers/avr32/ast_100.h
diff --git a/headers/avr32/ast_200.h b/headers/avr32/ast_200.h
diff --git a/headers/avr32/ast_300.h b/headers/avr32/ast_300.h
diff --git a/headers/avr32/avr32headers-version.txt b/headers/avr32/avr32headers-version.txt
@@ -0,0 +1 @@
+2.3.4 20091221
diff --git a/headers/avr32/aw_200.h b/headers/avr32/aw_200.h
diff --git a/headers/avr32/aw_201.h b/headers/avr32/aw_201.h
diff --git a/headers/avr32/aw_210.h b/headers/avr32/aw_210.h
diff --git a/headers/avr32/busmon_100.h b/headers/avr32/busmon_100.h
diff --git a/headers/avr32/canif_100.h b/headers/avr32/canif_100.h
diff --git a/headers/avr32/cat_100.h b/headers/avr32/cat_100.h
diff --git a/headers/avr32/cat_200.h b/headers/avr32/cat_200.h
diff --git a/headers/avr32/core_c3_100.h b/headers/avr32/core_c3_100.h
diff --git a/headers/avr32/core_c3_200.h b/headers/avr32/core_c3_200.h
diff --git a/headers/avr32/core_sc0_100.h b/headers/avr32/core_sc0_100.h
diff --git a/headers/avr32/core_sc0_130.h b/headers/avr32/core_sc0_130.h
diff --git a/headers/avr32/core_sc0_140.h b/headers/avr32/core_sc0_140.h
diff --git a/headers/avr32/core_sc0_142.h b/headers/avr32/core_sc0_142.h
diff --git a/headers/avr32/core_sc0_143.h b/headers/avr32/core_sc0_143.h
diff --git a/headers/avr32/core_sc0_200.h b/headers/avr32/core_sc0_200.h
diff --git a/headers/avr32/core_sc0_210.h b/headers/avr32/core_sc0_210.h
diff --git a/headers/avr32/dacifb_100.h b/headers/avr32/dacifb_100.h
diff --git a/headers/avr32/dmaca_206a.h b/headers/avr32/dmaca_206a.h
diff --git a/headers/avr32/ecc_100.h b/headers/avr32/ecc_100.h
@@ -0,0 +1,210 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Model        : AP7000
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $ 
+ *
+ ****************************************************************************/
+#ifndef AVR32_ECC_100_H_INCLUDED
+#define AVR32_ECC_100_H_INCLUDED
+
+#include "avr32/abi.h"
+
+
+/*
+ Note to user:
+
+ The following defines are always generated:
+ - Register offset: AVR32_ECC_<register>
+ - Bitfield mask:   AVR32_ECC_<register>_<bitfield>
+ - Bitfield offset: AVR32_ECC_<register>_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_ECC_<register>_<bitfield>_SIZE
+ - Bitfield values: AVR32_ECC_<register>_<bitfield>_<value name>
+
+ The following defines are generated if they don't cause ambiguities,
+ i.e. the name is unique, or all values with that name are the same.
+ - Bitfield mask:   AVR32_ECC_<bitfield>
+ - Bitfield offset: AVR32_ECC_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_ECC_<bitfield>_SIZE
+ - Bitfield values: AVR32_ECC_<bitfield>_<value name>
+ - Bitfield values: AVR32_ECC_<value name>
+
+ All defines are sorted alphabetically.
+*/
+
+
+#define AVR32_ECC_BITADDR                                           0
+#define AVR32_ECC_BITADDR_MASK                             0x0000000f
+#define AVR32_ECC_BITADDR_OFFSET                                    0
+#define AVR32_ECC_BITADDR_SIZE                                      4
+#define AVR32_ECC_CR                                       0x00000000
+#define AVR32_ECC_CR_RST                                            0
+#define AVR32_ECC_CR_RST_MASK                              0x00000001
+#define AVR32_ECC_CR_RST_OFFSET                                     0
+#define AVR32_ECC_CR_RST_SIZE                                       1
+#define AVR32_ECC_ECCERR                                            1
+#define AVR32_ECC_ECCERR_MASK                              0x00000002
+#define AVR32_ECC_ECCERR_OFFSET                                     1
+#define AVR32_ECC_ECCERR_SIZE                                       1
+#define AVR32_ECC_MR                                       0x00000004
+#define AVR32_ECC_MR_PAGESIZE                                       0
+#define AVR32_ECC_MR_PAGESIZE_MASK                         0x00000003
+#define AVR32_ECC_MR_PAGESIZE_OFFSET                                0
+#define AVR32_ECC_MR_PAGESIZE_SIZE                                  2
+#define AVR32_ECC_MULERR                                            2
+#define AVR32_ECC_MULERR_MASK                              0x00000004
+#define AVR32_ECC_MULERR_OFFSET                                     2
+#define AVR32_ECC_MULERR_SIZE                                       1
+#define AVR32_ECC_NPARITY                                           0
+#define AVR32_ECC_NPARITY_MASK                             0x0000ffff
+#define AVR32_ECC_NPARITY_OFFSET                                    0
+#define AVR32_ECC_NPARITY_SIZE                                     16
+#define AVR32_ECC_NPR                                      0x00000010
+#define AVR32_ECC_NPR_NPARITY                                       0
+#define AVR32_ECC_NPR_NPARITY_MASK                         0x0000ffff
+#define AVR32_ECC_NPR_NPARITY_OFFSET                                0
+#define AVR32_ECC_NPR_NPARITY_SIZE                                 16
+#define AVR32_ECC_PAGESIZE                                          0
+#define AVR32_ECC_PAGESIZE_MASK                            0x00000003
+#define AVR32_ECC_PAGESIZE_OFFSET                                   0
+#define AVR32_ECC_PAGESIZE_SIZE                                     2
+#define AVR32_ECC_PR                                       0x0000000c
+#define AVR32_ECC_PR_BITADDR                                        0
+#define AVR32_ECC_PR_BITADDR_MASK                          0x0000000f
+#define AVR32_ECC_PR_BITADDR_OFFSET                                 0
+#define AVR32_ECC_PR_BITADDR_SIZE                                   4
+#define AVR32_ECC_PR_WORDADDR                                       4
+#define AVR32_ECC_PR_WORDADDR_MASK                         0x0000fff0
+#define AVR32_ECC_PR_WORDADDR_OFFSET                                4
+#define AVR32_ECC_PR_WORDADDR_SIZE                                 12
+#define AVR32_ECC_RECERR                                            0
+#define AVR32_ECC_RECERR_MASK                              0x00000001
+#define AVR32_ECC_RECERR_OFFSET                                     0
+#define AVR32_ECC_RECERR_SIZE                                       1
+#define AVR32_ECC_RST                                               0
+#define AVR32_ECC_RST_MASK                                 0x00000001
+#define AVR32_ECC_RST_OFFSET                                        0
+#define AVR32_ECC_RST_SIZE                                          1
+#define AVR32_ECC_SR                                       0x00000008
+#define AVR32_ECC_SR_ECCERR                                         1
+#define AVR32_ECC_SR_ECCERR_MASK                           0x00000002
+#define AVR32_ECC_SR_ECCERR_OFFSET                                  1
+#define AVR32_ECC_SR_ECCERR_SIZE                                    1
+#define AVR32_ECC_SR_MULERR                                         2
+#define AVR32_ECC_SR_MULERR_MASK                           0x00000004
+#define AVR32_ECC_SR_MULERR_OFFSET                                  2
+#define AVR32_ECC_SR_MULERR_SIZE                                    1
+#define AVR32_ECC_SR_RECERR                                         0
+#define AVR32_ECC_SR_RECERR_MASK                           0x00000001
+#define AVR32_ECC_SR_RECERR_OFFSET                                  0
+#define AVR32_ECC_SR_RECERR_SIZE                                    1
+#define AVR32_ECC_WORDADDR                                          4
+#define AVR32_ECC_WORDADDR_MASK                            0x0000fff0
+#define AVR32_ECC_WORDADDR_OFFSET                                   4
+#define AVR32_ECC_WORDADDR_SIZE                                    12
+
+
+
+
+#ifdef __AVR32_ABI_COMPILER__
+
+
+typedef struct avr32_ecc_cr_t {
+    unsigned int                 :31;
+    unsigned int rst             : 1;
+} avr32_ecc_cr_t;
+
+
+
+typedef struct avr32_ecc_mr_t {
+    unsigned int                 :30;
+    unsigned int pagesize        : 2;
+} avr32_ecc_mr_t;
+
+
+
+typedef struct avr32_ecc_sr_t {
+    unsigned int                 :29;
+    unsigned int mulerr          : 1;
+    unsigned int eccerr          : 1;
+    unsigned int recerr          : 1;
+} avr32_ecc_sr_t;
+
+
+
+typedef struct avr32_ecc_pr_t {
+    unsigned int                 :16;
+    unsigned int wordaddr        :12;
+    unsigned int bitaddr         : 4;
+} avr32_ecc_pr_t;
+
+
+
+typedef struct avr32_ecc_npr_t {
+    unsigned int                 :16;
+    unsigned int nparity         :16;
+} avr32_ecc_npr_t;
+
+
+
+typedef struct avr32_ecc_t {
+  union {
+          unsigned long                  cr        ;//0x0000
+          avr32_ecc_cr_t                 CR        ;
+  };
+  union {
+          unsigned long                  mr        ;//0x0004
+          avr32_ecc_mr_t                 MR        ;
+  };
+  union {
+    const unsigned long                  sr        ;//0x0008
+    const avr32_ecc_sr_t                 SR        ;
+  };
+  union {
+    const unsigned long                  pr        ;//0x000c
+    const avr32_ecc_pr_t                 PR        ;
+  };
+  union {
+    const unsigned long                  npr       ;//0x0010
+    const avr32_ecc_npr_t                NPR       ;
+  };
+} avr32_ecc_t;
+
+
+
+/*#ifdef __AVR32_ABI_COMPILER__*/
+#endif
+
+/*#ifdef AVR32_ECC_100_H_INCLUDED*/
+#endif
+
diff --git a/headers/avr32/ecc_200.h b/headers/avr32/ecc_200.h
diff --git a/headers/avr32/ecchrs_100.h b/headers/avr32/ecchrs_100.h
diff --git a/headers/avr32/eic_100.h b/headers/avr32/eic_100.h
diff --git a/headers/avr32/eic_200.h b/headers/avr32/eic_200.h
diff --git a/headers/avr32/eic_210.h b/headers/avr32/eic_210.h
diff --git a/headers/avr32/eic_230.h b/headers/avr32/eic_230.h
diff --git a/headers/avr32/eic_231.h b/headers/avr32/eic_231.h
diff --git a/headers/avr32/eic_2311.h b/headers/avr32/eic_2311.h
diff --git a/headers/avr32/eic_300.h b/headers/avr32/eic_300.h
diff --git a/headers/avr32/eic_301.h b/headers/avr32/eic_301.h
diff --git a/headers/avr32/flashc_100.h b/headers/avr32/flashc_100.h
diff --git a/headers/avr32/flashc_200.h b/headers/avr32/flashc_200.h
diff --git a/headers/avr32/flashc_210.h b/headers/avr32/flashc_210.h
diff --git a/headers/avr32/flashc_212.h b/headers/avr32/flashc_212.h
diff --git a/headers/avr32/flashc_300.h b/headers/avr32/flashc_300.h
diff --git a/headers/avr32/flashcdw_100.h b/headers/avr32/flashcdw_100.h
diff --git a/headers/avr32/flashcdw_101.h b/headers/avr32/flashcdw_101.h
diff --git a/headers/avr32/flashcdw_102.h b/headers/avr32/flashcdw_102.h
diff --git a/headers/avr32/flashvault.h b/headers/avr32/flashvault.h
@@ -0,0 +1,131 @@
+/* Copyright (c) 2009, Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr32/flashvault.h - Flashvault API */
+
+#ifndef _AVR32_FLASHVAULT_H_
+#define _AVR32_FLASHVAULT_H_ 1
+
+
+/** \file */
+/** \defgroup avr32_flashvault <avr32/flashvault.h>: Flashvault Support
+
+    \par Introduction
+
+    The Flashvault API introduces some convenience macros to make it easier
+    to set critical values for an application that resides in the Flashvault
+    memory (a Flashvault Server application).
+    
+    \par Flashvault API
+    
+    There are two macros that are defined in this file:
+    #define FLASHVAULT_FLASH_SIZE (flash_size)
+    #define FLASHVAULT_RAM_SIZE (ram_size)
+    
+    Use the FLASHVAULT_FLASH_SIZE macro to set the total size of the Flashvault
+    flash memory by passing the flash size as a parameter to this macro. 
+    This macro must be used outside of any function. It should
+    only be used once in the Flashvault Server application.
+    
+    Use the FLASHVAULT_RAM_SIZE macro to set the total size of the Flashvault 
+    RAM memory by passing the RAM size as a parameter to this macro. This macro
+    must be used outside of any function. It should only be used once in the
+    Flashvault Server application.
+    
+    \par API Usage Example
+
+    At the top of a compilation unit, use the macros outside of any function.
+    Be sure to put a semicolon after the macros.
+
+    \code
+    FLASHVAULT_FLASH_SIZE(0x2000);  // 8K
+    FLASHVAULT_RAM_SIZE(0x400);     // 1K
+    \endcode
+
+    \par Implementation details
+    The FLASHVAULT_FLASH_SIZE macro will define two variables: 
+    
+    The macro will define a variable named __flashvault_flash_size as type 
+    uint32_t and it will assign the flash size to this variable. This variable
+    has an attribute and will be put into the custom named section 
+    .flashvault_flash_size. The default linker scripts will place this value
+    into an ELF section named .flashvault_flash_size. This ELF section will be
+    used by the chip programming software to set the Flashvault flash size on
+    programming.
+    
+    The macro will also define another variable named
+    __flashvault_user_app_start and will assign the value of the beginning flash
+    address (0x80000000) plus the size of the Flashvault Flash. This variable
+    is used in the special Flashvault startup code. Unfortunately at this time
+    the Flashvault startup code is hardcoded to specifically look for this
+    variable name. If this variable name (with a correct value) is not defined
+    in the Flashvault Server application there will be a linking error.
+    
+    The FLASHVAULT_RAM_SIZE macro is very similar to the FLASHVAULT_FLASH_SIZE
+    macro, and it will define a single variable:
+    
+    The macro will define a variable named __flashvault_ram_size as type 
+    uint32_t and it will assign the RAM size to this variable. This variable
+    has an attribute and will be put into the custom named section 
+    .flashvault_ram_size. The default linker scripts will place this value
+    into an ELF section named .flashvault_ram_size. This ELF section will be
+    used by the chip programming software to set the Flashvault RAM size on
+    programming.
+
+*/
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+#if !defined(FLASHVAULT_FLASH_SIZE)
+#undef FLASHVAULT_FLASH_SIZE
+
+#define FLASHVAULT_FLASH_SIZE(flash_size) \
+uint32_t __flashvault_flash_size __attribute__((section (".flashvault_flash_size"))) = (flash_size); \
+uint32_t __flashvault_user_app_start = (0x80000000 + (flash_size))
+
+#endif
+
+
+#if !defined(FLASHVAULT_RAM_SIZE)
+#undef FLASHVAULT_RAM_SIZE
+
+#define FLASHVAULT_RAM_SIZE(ram_size) \
+uint32_t __flashvault_ram_size __attribute__((section (".flashvault_ram_size"))) = (ram_size)
+
+#endif
+
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* _AVR32_FLASHVAULT_H_ */
diff --git a/headers/avr32/freqm_200.h b/headers/avr32/freqm_200.h
@@ -0,0 +1,322 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Model        : UC3A0512ES
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $ 
+ *
+ ****************************************************************************/
+#ifndef AVR32_FREQM_200_H_INCLUDED
+#define AVR32_FREQM_200_H_INCLUDED
+
+#include "avr32/abi.h"
+
+
+/*
+ Note to user:
+
+ The following defines are always generated:
+ - Register offset: AVR32_FREQM_<register>
+ - Bitfield mask:   AVR32_FREQM_<register>_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<register>_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<register>_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<register>_<bitfield>_<value name>
+
+ The following defines are generated if they don't cause ambiguities,
+ i.e. the name is unique, or all values with that name are the same.
+ - Bitfield mask:   AVR32_FREQM_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<bitfield>_<value name>
+ - Bitfield values: AVR32_FREQM_<value name>
+
+ All defines are sorted alphabetically.
+*/
+
+
+#define AVR32_FREQM_BUSY                                              0
+#define AVR32_FREQM_BUSY_MASK                                0x00000001
+#define AVR32_FREQM_BUSY_OFFSET                                       0
+#define AVR32_FREQM_BUSY_SIZE                                         1
+#define AVR32_FREQM_CLKSEL                                           16
+#define AVR32_FREQM_CLKSEL_CPU                               0x00000000
+#define AVR32_FREQM_CLKSEL_CRIPLEL                           0x0000000a
+#define AVR32_FREQM_CLKSEL_GENCLK0                           0x0000000b
+#define AVR32_FREQM_CLKSEL_GENCLK1                           0x0000000c
+#define AVR32_FREQM_CLKSEL_GENCLK2                           0x0000000d
+#define AVR32_FREQM_CLKSEL_GENCLK3                           0x0000000e
+#define AVR32_FREQM_CLKSEL_GENCLK4                           0x0000000f
+#define AVR32_FREQM_CLKSEL_GENCLK5                           0x00000010
+#define AVR32_FREQM_CLKSEL_HSB                               0x00000001
+#define AVR32_FREQM_CLKSEL_MASK                              0x001f0000
+#define AVR32_FREQM_CLKSEL_OFFSET                                    16
+#define AVR32_FREQM_CLKSEL_OSC0                              0x00000004
+#define AVR32_FREQM_CLKSEL_OSC1                              0x00000005
+#define AVR32_FREQM_CLKSEL_OSC32                             0x00000006
+#define AVR32_FREQM_CLKSEL_PBA                               0x00000002
+#define AVR32_FREQM_CLKSEL_PBB                               0x00000003
+#define AVR32_FREQM_CLKSEL_PLL0                              0x00000008
+#define AVR32_FREQM_CLKSEL_PLL1                              0x00000009
+#define AVR32_FREQM_CLKSEL_RCOSC                             0x00000007
+#define AVR32_FREQM_CLKSEL_SIZE                                       5
+#define AVR32_FREQM_CPU                                      0x00000000
+#define AVR32_FREQM_CRIPLEL                                  0x0000000a
+#define AVR32_FREQM_CTRL                                     0x00000000
+#define AVR32_FREQM_CTRL_START                                        0
+#define AVR32_FREQM_CTRL_START_MASK                          0x00000001
+#define AVR32_FREQM_CTRL_START_OFFSET                                 0
+#define AVR32_FREQM_CTRL_START_SIZE                                   1
+#define AVR32_FREQM_DONE                                              0
+#define AVR32_FREQM_DONE_MASK                                0x00000001
+#define AVR32_FREQM_DONE_OFFSET                                       0
+#define AVR32_FREQM_DONE_SIZE                                         1
+#define AVR32_FREQM_GENCLK0                                  0x0000000b
+#define AVR32_FREQM_GENCLK1                                  0x0000000c
+#define AVR32_FREQM_GENCLK2                                  0x0000000d
+#define AVR32_FREQM_GENCLK3                                  0x0000000e
+#define AVR32_FREQM_GENCLK4                                  0x0000000f
+#define AVR32_FREQM_GENCLK5                                  0x00000010
+#define AVR32_FREQM_HSB                                      0x00000001
+#define AVR32_FREQM_ICR                                      0x00000020
+#define AVR32_FREQM_ICR_DONE                                          0
+#define AVR32_FREQM_ICR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ICR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ICR_DONE_SIZE                                     1
+#define AVR32_FREQM_IDR                                      0x00000014
+#define AVR32_FREQM_IDR_DONE                                          0
+#define AVR32_FREQM_IDR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IDR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IDR_DONE_SIZE                                     1
+#define AVR32_FREQM_IER                                      0x00000010
+#define AVR32_FREQM_IER_DONE                                          0
+#define AVR32_FREQM_IER_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IER_DONE_OFFSET                                   0
+#define AVR32_FREQM_IER_DONE_SIZE                                     1
+#define AVR32_FREQM_IMR                                      0x00000018
+#define AVR32_FREQM_IMR_DONE                                          0
+#define AVR32_FREQM_IMR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IMR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IMR_DONE_SIZE                                     1
+#define AVR32_FREQM_ISR                                      0x0000001c
+#define AVR32_FREQM_ISR_DONE                                          0
+#define AVR32_FREQM_ISR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ISR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ISR_DONE_SIZE                                     1
+#define AVR32_FREQM_MODE                                     0x00000004
+#define AVR32_FREQM_MODE_CLKSEL                                      16
+#define AVR32_FREQM_MODE_CLKSEL_CPU                          0x00000000
+#define AVR32_FREQM_MODE_CLKSEL_CRIPLEL                      0x0000000a
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK0                      0x0000000b
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK1                      0x0000000c
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK2                      0x0000000d
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK3                      0x0000000e
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK4                      0x0000000f
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK5                      0x00000010
+#define AVR32_FREQM_MODE_CLKSEL_HSB                          0x00000001
+#define AVR32_FREQM_MODE_CLKSEL_MASK                         0x001f0000
+#define AVR32_FREQM_MODE_CLKSEL_OFFSET                               16
+#define AVR32_FREQM_MODE_CLKSEL_OSC0                         0x00000004
+#define AVR32_FREQM_MODE_CLKSEL_OSC1                         0x00000005
+#define AVR32_FREQM_MODE_CLKSEL_OSC32                        0x00000006
+#define AVR32_FREQM_MODE_CLKSEL_PBA                          0x00000002
+#define AVR32_FREQM_MODE_CLKSEL_PBB                          0x00000003
+#define AVR32_FREQM_MODE_CLKSEL_PLL0                         0x00000008
+#define AVR32_FREQM_MODE_CLKSEL_PLL1                         0x00000009
+#define AVR32_FREQM_MODE_CLKSEL_RCOSC                        0x00000007
+#define AVR32_FREQM_MODE_CLKSEL_SIZE                                  5
+#define AVR32_FREQM_MODE_REFNUM                                       8
+#define AVR32_FREQM_MODE_REFNUM_MASK                         0x0000ff00
+#define AVR32_FREQM_MODE_REFNUM_OFFSET                                8
+#define AVR32_FREQM_MODE_REFNUM_SIZE                                  8
+#define AVR32_FREQM_MODE_REFSEL                                       0
+#define AVR32_FREQM_MODE_REFSEL_MASK                         0x00000001
+#define AVR32_FREQM_MODE_REFSEL_OFFSET                                0
+#define AVR32_FREQM_MODE_REFSEL_REF_OSC32                    0x00000001
+#define AVR32_FREQM_MODE_REFSEL_REF_RCOSC                    0x00000000
+#define AVR32_FREQM_MODE_REFSEL_SIZE                                  1
+#define AVR32_FREQM_OSC0                                     0x00000004
+#define AVR32_FREQM_OSC1                                     0x00000005
+#define AVR32_FREQM_OSC32                                    0x00000006
+#define AVR32_FREQM_PBA                                      0x00000002
+#define AVR32_FREQM_PBB                                      0x00000003
+#define AVR32_FREQM_PLL0                                     0x00000008
+#define AVR32_FREQM_PLL1                                     0x00000009
+#define AVR32_FREQM_RCOSC                                    0x00000007
+#define AVR32_FREQM_REFNUM                                            8
+#define AVR32_FREQM_REFNUM_MASK                              0x0000ff00
+#define AVR32_FREQM_REFNUM_OFFSET                                     8
+#define AVR32_FREQM_REFNUM_SIZE                                       8
+#define AVR32_FREQM_REFSEL                                            0
+#define AVR32_FREQM_REFSEL_MASK                              0x00000001
+#define AVR32_FREQM_REFSEL_OFFSET                                     0
+#define AVR32_FREQM_REFSEL_REF_OSC32                         0x00000001
+#define AVR32_FREQM_REFSEL_REF_RCOSC                         0x00000000
+#define AVR32_FREQM_REFSEL_SIZE                                       1
+#define AVR32_FREQM_REF_OSC32                                0x00000001
+#define AVR32_FREQM_REF_RCOSC                                0x00000000
+#define AVR32_FREQM_START                                             0
+#define AVR32_FREQM_START_MASK                               0x00000001
+#define AVR32_FREQM_START_OFFSET                                      0
+#define AVR32_FREQM_START_SIZE                                        1
+#define AVR32_FREQM_STATUS                                   0x00000008
+#define AVR32_FREQM_STATUS_BUSY                                       0
+#define AVR32_FREQM_STATUS_BUSY_MASK                         0x00000001
+#define AVR32_FREQM_STATUS_BUSY_OFFSET                                0
+#define AVR32_FREQM_STATUS_BUSY_SIZE                                  1
+#define AVR32_FREQM_VALUE                                    0x0000000c
+#define AVR32_FREQM_VALUE_MASK                               0x00ffffff
+#define AVR32_FREQM_VALUE_OFFSET                                      0
+#define AVR32_FREQM_VALUE_SIZE                                       24
+#define AVR32_FREQM_VALUE_VALUE                                       0
+#define AVR32_FREQM_VALUE_VALUE_MASK                         0x00ffffff
+#define AVR32_FREQM_VALUE_VALUE_OFFSET                                0
+#define AVR32_FREQM_VALUE_VALUE_SIZE                                 24
+
+
+
+
+#ifdef __AVR32_ABI_COMPILER__
+
+
+typedef struct avr32_freqm_ctrl_t {
+    unsigned int                 :31;
+    unsigned int start           : 1;
+} avr32_freqm_ctrl_t;
+
+
+
+typedef struct avr32_freqm_mode_t {
+    unsigned int                 :11;
+    unsigned int clksel          : 5;
+    unsigned int refnum          : 8;
+    unsigned int                 : 7;
+    unsigned int refsel          : 1;
+} avr32_freqm_mode_t;
+
+
+
+typedef struct avr32_freqm_status_t {
+    unsigned int                 :31;
+    unsigned int busy            : 1;
+} avr32_freqm_status_t;
+
+
+
+typedef struct avr32_freqm_value_t {
+    unsigned int                 : 8;
+    unsigned int value           :24;
+} avr32_freqm_value_t;
+
+
+
+typedef struct avr32_freqm_ier_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_ier_t;
+
+
+
+typedef struct avr32_freqm_idr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_idr_t;
+
+
+
+typedef struct avr32_freqm_imr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_imr_t;
+
+
+
+typedef struct avr32_freqm_isr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_isr_t;
+
+
+
+typedef struct avr32_freqm_icr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_icr_t;
+
+
+
+typedef struct avr32_freqm_t {
+  union {
+          unsigned long                  ctrl      ;//0x0000
+          avr32_freqm_ctrl_t             CTRL      ;
+  };
+  union {
+          unsigned long                  mode      ;//0x0004
+          avr32_freqm_mode_t             MODE      ;
+  };
+  union {
+    const unsigned long                  status    ;//0x0008
+    const avr32_freqm_status_t           STATUS    ;
+  };
+  union {
+          unsigned long                  value     ;//0x000c
+          avr32_freqm_value_t            VALUE     ;
+  };
+  union {
+          unsigned long                  ier       ;//0x0010
+          avr32_freqm_ier_t              IER       ;
+  };
+  union {
+          unsigned long                  idr       ;//0x0014
+          avr32_freqm_idr_t              IDR       ;
+  };
+  union {
+    const unsigned long                  imr       ;//0x0018
+    const avr32_freqm_imr_t              IMR       ;
+  };
+  union {
+    const unsigned long                  isr       ;//0x001c
+    const avr32_freqm_isr_t              ISR       ;
+  };
+  union {
+          unsigned long                  icr       ;//0x0020
+          avr32_freqm_icr_t              ICR       ;
+  };
+} avr32_freqm_t;
+
+
+
+/*#ifdef __AVR32_ABI_COMPILER__*/
+#endif
+
+/*#ifdef AVR32_FREQM_200_H_INCLUDED*/
+#endif
+
diff --git a/headers/avr32/freqm_210.h b/headers/avr32/freqm_210.h
@@ -0,0 +1,322 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Model        : UC3000
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $ 
+ *
+ ****************************************************************************/
+#ifndef AVR32_FREQM_210_H_INCLUDED
+#define AVR32_FREQM_210_H_INCLUDED
+
+#include "avr32/abi.h"
+
+
+/*
+ Note to user:
+
+ The following defines are always generated:
+ - Register offset: AVR32_FREQM_<register>
+ - Bitfield mask:   AVR32_FREQM_<register>_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<register>_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<register>_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<register>_<bitfield>_<value name>
+
+ The following defines are generated if they don't cause ambiguities,
+ i.e. the name is unique, or all values with that name are the same.
+ - Bitfield mask:   AVR32_FREQM_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<bitfield>_<value name>
+ - Bitfield values: AVR32_FREQM_<value name>
+
+ All defines are sorted alphabetically.
+*/
+
+
+#define AVR32_FREQM_BUSY                                              0
+#define AVR32_FREQM_BUSY_MASK                                0x00000001
+#define AVR32_FREQM_BUSY_OFFSET                                       0
+#define AVR32_FREQM_BUSY_SIZE                                         1
+#define AVR32_FREQM_CLKSEL                                           16
+#define AVR32_FREQM_CLKSEL_CPU                               0x00000000
+#define AVR32_FREQM_CLKSEL_CRIPLEL                           0x0000000a
+#define AVR32_FREQM_CLKSEL_GENCLK0                           0x0000000b
+#define AVR32_FREQM_CLKSEL_GENCLK1                           0x0000000c
+#define AVR32_FREQM_CLKSEL_GENCLK2                           0x0000000d
+#define AVR32_FREQM_CLKSEL_GENCLK3                           0x0000000e
+#define AVR32_FREQM_CLKSEL_GENCLK4                           0x0000000f
+#define AVR32_FREQM_CLKSEL_GENCLK5                           0x00000010
+#define AVR32_FREQM_CLKSEL_HSB                               0x00000001
+#define AVR32_FREQM_CLKSEL_MASK                              0x001f0000
+#define AVR32_FREQM_CLKSEL_OFFSET                                    16
+#define AVR32_FREQM_CLKSEL_OSC0                              0x00000004
+#define AVR32_FREQM_CLKSEL_OSC1                              0x00000005
+#define AVR32_FREQM_CLKSEL_OSC32                             0x00000006
+#define AVR32_FREQM_CLKSEL_PBA                               0x00000002
+#define AVR32_FREQM_CLKSEL_PBB                               0x00000003
+#define AVR32_FREQM_CLKSEL_PLL0                              0x00000008
+#define AVR32_FREQM_CLKSEL_PLL1                              0x00000009
+#define AVR32_FREQM_CLKSEL_RCOSC                             0x00000007
+#define AVR32_FREQM_CLKSEL_SIZE                                       5
+#define AVR32_FREQM_CPU                                      0x00000000
+#define AVR32_FREQM_CRIPLEL                                  0x0000000a
+#define AVR32_FREQM_CTRL                                     0x00000000
+#define AVR32_FREQM_CTRL_START                                        0
+#define AVR32_FREQM_CTRL_START_MASK                          0x00000001
+#define AVR32_FREQM_CTRL_START_OFFSET                                 0
+#define AVR32_FREQM_CTRL_START_SIZE                                   1
+#define AVR32_FREQM_DONE                                              0
+#define AVR32_FREQM_DONE_MASK                                0x00000001
+#define AVR32_FREQM_DONE_OFFSET                                       0
+#define AVR32_FREQM_DONE_SIZE                                         1
+#define AVR32_FREQM_GENCLK0                                  0x0000000b
+#define AVR32_FREQM_GENCLK1                                  0x0000000c
+#define AVR32_FREQM_GENCLK2                                  0x0000000d
+#define AVR32_FREQM_GENCLK3                                  0x0000000e
+#define AVR32_FREQM_GENCLK4                                  0x0000000f
+#define AVR32_FREQM_GENCLK5                                  0x00000010
+#define AVR32_FREQM_HSB                                      0x00000001
+#define AVR32_FREQM_ICR                                      0x00000020
+#define AVR32_FREQM_ICR_DONE                                          0
+#define AVR32_FREQM_ICR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ICR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ICR_DONE_SIZE                                     1
+#define AVR32_FREQM_IDR                                      0x00000014
+#define AVR32_FREQM_IDR_DONE                                          0
+#define AVR32_FREQM_IDR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IDR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IDR_DONE_SIZE                                     1
+#define AVR32_FREQM_IER                                      0x00000010
+#define AVR32_FREQM_IER_DONE                                          0
+#define AVR32_FREQM_IER_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IER_DONE_OFFSET                                   0
+#define AVR32_FREQM_IER_DONE_SIZE                                     1
+#define AVR32_FREQM_IMR                                      0x00000018
+#define AVR32_FREQM_IMR_DONE                                          0
+#define AVR32_FREQM_IMR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IMR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IMR_DONE_SIZE                                     1
+#define AVR32_FREQM_ISR                                      0x0000001c
+#define AVR32_FREQM_ISR_DONE                                          0
+#define AVR32_FREQM_ISR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ISR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ISR_DONE_SIZE                                     1
+#define AVR32_FREQM_MODE                                     0x00000004
+#define AVR32_FREQM_MODE_CLKSEL                                      16
+#define AVR32_FREQM_MODE_CLKSEL_CPU                          0x00000000
+#define AVR32_FREQM_MODE_CLKSEL_CRIPLEL                      0x0000000a
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK0                      0x0000000b
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK1                      0x0000000c
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK2                      0x0000000d
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK3                      0x0000000e
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK4                      0x0000000f
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK5                      0x00000010
+#define AVR32_FREQM_MODE_CLKSEL_HSB                          0x00000001
+#define AVR32_FREQM_MODE_CLKSEL_MASK                         0x001f0000
+#define AVR32_FREQM_MODE_CLKSEL_OFFSET                               16
+#define AVR32_FREQM_MODE_CLKSEL_OSC0                         0x00000004
+#define AVR32_FREQM_MODE_CLKSEL_OSC1                         0x00000005
+#define AVR32_FREQM_MODE_CLKSEL_OSC32                        0x00000006
+#define AVR32_FREQM_MODE_CLKSEL_PBA                          0x00000002
+#define AVR32_FREQM_MODE_CLKSEL_PBB                          0x00000003
+#define AVR32_FREQM_MODE_CLKSEL_PLL0                         0x00000008
+#define AVR32_FREQM_MODE_CLKSEL_PLL1                         0x00000009
+#define AVR32_FREQM_MODE_CLKSEL_RCOSC                        0x00000007
+#define AVR32_FREQM_MODE_CLKSEL_SIZE                                  5
+#define AVR32_FREQM_MODE_REFNUM                                       8
+#define AVR32_FREQM_MODE_REFNUM_MASK                         0x0000ff00
+#define AVR32_FREQM_MODE_REFNUM_OFFSET                                8
+#define AVR32_FREQM_MODE_REFNUM_SIZE                                  8
+#define AVR32_FREQM_MODE_REFSEL                                       0
+#define AVR32_FREQM_MODE_REFSEL_MASK                         0x00000001
+#define AVR32_FREQM_MODE_REFSEL_OFFSET                                0
+#define AVR32_FREQM_MODE_REFSEL_REF_OSC32                    0x00000001
+#define AVR32_FREQM_MODE_REFSEL_REF_RCOSC                    0x00000000
+#define AVR32_FREQM_MODE_REFSEL_SIZE                                  1
+#define AVR32_FREQM_OSC0                                     0x00000004
+#define AVR32_FREQM_OSC1                                     0x00000005
+#define AVR32_FREQM_OSC32                                    0x00000006
+#define AVR32_FREQM_PBA                                      0x00000002
+#define AVR32_FREQM_PBB                                      0x00000003
+#define AVR32_FREQM_PLL0                                     0x00000008
+#define AVR32_FREQM_PLL1                                     0x00000009
+#define AVR32_FREQM_RCOSC                                    0x00000007
+#define AVR32_FREQM_REFNUM                                            8
+#define AVR32_FREQM_REFNUM_MASK                              0x0000ff00
+#define AVR32_FREQM_REFNUM_OFFSET                                     8
+#define AVR32_FREQM_REFNUM_SIZE                                       8
+#define AVR32_FREQM_REFSEL                                            0
+#define AVR32_FREQM_REFSEL_MASK                              0x00000001
+#define AVR32_FREQM_REFSEL_OFFSET                                     0
+#define AVR32_FREQM_REFSEL_REF_OSC32                         0x00000001
+#define AVR32_FREQM_REFSEL_REF_RCOSC                         0x00000000
+#define AVR32_FREQM_REFSEL_SIZE                                       1
+#define AVR32_FREQM_REF_OSC32                                0x00000001
+#define AVR32_FREQM_REF_RCOSC                                0x00000000
+#define AVR32_FREQM_START                                             0
+#define AVR32_FREQM_START_MASK                               0x00000001
+#define AVR32_FREQM_START_OFFSET                                      0
+#define AVR32_FREQM_START_SIZE                                        1
+#define AVR32_FREQM_STATUS                                   0x00000008
+#define AVR32_FREQM_STATUS_BUSY                                       0
+#define AVR32_FREQM_STATUS_BUSY_MASK                         0x00000001
+#define AVR32_FREQM_STATUS_BUSY_OFFSET                                0
+#define AVR32_FREQM_STATUS_BUSY_SIZE                                  1
+#define AVR32_FREQM_VALUE                                    0x0000000c
+#define AVR32_FREQM_VALUE_MASK                               0x00ffffff
+#define AVR32_FREQM_VALUE_OFFSET                                      0
+#define AVR32_FREQM_VALUE_SIZE                                       24
+#define AVR32_FREQM_VALUE_VALUE                                       0
+#define AVR32_FREQM_VALUE_VALUE_MASK                         0x00ffffff
+#define AVR32_FREQM_VALUE_VALUE_OFFSET                                0
+#define AVR32_FREQM_VALUE_VALUE_SIZE                                 24
+
+
+
+
+#ifdef __AVR32_ABI_COMPILER__
+
+
+typedef struct avr32_freqm_ctrl_t {
+    unsigned int                 :31;
+    unsigned int start           : 1;
+} avr32_freqm_ctrl_t;
+
+
+
+typedef struct avr32_freqm_mode_t {
+    unsigned int                 :11;
+    unsigned int clksel          : 5;
+    unsigned int refnum          : 8;
+    unsigned int                 : 7;
+    unsigned int refsel          : 1;
+} avr32_freqm_mode_t;
+
+
+
+typedef struct avr32_freqm_status_t {
+    unsigned int                 :31;
+    unsigned int busy            : 1;
+} avr32_freqm_status_t;
+
+
+
+typedef struct avr32_freqm_value_t {
+    unsigned int                 : 8;
+    unsigned int value           :24;
+} avr32_freqm_value_t;
+
+
+
+typedef struct avr32_freqm_ier_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_ier_t;
+
+
+
+typedef struct avr32_freqm_idr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_idr_t;
+
+
+
+typedef struct avr32_freqm_imr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_imr_t;
+
+
+
+typedef struct avr32_freqm_isr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_isr_t;
+
+
+
+typedef struct avr32_freqm_icr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_icr_t;
+
+
+
+typedef struct avr32_freqm_t {
+  union {
+          unsigned long                  ctrl      ;//0x0000
+          avr32_freqm_ctrl_t             CTRL      ;
+  };
+  union {
+          unsigned long                  mode      ;//0x0004
+          avr32_freqm_mode_t             MODE      ;
+  };
+  union {
+    const unsigned long                  status    ;//0x0008
+    const avr32_freqm_status_t           STATUS    ;
+  };
+  union {
+          unsigned long                  value     ;//0x000c
+          avr32_freqm_value_t            VALUE     ;
+  };
+  union {
+          unsigned long                  ier       ;//0x0010
+          avr32_freqm_ier_t              IER       ;
+  };
+  union {
+          unsigned long                  idr       ;//0x0014
+          avr32_freqm_idr_t              IDR       ;
+  };
+  union {
+    const unsigned long                  imr       ;//0x0018
+    const avr32_freqm_imr_t              IMR       ;
+  };
+  union {
+    const unsigned long                  isr       ;//0x001c
+    const avr32_freqm_isr_t              ISR       ;
+  };
+  union {
+          unsigned long                  icr       ;//0x0020
+          avr32_freqm_icr_t              ICR       ;
+  };
+} avr32_freqm_t;
+
+
+
+/*#ifdef __AVR32_ABI_COMPILER__*/
+#endif
+
+/*#ifdef AVR32_FREQM_210_H_INCLUDED*/
+#endif
+
diff --git a/headers/avr32/freqm_230.h b/headers/avr32/freqm_230.h
@@ -0,0 +1,322 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Model        : UC3000
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $ 
+ *
+ ****************************************************************************/
+#ifndef AVR32_FREQM_230_H_INCLUDED
+#define AVR32_FREQM_230_H_INCLUDED
+
+#include "avr32/abi.h"
+
+
+/*
+ Note to user:
+
+ The following defines are always generated:
+ - Register offset: AVR32_FREQM_<register>
+ - Bitfield mask:   AVR32_FREQM_<register>_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<register>_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<register>_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<register>_<bitfield>_<value name>
+
+ The following defines are generated if they don't cause ambiguities,
+ i.e. the name is unique, or all values with that name are the same.
+ - Bitfield mask:   AVR32_FREQM_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<bitfield>_<value name>
+ - Bitfield values: AVR32_FREQM_<value name>
+
+ All defines are sorted alphabetically.
+*/
+
+
+#define AVR32_FREQM_BUSY                                              0
+#define AVR32_FREQM_BUSY_MASK                                0x00000001
+#define AVR32_FREQM_BUSY_OFFSET                                       0
+#define AVR32_FREQM_BUSY_SIZE                                         1
+#define AVR32_FREQM_CLKSEL                                           16
+#define AVR32_FREQM_CLKSEL_CPU                               0x00000000
+#define AVR32_FREQM_CLKSEL_CRIPLEL                           0x0000000a
+#define AVR32_FREQM_CLKSEL_GENCLK0                           0x0000000b
+#define AVR32_FREQM_CLKSEL_GENCLK1                           0x0000000c
+#define AVR32_FREQM_CLKSEL_GENCLK2                           0x0000000d
+#define AVR32_FREQM_CLKSEL_GENCLK3                           0x0000000e
+#define AVR32_FREQM_CLKSEL_GENCLK4                           0x0000000f
+#define AVR32_FREQM_CLKSEL_GENCLK5                           0x00000010
+#define AVR32_FREQM_CLKSEL_HSB                               0x00000001
+#define AVR32_FREQM_CLKSEL_MASK                              0x001f0000
+#define AVR32_FREQM_CLKSEL_OFFSET                                    16
+#define AVR32_FREQM_CLKSEL_OSC0                              0x00000004
+#define AVR32_FREQM_CLKSEL_OSC1                              0x00000005
+#define AVR32_FREQM_CLKSEL_OSC32                             0x00000006
+#define AVR32_FREQM_CLKSEL_PBA                               0x00000002
+#define AVR32_FREQM_CLKSEL_PBB                               0x00000003
+#define AVR32_FREQM_CLKSEL_PLL0                              0x00000008
+#define AVR32_FREQM_CLKSEL_PLL1                              0x00000009
+#define AVR32_FREQM_CLKSEL_RCOSC                             0x00000007
+#define AVR32_FREQM_CLKSEL_SIZE                                       5
+#define AVR32_FREQM_CPU                                      0x00000000
+#define AVR32_FREQM_CRIPLEL                                  0x0000000a
+#define AVR32_FREQM_CTRL                                     0x00000000
+#define AVR32_FREQM_CTRL_START                                        0
+#define AVR32_FREQM_CTRL_START_MASK                          0x00000001
+#define AVR32_FREQM_CTRL_START_OFFSET                                 0
+#define AVR32_FREQM_CTRL_START_SIZE                                   1
+#define AVR32_FREQM_DONE                                              0
+#define AVR32_FREQM_DONE_MASK                                0x00000001
+#define AVR32_FREQM_DONE_OFFSET                                       0
+#define AVR32_FREQM_DONE_SIZE                                         1
+#define AVR32_FREQM_GENCLK0                                  0x0000000b
+#define AVR32_FREQM_GENCLK1                                  0x0000000c
+#define AVR32_FREQM_GENCLK2                                  0x0000000d
+#define AVR32_FREQM_GENCLK3                                  0x0000000e
+#define AVR32_FREQM_GENCLK4                                  0x0000000f
+#define AVR32_FREQM_GENCLK5                                  0x00000010
+#define AVR32_FREQM_HSB                                      0x00000001
+#define AVR32_FREQM_ICR                                      0x00000020
+#define AVR32_FREQM_ICR_DONE                                          0
+#define AVR32_FREQM_ICR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ICR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ICR_DONE_SIZE                                     1
+#define AVR32_FREQM_IDR                                      0x00000014
+#define AVR32_FREQM_IDR_DONE                                          0
+#define AVR32_FREQM_IDR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IDR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IDR_DONE_SIZE                                     1
+#define AVR32_FREQM_IER                                      0x00000010
+#define AVR32_FREQM_IER_DONE                                          0
+#define AVR32_FREQM_IER_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IER_DONE_OFFSET                                   0
+#define AVR32_FREQM_IER_DONE_SIZE                                     1
+#define AVR32_FREQM_IMR                                      0x00000018
+#define AVR32_FREQM_IMR_DONE                                          0
+#define AVR32_FREQM_IMR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IMR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IMR_DONE_SIZE                                     1
+#define AVR32_FREQM_ISR                                      0x0000001c
+#define AVR32_FREQM_ISR_DONE                                          0
+#define AVR32_FREQM_ISR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ISR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ISR_DONE_SIZE                                     1
+#define AVR32_FREQM_MODE                                     0x00000004
+#define AVR32_FREQM_MODE_CLKSEL                                      16
+#define AVR32_FREQM_MODE_CLKSEL_CPU                          0x00000000
+#define AVR32_FREQM_MODE_CLKSEL_CRIPLEL                      0x0000000a
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK0                      0x0000000b
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK1                      0x0000000c
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK2                      0x0000000d
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK3                      0x0000000e
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK4                      0x0000000f
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK5                      0x00000010
+#define AVR32_FREQM_MODE_CLKSEL_HSB                          0x00000001
+#define AVR32_FREQM_MODE_CLKSEL_MASK                         0x001f0000
+#define AVR32_FREQM_MODE_CLKSEL_OFFSET                               16
+#define AVR32_FREQM_MODE_CLKSEL_OSC0                         0x00000004
+#define AVR32_FREQM_MODE_CLKSEL_OSC1                         0x00000005
+#define AVR32_FREQM_MODE_CLKSEL_OSC32                        0x00000006
+#define AVR32_FREQM_MODE_CLKSEL_PBA                          0x00000002
+#define AVR32_FREQM_MODE_CLKSEL_PBB                          0x00000003
+#define AVR32_FREQM_MODE_CLKSEL_PLL0                         0x00000008
+#define AVR32_FREQM_MODE_CLKSEL_PLL1                         0x00000009
+#define AVR32_FREQM_MODE_CLKSEL_RCOSC                        0x00000007
+#define AVR32_FREQM_MODE_CLKSEL_SIZE                                  5
+#define AVR32_FREQM_MODE_REFNUM                                       8
+#define AVR32_FREQM_MODE_REFNUM_MASK                         0x0000ff00
+#define AVR32_FREQM_MODE_REFNUM_OFFSET                                8
+#define AVR32_FREQM_MODE_REFNUM_SIZE                                  8
+#define AVR32_FREQM_MODE_REFSEL                                       0
+#define AVR32_FREQM_MODE_REFSEL_MASK                         0x00000001
+#define AVR32_FREQM_MODE_REFSEL_OFFSET                                0
+#define AVR32_FREQM_MODE_REFSEL_REF_OSC32                    0x00000001
+#define AVR32_FREQM_MODE_REFSEL_REF_RCOSC                    0x00000000
+#define AVR32_FREQM_MODE_REFSEL_SIZE                                  1
+#define AVR32_FREQM_OSC0                                     0x00000004
+#define AVR32_FREQM_OSC1                                     0x00000005
+#define AVR32_FREQM_OSC32                                    0x00000006
+#define AVR32_FREQM_PBA                                      0x00000002
+#define AVR32_FREQM_PBB                                      0x00000003
+#define AVR32_FREQM_PLL0                                     0x00000008
+#define AVR32_FREQM_PLL1                                     0x00000009
+#define AVR32_FREQM_RCOSC                                    0x00000007
+#define AVR32_FREQM_REFNUM                                            8
+#define AVR32_FREQM_REFNUM_MASK                              0x0000ff00
+#define AVR32_FREQM_REFNUM_OFFSET                                     8
+#define AVR32_FREQM_REFNUM_SIZE                                       8
+#define AVR32_FREQM_REFSEL                                            0
+#define AVR32_FREQM_REFSEL_MASK                              0x00000001
+#define AVR32_FREQM_REFSEL_OFFSET                                     0
+#define AVR32_FREQM_REFSEL_REF_OSC32                         0x00000001
+#define AVR32_FREQM_REFSEL_REF_RCOSC                         0x00000000
+#define AVR32_FREQM_REFSEL_SIZE                                       1
+#define AVR32_FREQM_REF_OSC32                                0x00000001
+#define AVR32_FREQM_REF_RCOSC                                0x00000000
+#define AVR32_FREQM_START                                             0
+#define AVR32_FREQM_START_MASK                               0x00000001
+#define AVR32_FREQM_START_OFFSET                                      0
+#define AVR32_FREQM_START_SIZE                                        1
+#define AVR32_FREQM_STATUS                                   0x00000008
+#define AVR32_FREQM_STATUS_BUSY                                       0
+#define AVR32_FREQM_STATUS_BUSY_MASK                         0x00000001
+#define AVR32_FREQM_STATUS_BUSY_OFFSET                                0
+#define AVR32_FREQM_STATUS_BUSY_SIZE                                  1
+#define AVR32_FREQM_VALUE                                    0x0000000c
+#define AVR32_FREQM_VALUE_MASK                               0x00ffffff
+#define AVR32_FREQM_VALUE_OFFSET                                      0
+#define AVR32_FREQM_VALUE_SIZE                                       24
+#define AVR32_FREQM_VALUE_VALUE                                       0
+#define AVR32_FREQM_VALUE_VALUE_MASK                         0x00ffffff
+#define AVR32_FREQM_VALUE_VALUE_OFFSET                                0
+#define AVR32_FREQM_VALUE_VALUE_SIZE                                 24
+
+
+
+
+#ifdef __AVR32_ABI_COMPILER__
+
+
+typedef struct avr32_freqm_ctrl_t {
+    unsigned int                 :31;
+    unsigned int start           : 1;
+} avr32_freqm_ctrl_t;
+
+
+
+typedef struct avr32_freqm_mode_t {
+    unsigned int                 :11;
+    unsigned int clksel          : 5;
+    unsigned int refnum          : 8;
+    unsigned int                 : 7;
+    unsigned int refsel          : 1;
+} avr32_freqm_mode_t;
+
+
+
+typedef struct avr32_freqm_status_t {
+    unsigned int                 :31;
+    unsigned int busy            : 1;
+} avr32_freqm_status_t;
+
+
+
+typedef struct avr32_freqm_value_t {
+    unsigned int                 : 8;
+    unsigned int value           :24;
+} avr32_freqm_value_t;
+
+
+
+typedef struct avr32_freqm_ier_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_ier_t;
+
+
+
+typedef struct avr32_freqm_idr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_idr_t;
+
+
+
+typedef struct avr32_freqm_imr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_imr_t;
+
+
+
+typedef struct avr32_freqm_isr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_isr_t;
+
+
+
+typedef struct avr32_freqm_icr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_icr_t;
+
+
+
+typedef struct avr32_freqm_t {
+  union {
+          unsigned long                  ctrl      ;//0x0000
+          avr32_freqm_ctrl_t             CTRL      ;
+  };
+  union {
+          unsigned long                  mode      ;//0x0004
+          avr32_freqm_mode_t             MODE      ;
+  };
+  union {
+    const unsigned long                  status    ;//0x0008
+    const avr32_freqm_status_t           STATUS    ;
+  };
+  union {
+          unsigned long                  value     ;//0x000c
+          avr32_freqm_value_t            VALUE     ;
+  };
+  union {
+          unsigned long                  ier       ;//0x0010
+          avr32_freqm_ier_t              IER       ;
+  };
+  union {
+          unsigned long                  idr       ;//0x0014
+          avr32_freqm_idr_t              IDR       ;
+  };
+  union {
+    const unsigned long                  imr       ;//0x0018
+    const avr32_freqm_imr_t              IMR       ;
+  };
+  union {
+    const unsigned long                  isr       ;//0x001c
+    const avr32_freqm_isr_t              ISR       ;
+  };
+  union {
+          unsigned long                  icr       ;//0x0020
+          avr32_freqm_icr_t              ICR       ;
+  };
+} avr32_freqm_t;
+
+
+
+/*#ifdef __AVR32_ABI_COMPILER__*/
+#endif
+
+/*#ifdef AVR32_FREQM_230_H_INCLUDED*/
+#endif
+
diff --git a/headers/avr32/freqm_231.h b/headers/avr32/freqm_231.h
@@ -0,0 +1,322 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Model        : UC3A3128
+ * Revision     : $Revision: 62595 $
+ * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (on., 21 okt. 2009) $ 
+ *
+ ****************************************************************************/
+#ifndef AVR32_FREQM_231_H_INCLUDED
+#define AVR32_FREQM_231_H_INCLUDED
+
+#include "avr32/abi.h"
+
+
+/*
+ Note to user:
+
+ The following defines are always generated:
+ - Register offset: AVR32_FREQM_<register>
+ - Bitfield mask:   AVR32_FREQM_<register>_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<register>_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<register>_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<register>_<bitfield>_<value name>
+
+ The following defines are generated if they don't cause ambiguities,
+ i.e. the name is unique, or all values with that name are the same.
+ - Bitfield mask:   AVR32_FREQM_<bitfield>
+ - Bitfield offset: AVR32_FREQM_<bitfield>_OFFSET
+ - Bitfield size:   AVR32_FREQM_<bitfield>_SIZE
+ - Bitfield values: AVR32_FREQM_<bitfield>_<value name>
+ - Bitfield values: AVR32_FREQM_<value name>
+
+ All defines are sorted alphabetically.
+*/
+
+
+#define AVR32_FREQM_BUSY                                              0
+#define AVR32_FREQM_BUSY_MASK                                0x00000001
+#define AVR32_FREQM_BUSY_OFFSET                                       0
+#define AVR32_FREQM_BUSY_SIZE                                         1
+#define AVR32_FREQM_CLKSEL                                           16
+#define AVR32_FREQM_CLKSEL_CPU                               0x00000000
+#define AVR32_FREQM_CLKSEL_CRIPLEL                           0x0000000a
+#define AVR32_FREQM_CLKSEL_GENCLK0                           0x0000000b
+#define AVR32_FREQM_CLKSEL_GENCLK1                           0x0000000c
+#define AVR32_FREQM_CLKSEL_GENCLK2                           0x0000000d
+#define AVR32_FREQM_CLKSEL_GENCLK3                           0x0000000e
+#define AVR32_FREQM_CLKSEL_GENCLK4                           0x0000000f
+#define AVR32_FREQM_CLKSEL_GENCLK5                           0x00000010
+#define AVR32_FREQM_CLKSEL_HSB                               0x00000001
+#define AVR32_FREQM_CLKSEL_MASK                              0x001f0000
+#define AVR32_FREQM_CLKSEL_OFFSET                                    16
+#define AVR32_FREQM_CLKSEL_OSC0                              0x00000004
+#define AVR32_FREQM_CLKSEL_OSC1                              0x00000005
+#define AVR32_FREQM_CLKSEL_OSC32                             0x00000006
+#define AVR32_FREQM_CLKSEL_PBA                               0x00000002
+#define AVR32_FREQM_CLKSEL_PBB                               0x00000003
+#define AVR32_FREQM_CLKSEL_PLL0                              0x00000008
+#define AVR32_FREQM_CLKSEL_PLL1                              0x00000009
+#define AVR32_FREQM_CLKSEL_RCOSC                             0x00000007
+#define AVR32_FREQM_CLKSEL_SIZE                                       5
+#define AVR32_FREQM_CPU                                      0x00000000
+#define AVR32_FREQM_CRIPLEL                                  0x0000000a
+#define AVR32_FREQM_CTRL                                     0x00000000
+#define AVR32_FREQM_CTRL_START                                        0
+#define AVR32_FREQM_CTRL_START_MASK                          0x00000001
+#define AVR32_FREQM_CTRL_START_OFFSET                                 0
+#define AVR32_FREQM_CTRL_START_SIZE                                   1
+#define AVR32_FREQM_DONE                                              0
+#define AVR32_FREQM_DONE_MASK                                0x00000001
+#define AVR32_FREQM_DONE_OFFSET                                       0
+#define AVR32_FREQM_DONE_SIZE                                         1
+#define AVR32_FREQM_GENCLK0                                  0x0000000b
+#define AVR32_FREQM_GENCLK1                                  0x0000000c
+#define AVR32_FREQM_GENCLK2                                  0x0000000d
+#define AVR32_FREQM_GENCLK3                                  0x0000000e
+#define AVR32_FREQM_GENCLK4                                  0x0000000f
+#define AVR32_FREQM_GENCLK5                                  0x00000010
+#define AVR32_FREQM_HSB                                      0x00000001
+#define AVR32_FREQM_ICR                                      0x00000020
+#define AVR32_FREQM_ICR_DONE                                          0
+#define AVR32_FREQM_ICR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ICR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ICR_DONE_SIZE                                     1
+#define AVR32_FREQM_IDR                                      0x00000014
+#define AVR32_FREQM_IDR_DONE                                          0
+#define AVR32_FREQM_IDR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IDR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IDR_DONE_SIZE                                     1
+#define AVR32_FREQM_IER                                      0x00000010
+#define AVR32_FREQM_IER_DONE                                          0
+#define AVR32_FREQM_IER_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IER_DONE_OFFSET                                   0
+#define AVR32_FREQM_IER_DONE_SIZE                                     1
+#define AVR32_FREQM_IMR                                      0x00000018
+#define AVR32_FREQM_IMR_DONE                                          0
+#define AVR32_FREQM_IMR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_IMR_DONE_OFFSET                                   0
+#define AVR32_FREQM_IMR_DONE_SIZE                                     1
+#define AVR32_FREQM_ISR                                      0x0000001c
+#define AVR32_FREQM_ISR_DONE                                          0
+#define AVR32_FREQM_ISR_DONE_MASK                            0x00000001
+#define AVR32_FREQM_ISR_DONE_OFFSET                                   0
+#define AVR32_FREQM_ISR_DONE_SIZE                                     1
+#define AVR32_FREQM_MODE                                     0x00000004
+#define AVR32_FREQM_MODE_CLKSEL                                      16
+#define AVR32_FREQM_MODE_CLKSEL_CPU                          0x00000000
+#define AVR32_FREQM_MODE_CLKSEL_CRIPLEL                      0x0000000a
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK0                      0x0000000b
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK1                      0x0000000c
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK2                      0x0000000d
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK3                      0x0000000e
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK4                      0x0000000f
+#define AVR32_FREQM_MODE_CLKSEL_GENCLK5                      0x00000010
+#define AVR32_FREQM_MODE_CLKSEL_HSB                          0x00000001
+#define AVR32_FREQM_MODE_CLKSEL_MASK                         0x001f0000
+#define AVR32_FREQM_MODE_CLKSEL_OFFSET                               16
+#define AVR32_FREQM_MODE_CLKSEL_OSC0                         0x00000004
+#define AVR32_FREQM_MODE_CLKSEL_OSC1                         0x00000005
+#define AVR32_FREQM_MODE_CLKSEL_OSC32                        0x00000006
+#define AVR32_FREQM_MODE_CLKSEL_PBA                          0x00000002
+#define AVR32_FREQM_MODE_CLKSEL_PBB                          0x00000003
+#define AVR32_FREQM_MODE_CLKSEL_PLL0                         0x00000008
+#define AVR32_FREQM_MODE_CLKSEL_PLL1                         0x00000009
+#define AVR32_FREQM_MODE_CLKSEL_RCOSC                        0x00000007
+#define AVR32_FREQM_MODE_CLKSEL_SIZE                                  5
+#define AVR32_FREQM_MODE_REFNUM                                       8
+#define AVR32_FREQM_MODE_REFNUM_MASK                         0x0000ff00
+#define AVR32_FREQM_MODE_REFNUM_OFFSET                                8
+#define AVR32_FREQM_MODE_REFNUM_SIZE                                  8
+#define AVR32_FREQM_MODE_REFSEL                                       0
+#define AVR32_FREQM_MODE_REFSEL_MASK                         0x00000001
+#define AVR32_FREQM_MODE_REFSEL_OFFSET                                0
+#define AVR32_FREQM_MODE_REFSEL_REF_OSC32                    0x00000001
+#define AVR32_FREQM_MODE_REFSEL_REF_RCOSC                    0x00000000
+#define AVR32_FREQM_MODE_REFSEL_SIZE                                  1
+#define AVR32_FREQM_OSC0                                     0x00000004
+#define AVR32_FREQM_OSC1                                     0x00000005
+#define AVR32_FREQM_OSC32                                    0x00000006
+#define AVR32_FREQM_PBA                                      0x00000002
+#define AVR32_FREQM_PBB                                      0x00000003
+#define AVR32_FREQM_PLL0                                     0x00000008
+#define AVR32_FREQM_PLL1                                     0x00000009
+#define AVR32_FREQM_RCOSC                                    0x00000007
+#define AVR32_FREQM_REFNUM                                            8
+#define AVR32_FREQM_REFNUM_MASK                              0x0000ff00
+#define AVR32_FREQM_REFNUM_OFFSET                                     8
+#define AVR32_FREQM_REFNUM_SIZE                                       8
+#define AVR32_FREQM_REFSEL                                            0
+#define AVR32_FREQM_REFSEL_MASK                              0x00000001
+#define AVR32_FREQM_REFSEL_OFFSET                                     0
+#define AVR32_FREQM_REFSEL_REF_OSC32                         0x00000001
+#define AVR32_FREQM_REFSEL_REF_RCOSC                         0x00000000
+#define AVR32_FREQM_REFSEL_SIZE                                       1
+#define AVR32_FREQM_REF_OSC32                                0x00000001
+#define AVR32_FREQM_REF_RCOSC                                0x00000000
+#define AVR32_FREQM_START                                             0
+#define AVR32_FREQM_START_MASK                               0x00000001
+#define AVR32_FREQM_START_OFFSET                                      0
+#define AVR32_FREQM_START_SIZE                                        1
+#define AVR32_FREQM_STATUS                                   0x00000008
+#define AVR32_FREQM_STATUS_BUSY                                       0
+#define AVR32_FREQM_STATUS_BUSY_MASK                         0x00000001
+#define AVR32_FREQM_STATUS_BUSY_OFFSET                                0
+#define AVR32_FREQM_STATUS_BUSY_SIZE                                  1
+#define AVR32_FREQM_VALUE                                    0x0000000c
+#define AVR32_FREQM_VALUE_MASK                               0x00ffffff
+#define AVR32_FREQM_VALUE_OFFSET                                      0
+#define AVR32_FREQM_VALUE_SIZE                                       24
+#define AVR32_FREQM_VALUE_VALUE                                       0
+#define AVR32_FREQM_VALUE_VALUE_MASK                         0x00ffffff
+#define AVR32_FREQM_VALUE_VALUE_OFFSET                                0
+#define AVR32_FREQM_VALUE_VALUE_SIZE                                 24
+
+
+
+
+#ifdef __AVR32_ABI_COMPILER__
+
+
+typedef struct avr32_freqm_ctrl_t {
+    unsigned int                 :31;
+    unsigned int start           : 1;
+} avr32_freqm_ctrl_t;
+
+
+
+typedef struct avr32_freqm_mode_t {
+    unsigned int                 :11;
+    unsigned int clksel          : 5;
+    unsigned int refnum          : 8;
+    unsigned int                 : 7;
+    unsigned int refsel          : 1;
+} avr32_freqm_mode_t;
+
+
+
+typedef struct avr32_freqm_status_t {
+    unsigned int                 :31;
+    unsigned int busy            : 1;
+} avr32_freqm_status_t;
+
+
+
+typedef struct avr32_freqm_value_t {
+    unsigned int                 : 8;
+    unsigned int value           :24;
+} avr32_freqm_value_t;
+
+
+
+typedef struct avr32_freqm_ier_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_ier_t;
+
+
+
+typedef struct avr32_freqm_idr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_idr_t;
+
+
+
+typedef struct avr32_freqm_imr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_imr_t;
+
+
+
+typedef struct avr32_freqm_isr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_isr_t;
+
+
+
+typedef struct avr32_freqm_icr_t {
+    unsigned int                 :31;
+    unsigned int done            : 1;
+} avr32_freqm_icr_t;
+
+
+
+typedef struct avr32_freqm_t {
+  union {
+          unsigned long                  ctrl      ;//0x0000
+          avr32_freqm_ctrl_t             CTRL      ;
+  };
+  union {
+          unsigned long                  mode      ;//0x0004
+          avr32_freqm_mode_t             MODE      ;
+  };
+  union {
+    const unsigned long                  status    ;//0x0008
+    const avr32_freqm_status_t           STATUS    ;
+  };
+  union {
+          unsigned long                  value     ;//0x000c
+          avr32_freqm_value_t            VALUE     ;
+  };
+  union {
+          unsigned long                  ier       ;//0x0010
+          avr32_freqm_ier_t              IER       ;
+  };
+  union {
+          unsigned long                  idr       ;//0x0014
+          avr32_freqm_idr_t              IDR       ;
+  };
+  union {
+    const unsigned long                  imr       ;//0x0018
+    const avr32_freqm_imr_t              IMR       ;
+  };
+  union {
+    const unsigned long                  isr       ;//0x001c
+    const avr32_freqm_isr_t              ISR       ;
+  };
+  union {
+          unsigned long                  icr       ;//0x0020
+          avr32_freqm_icr_t              ICR       ;
+  };
+} avr32_freqm_t;
+
+
+
+/*#ifdef __AVR32_ABI_COMPILER__*/
+#endif
+
+/*#ifdef AVR32_FREQM_231_H_INCLUDED*/
+#endif
+