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Write perf maps using JIT trace information.

This should probably be behind a switch or OS detection option of some sort.

Signed-off-by: Corbin Simpson <cds@corbinsimpson.com> <simpsoco@google.com>
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MostAwesomeDude committed Feb 28, 2015
1 parent ddd4667 commit 2357ae0f46d73567a6ed6560e3e0aef14e73060b
Showing with 28 additions and 4 deletions.
  1. +28 −4 main.py
32 main.py
@@ -12,10 +12,12 @@
# License for the specific language governing permissions and limitations
# under the License.
import os
import sys
from rpython.jit.codewriter.policy import JitPolicy
from rpython.rlib.debug import debug_print
from rpython.rlib.jit import JitHookInterface
from rpython.rlib.rpath import rjoin
from typhon.arguments import Configuration
@@ -44,10 +46,6 @@ def dirname(p):
return head
def jitPolicy(driver):
return JitPolicy()
def loadPrelude(config, recorder, vat):
scope = safeScope()
code = obtainModule(rjoin(config.libraryPath, "prelude.ty"), scope.keys(),
@@ -159,6 +157,32 @@ def entryPoint(argv):
return 0
def writePerfMap(s):
path = "/tmp/perf-%d.map" % os.getpid()
fd = os.open(path, os.O_CREAT | os.O_APPEND | os.O_WRONLY, 0777)
os.write(fd, s)
os.close(fd)
class TyphonJitHooks(JitHookInterface):
def after_compile(self, debug_info):
s = "%x %x %s\n" % (debug_info.asminfo.asmaddr,
debug_info.asminfo.asmlen,
"<Typhon JIT trace>")
writePerfMap(s)
def after_compile_bridge(self, debug_info):
s = "%x %x %s\n" % (debug_info.asminfo.asmaddr,
debug_info.asminfo.asmlen,
"<Typhon JIT bridge>")
writePerfMap(s)
def jitpolicy(driver):
return JitPolicy(TyphonJitHooks())
def target(*args):
return entryPoint, None

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