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6.375 Final Project
C++ Perl C Python Tcl
branch: master

Pushing pair debugging changes.

latest commit ee7006d72e
Bhaskar Mookerji authored
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data added scemi, fpga, sim, tb, etc. host processing and interface nonsense
docs Added synthesis information
fpga added scemi, fpga, sim, tb, etc. host processing and interface nonsense
prototype
ref Added microarchitecture design template
scemi added scemi, fpga, sim, tb, etc. host processing and interface nonsense
sim //this must be a configreg because we want dispatch_alu, check_comple…
src Pushing pair debugging changes.
tb
tools added scemi, fpga, sim, tb, etc. host processing and interface nonsense
README added design exploration
tomasulo.bspec

README

6.375 Complex Digital Systems 
Final Project Repository
Authors: David S. Greenberg and Bhaskar Mookerji

Repository Contents:
data/      Test routines
docs/      Proposal and report deliverables organized by date
           Latest changes made to April_06 directory
fpga/      FPGA build files
proto*/    Depricated pre-design interface
ref/       Reference documents for design and class stuff
scemi/     SCE-MI source files
sim/       Bluespec simulator build files
src/       Bluespec implementation
tb/        Test bench
tools/     Miscellaneous tools for debugging traces
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