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Tests for MAX2837 with OLS Capture.

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commit 23b136bde6addcc82348ab6b1b94da64e77c7b82 1 parent d876ae7
@bvernoux bvernoux authored
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18 test_max2837/Makefile
@@ -0,0 +1,18 @@
+# Makefile
+
+CC=mingw32-gcc
+
+CFLAGS=-c -Wall -DTEST -DBUS_PIRATE -DDEBUG -Dgpio_set
+LDFLAGS=-fno-exceptions -s
+
+all: max2837.exe
+
+%.exe:%.o
+ $(CC) $(LDFLAGS) $< -o $@
+
+%.o:%.c
+ $(CC) $(CFLAGS) $< -o $@
+
+clean:
+ -$(RM) *.o
+ -$(RM) *.exe
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296 test_max2837/max2837.c
@@ -0,0 +1,296 @@
+/*
+ * 'gcc -DTEST -DDEBUG -O2 -o test max2837.c' prints out what test
+ * program would do if it had a real spi library
+ *
+ * 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus
+ * pirate commands to do the same thing.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "max2837.h"
+#include "max2837_regs.def" // private register def macros
+
+#if (defined DEBUG || defined BUS_PIRATE)
+#include <stdio.h>
+#define LOG printf
+#else
+#define LOG(x,...)
+#include <libopencm3/lpc43xx/ssp.h>
+#include <libopencm3/lpc43xx/scu.h>
+#include <libopencm3/lpc43xx/gpio.h>
+#include "hackrf_core.h"
+#endif
+
+/* Default register values. */
+static uint16_t max2837_regs_default[MAX2837_NUM_REGS] = {
+ 0x150, /* 0 */
+ 0x002, /* 1 */
+ 0x1f4, /* 2 */
+ 0x1b9, /* 3 */
+ 0x00a, /* 4 */
+ 0x080, /* 5 */
+ 0x006, /* 6 */
+ 0x000, /* 7 */
+ 0x080, /* 8 */
+ 0x018, /* 9 */
+ 0x058, /* 10 */
+ 0x016, /* 11 */
+ 0x24f, /* 12 */
+ 0x150, /* 13 */
+ 0x1c5, /* 14 */
+ 0x081, /* 15 */
+ 0x01c, /* 16 */
+ 0x155, /* 17 */
+ 0x155, /* 18 */
+ 0x153, /* 19 */
+ 0x241, /* 20 */
+ 0x02c, /* 21 */
+ 0x1a9, /* 22 */
+ 0x24f, /* 23 */
+ 0x180, /* 24 */
+ 0x100, /* 25 */
+ 0x3ca, /* 26 */
+ 0x3e3, /* 27 */
+ 0x0c0, /* 28 */
+ 0x3f0, /* 29 */
+ 0x080, /* 30 */
+ 0x000 }; /* 31 */
+
+uint16_t max2837_regs[MAX2837_NUM_REGS];
+
+/* Mark all regsisters dirty so all will be written at init. */
+uint32_t max2837_regs_dirty = 0xffffffff;
+
+/* Set up all registers according to defaults specified in docs. */
+void max2837_init(void)
+{
+ LOG("# max2837_init\n");
+ memcpy(max2837_regs, max2837_regs_default, sizeof(max2837_regs));
+ max2837_regs_dirty = 0xffffffff;
+
+ /* Write default register values to chip. */
+ max2837_regs_commit();
+}
+
+/*
+ * Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
+ * set our own default register configuration.
+ */
+#if (defined DEBUG || defined BUS_PIRATE)
+void max2837_setup(void)
+{
+}
+#else
+void max2837_setup(void)
+{
+ /* FIXME speed up once everything is working reliably */
+ const uint8_t serial_clock_rate = 32;
+ const uint8_t clock_prescale_rate = 128;
+
+ /* Configure XCVR_CTL GPIO pins. */
+ scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
+ scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);
+ scu_pinmux(SCU_XCVR_TXENABLE, SCU_GPIO_FAST);
+
+ /* Set GPIO pins as outputs. */
+ GPIO2_DIR |= (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE);
+
+ /* disable everything */
+ gpio_clear(PORT_XCVR_ENABLE,
+ (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
+
+ /*
+ * Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the
+ * SPI bus for the MAX2837. FIXME: this should probably be somewhere else.
+ */
+ scu_pinmux(SCU_CS_AD, SCU_GPIO_FAST);
+ GPIO2_DIR |= PIN_CS_AD;
+ gpio_set(PORT_CS_AD, PIN_CS_AD);
+
+ /* Configure SSP1 Peripheral (to be moved later in SSP driver) */
+ scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+ scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+
+ ssp_init(SSP1_NUM,
+ SSP_DATA_16BITS,
+ SSP_FRAME_SPI,
+ SSP_CPOL_0_CPHA_0,
+ serial_clock_rate,
+ clock_prescale_rate,
+ SSP_MODE_NORMAL,
+ SSP_MASTER,
+ SSP_SLAVE_OUT_ENABLE);
+
+ max2837_init();
+
+ /* Use SPI control instead of B1-B7 pins for gain settings. */
+ set_MAX2837_TXVGA_GAIN_SPI_EN(1);
+ set_MAX2837_TXVGA_GAIN_MSB_SPI_EN(1);
+ set_MAX2837_TXVGA_GAIN(0x3f); /* maximum attenuation */
+ set_MAX2837_LNAgain_SPI_EN(1);
+ set_MAX2837_LNAgain(MAX2837_LNAgain_MAX); /* maximum gain */
+ set_MAX2837_VGAgain_SPI_EN(1);
+ set_MAX2837_VGA(0x00); /* minimum attenuation */
+
+ max2837_regs_commit();
+}
+#endif
+
+/* SPI register read. */
+uint16_t max2837_spi_read(uint8_t r) {
+ return 0;
+}
+
+/* SPI register write */
+void max2837_spi_write(uint8_t r, uint16_t v) {
+
+#ifdef BUS_PIRATE
+ LOG("{0x%02x 0x%02x]\n", 0x00 | ((uint16_t)r<<2) | ((v>>8) & 0x3),
+ v & 0xff);
+#elif DEBUG
+ LOG("0x%03x -> reg%d\n", v, r);
+#else
+ ssp_write(SSP1_NUM, (uint16_t)((r << 10) | (v & 0x3ff)));
+#endif
+}
+
+uint16_t max2837_reg_read(uint8_t r)
+{
+ if ((max2837_regs_dirty >> r) & 0x1) {
+ max2837_spi_read(r);
+ };
+ return max2837_regs[r];
+}
+
+void max2837_reg_write(uint8_t r, uint16_t v)
+{
+ max2837_regs[r] = v;
+ max2837_spi_write(r, v);
+ MAX2837_REG_SET_CLEAN(r);
+}
+
+/* This functions should not be needed, and might be confusing. DELETE. */
+void max2837_regs_read(void)
+{
+ ;
+}
+
+static inline void max2837_reg_commit(uint8_t r)
+{
+ max2837_reg_write(r,max2837_regs[r]);
+}
+
+void max2837_regs_commit(void)
+{
+ int r;
+ for(r = 0; r < MAX2837_NUM_REGS; r++) {
+ if ((max2837_regs_dirty >> r) & 0x1) {
+ max2837_reg_commit(r);
+ }
+ }
+}
+
+void max2837_start(void)
+{
+ LOG("# max2837_start\n");
+ set_MAX2837_EN_SPI(1);
+ max2837_regs_commit();
+/*
+ gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_ENABLE);
+*/
+}
+
+void max2837_tx(void)
+{
+ LOG("# max2837_tx\n");
+/*
+ gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE);
+*/
+}
+
+void max2837_stop(void)
+{
+ LOG("# max2837_stop\n");
+ set_MAX2837_EN_SPI(0);
+ max2837_regs_commit();
+/*
+ gpio_clear(PORT_XCVR_ENABLE,
+ (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
+*/
+}
+
+void max2837_set_frequency(uint32_t freq)
+{
+ uint8_t band;
+ uint8_t lna_band;
+ uint32_t div_frac;
+ uint32_t div_int;
+ uint32_t div_rem;
+ uint32_t div_cmp;
+ int i;
+
+ /* Select band. Allow tuning outside specified bands. */
+ if (freq < 2400000000U) {
+ band = MAX2837_LOGEN_BSW_2_3;
+ lna_band = MAX2837_LNAband_2_4;
+ }
+ else if (freq < 2500000000U) {
+ band = MAX2837_LOGEN_BSW_2_4;
+ lna_band = MAX2837_LNAband_2_4;
+ }
+ else if (freq < 2600000000U) {
+ band = MAX2837_LOGEN_BSW_2_5;
+ lna_band = MAX2837_LNAband_2_6;
+ }
+ else {
+ band = MAX2837_LOGEN_BSW_2_6;
+ lna_band = MAX2837_LNAband_2_6;
+ }
+
+ LOG("# max2837_set_frequency %ld, band %d, lna band %d\n",
+ freq, band, lna_band);
+
+ /* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
+ div_int = freq / 30000000;
+ div_rem = freq % 30000000;
+ div_frac = 0;
+ div_cmp = 30000000;
+ for( i = 0; i < 20; i++) {
+ div_frac <<= 1;
+ div_cmp >>= 1;
+ if (div_rem > div_cmp) {
+ div_frac |= 0x1;
+ div_rem -= div_cmp;
+ }
+ }
+ LOG("# int %ld, frac %ld\n", div_int, div_frac);
+
+ /* Band settings */
+ set_MAX2837_LOGEN_BSW(band);
+ set_MAX2837_LNAband(lna_band);
+
+ /* Write order matters here, so commit INT and FRAC_HI before
+ * committing FRAC_LO, which is the trigger for VCO
+ * auto-select. TODO - it's cleaner this way, but it would be
+ * faster to explicitly commit the registers explicitly so the
+ * dirty bits aren't scanned twice. */
+ set_MAX2837_SYN_INT(div_int);
+ set_MAX2837_SYN_FRAC_HI((div_frac >> 10) & 0x3ff);
+ max2837_regs_commit();
+ set_MAX2837_SYN_FRAC_LO(div_frac & 0x3ff);
+ max2837_regs_commit();
+}
+
+#ifdef TEST
+int main(int ac, char **av)
+{
+ max2837_init();
+ max2837_start();
+ max2837_tx();
+ max2837_set_frequency(2441000000);
+ max2837_stop();
+}
+#endif //TEST
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46 test_max2837/max2837.h
@@ -0,0 +1,46 @@
+#ifndef __MAX2837_H
+#define __MAX2837_H
+
+/* TODO - make this a private header for max2837.c only, make new max2837.h */
+
+/* 32 registers, each containing 10 bits of data. */
+#define MAX2837_NUM_REGS 32
+
+/* TODO - these externs will be local to max2837.c ... don't define here? */
+extern uint16_t max2837_regs[MAX2837_NUM_REGS];
+extern uint32_t max2837_regs_dirty;
+
+#define MAX2837_REG_SET_CLEAN(r) max2837_regs_dirty &= ~(1UL<<r)
+#define MAX2837_REG_SET_DIRTY(r) max2837_regs_dirty |= (1UL<<r)
+
+/* Initialize chip. */
+extern void max2837_init(void);
+extern void max2837_setup(void);
+
+/* Read a register via SPI. Save a copy to memory and return
+ * value. Mark clean. */
+extern uint16_t max2837_reg_read(uint8_t r);
+
+/* Write value to register via SPI and save a copy to memory. Mark
+ * clean. */
+extern void max2837_reg_write(uint8_t r, uint16_t v);
+
+/* Read all registers from chip and copy to memory. Mark all clean. */
+extern void max2837_regs_read(void);
+
+/* Write all dirty registers via SPI from memory. Mark all clean. Some
+ * operations require registers to be written in a certain order. Use
+ * provided routines for those operations. */
+extern void max2837_regs_commit(void);
+
+/* Turn on/off all chip functions. Does not control oscillator and CLKOUT */
+extern void max2837_start(void);
+extern void max2837_stop(void);
+
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+extern void max2837_set_frequency(uint32_t freq);
+
+extern void max2837_tx(void);
+
+#endif // __MAX2837_H
View
44 test_max2837/max2837_BusPirate.txt
@@ -0,0 +1,44 @@
+# max2837_init
+{0x01 0x50]
+{0x04 0x02]
+{0x09 0xf4]
+{0x0d 0xb9]
+{0x10 0x0a]
+{0x14 0x80]
+{0x18 0x06]
+{0x1c 0x00]
+{0x20 0x80]
+{0x24 0x18]
+{0x28 0x58]
+{0x2c 0x16]
+{0x32 0x4f]
+{0x35 0x50]
+{0x39 0xc5]
+{0x3c 0x81]
+{0x40 0x1c]
+{0x45 0x55]
+{0x49 0x55]
+{0x4d 0x53]
+{0x52 0x41]
+{0x54 0x2c]
+{0x59 0xa9]
+{0x5e 0x4f]
+{0x61 0x80]
+{0x65 0x00]
+{0x6b 0xca]
+{0x6f 0xe3]
+{0x70 0xc0]
+{0x77 0xf0]
+{0x78 0x80]
+{0x7c 0x00]
+# max2837_start
+{0x40 0x1d]
+# max2837_tx
+# max2837_set_frequency -1853967296, band 1, lna band 0
+# int 81, frac 384478
+{0x01 0x50]
+{0x49 0x77]
+{0x4d 0x51]
+{0x45 0xde]
+# max2837_stop
+{0x40 0x1c]
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405 test_max2837/max2837_regs.def
@@ -0,0 +1,405 @@
+/* -*- mode: c -*- */
+
+#ifndef __MAX2837_REGS_DEF
+#define __MAX2837_REGS_DEF
+
+/* Generate static inline accessors that operate on the global
+ * regs. Done this way to (1) allow defs to be scraped out and used
+ * elsewhere, e.g. in scripts, (2) to avoid dealing with endian
+ * (structs). This may be used in firmware, or on host predefined
+ * register loads. */
+
+/* On set_, register is always set dirty, even if nothing
+ * changed. This makes sure that write that have side effects,
+ * e.g. frequency setting, are not skipped. */
+
+/* n=name, r=regnum, o=offset (bits from LSB), l=length (bits) */
+#define __MREG__(n,r,o,l) \
+static inline uint16_t get_##n(void) { \
+ return (max2837_regs[r] >> o) & ((1<<l)-1); \
+} \
+static inline void set_##n(uint16_t v) { \
+ max2837_regs[r] &= ~(((1<<l)-1)<<(o-l+1)); \
+ max2837_regs[r] |= ((v&((1<<l)-1))<<(o-l+1)); \
+ MAX2837_REG_SET_DIRTY(r); \
+}
+
+/* REG 0 */
+__MREG__(MAX2837_LNA_EN, 0,0,1)
+__MREG__(MAX2837_Mixer_EN, 0,1,1)
+__MREG__(MAX2837_RxLO_EN, 0,2,1)
+__MREG__(MAX2837_Lbias, 0,4,2)
+#define MAX2837_Lbias_LOWEST 0
+#define MAX2837_Lbias_NOMINAL 2
+#define MAX2837_Lbias_HIGHEST 3
+__MREG__(MAX2837_Mbias, 0,6,2)
+#define MAX2837_Mbias_LOWEST 0
+#define MAX2837_Mbias_NOMINAL 2
+#define MAX2837_Mbias_HIGHEST 3
+__MREG__(MAX2837_buf, 0,8,2)
+#define MAX2837_buf_LOWEST 0
+#define MAX2837_buf_NOMINAL 2
+#define MAX2837_buf_HIGHEST 3
+__MREG__(MAX2837_LNAband, 0,9,1)
+#define MAX2837_LNAband_2_4 0 // 2.3-2.5 GHz
+#define MAX2837_LNAband_2_6 1 // 2.5-2.7 GHz
+
+/* REG 1 */
+__MREG__(MAX2837_LNAtune, 1,0,1)
+#define MAX2837_LNAtune_NOMINAL 0
+#define MAX2837_LNAtune_DOWN 1
+__MREG__(MAX2837_LNAde_Q,1,1,1)
+#define MAX2837_LNAde_Q_NOMINAL 0
+#define MAX2837_LNAde_Q_2DB 1
+__MREG__(MAX2837_LNAgain,1,4,3)
+#define MAX2837_LNAgain_MAX 0b000 // Pad in 8dB steps, bits reversed
+#define MAX2837_LNAgain_M8 0b100
+#define MAX2837_LNAgain_M16 0b010
+#define MAX2837_LNAgain_M24 0b110
+#define MAX2837_LNAgain_M32 0b001
+#define MAX2837_LNAgain_M40 0b111
+__MREG__(MAX2837_iqerr_trim,1,9,5)
+// 0b00000 = +4.0 degree phase error
+// 0b01111 = 0.0
+// 0b11111 = -4.0
+
+/* REG 2 */
+__MREG__(MAX2837_LPF_EN,2,0,1)
+__MREG__(MAX2837_TxBB_EN,2,1,1)
+__MREG__(MAX2837_ModeCtrl,2,3,2)
+#define MAX2837_ModeCtrl_RxCalibration 0
+#define MAX2837_ModeCtrl_RxLPF 1
+#define MAX2837_ModeCtrl_TxLPF 2
+#define MAX2837_ModeCtrl_LPFTrim 3
+__MREG__(MAX2837_FT,2,7,4)
+#define MAX2837_FT_1_75M 0
+#define MAX2837_FT_2_5M 1
+#define MAX2837_FT_3_5M 2
+#define MAX2837_FT_5M 3
+#define MAX2837_FT_5_5M 4
+#define MAX2837_FT_6M 5
+#define MAX2837_FT_7M 6
+#define MAX2837_FT_8M 7
+#define MAX2837_FT_9M 8
+#define MAX2837_FT_10M 9
+#define MAX2837_FT_12M 10
+#define MAX2837_FT_14M 11
+#define MAX2837_FT_15M 12
+#define MAX2837_FT_20M 13
+#define MAX2837_FT_24M 14
+#define MAX2837_FT_28M 15
+__MREG__(MAX2837_dF,2,9,2)
+#define MAX2837_dF_M10 0b00 // -10%
+#define MAX2837_dF_NOMINAL 0b01
+#define MAX2837_dF_10 0b11 // +10%
+
+/* REG 3 */
+__MREG__(MAX2837_PT_SPI,3,3,4) // slowest=1111 fastest=0000 nom=1001
+__MREG__(MAX2837_Bqd,3,6,3) // MSB doubles bias current, lower 2 25% each
+__MREG__(MAX2837_TxRPCM,3,9,3) // 000=1.00V, 0.05V steps, 111 not allowed
+
+/* REG 4 */
+__MREG__(MAX2837_RP,4,1,2) // 20% steps, 00=lowest, 11=highest
+__MREG__(MAX2837_TxBuff,4,3,2) // 25% steps, 00=lowest, 11=highest
+__MREG__(MAX2837_VGA_EN,4,4,1)
+__MREG__(MAX2837_VGAMUX_enable,4,5,1)
+__MREG__(MAX2837_BUFF_Curr,4,7,2) // 250uA + 125uA steps
+__MREG__(MAX2837_BUFF_VCM,4,9,2) // VGA common mode
+#define MAX2837_BUFF_VCM_0_9 0 // 0.9V
+#define MAX2837_BUFF_VCM_1_0 1 // 1.0V
+#define MAX2837_BUFF_VCM_1_1 2 // 1.1V
+#define MAX2837_BUFF_VCM_1_25 3 // 1.25V
+
+/* REG 5 */
+__MREG__(MAX2837_VGA,5,4,5) // max=00000, attenuation in 2dB steps
+__MREG__(MAX2837_sel_In1_In2,5,5,1)
+#define MAX2837_sel_In1_In2_RXVGA 0
+#define MAX2837_sel_In1_In2_TXAM 1
+__MREG__(MAX2837_turbo15n20,5,6,1)
+__MREG__(MAX2837_VGA_Curr,5,8,2) // 01=default, 00=-33%, 10=+33%, 11=+67%
+__MREG__(MAX2837_fuse_arm,5,9,1)
+
+/* REG 6 */
+__MREG__(MAX2837_RSSI_EN,6,6,1) // enable RSSI
+__MREG__(MAX2837_RSSI_MUX,6,7,1)
+#define MAX2837_RSSI_MUX_RSSI 0
+#define MAX2837_RSSI_MUX_TEMP 1
+__MREG__(MAX2837_RSSI_MODE,6,8,1) // set to override RXHP pin
+__MREG__(MAX2837_LPF_MODE_SEL,6,9,1) // set to enable mode in reg 2 ModeCtrl
+
+/* REG 7 is R/O */
+// D4:0 ts_adc (temp sensor)
+// D9:5 zeros or test outputs
+
+/* REG 8 */
+__MREG__(MAX2837_LNAgain_SPI_EN,8,0,1) // set to override pin control of LNA
+__MREG__(MAX2837_VGAgain_SPI_EN,8,1,0) // set to override pin control of VGA
+__MREG__(MAX2837_EN_Bias_Trim,8,2,1) // route bias current to bondpad
+__MREG__(MAX2837_BIAS_TRIM_SPI,8,7,3) // down=00000, up=11111, nom=10000
+__MREG__(MAX2837_BIAS_TRIM_CNTRL,8,8,1) // enable BIAS_TRIM_SPI value
+__MREG__(MAX2837_RX_IQERR_SPI_EN,8,9,1) // ???
+
+/* REG 9 */
+__MREG__(MAX2837_ts_adc_trigger,9,0,1) // temp sensor trigger (one shot)
+__MREG__(MAX2837_ts_en,9,1,1) // temp sensor enable (before trigger)
+__MREG__(MAX2837_LPFtrim_SPI_EN,9,2,1)
+__MREG__(MAX2837_DOUT_DRVH,9,3,1)
+#define MAX2837_DOUT_DRVH_1X 0
+#define MAX2837_DOUT_DRVH_4X 1
+__MREG__(MAX2837_DOUT_PU,9,4,1) // set to enable CMOS PU (default), else OD
+__MREG__(MAX2837_DOUT_SEL,9,7,3)
+#define MAX2837_DOUT_SEL_SPI 0 // default, SPI comm
+#define MAX2837_DOUT_SEL_PLL_LOCK_DETECT 1
+#define MAX2837_DOUT_SEL_VAS_TEST_OUT 2
+#define MAX2837_DOUT_SEL_HPFSM_TEST_OUT 3
+#define MAX2837_DOUT_SEL_LOGEN_TRIM_OUT 4
+#define MAX2837_DOUT_SEL_RX_FUSE_GASKET 5
+#define MAX2837_DOUT_SEL_TX_FUSE_GASKET 6
+#define MAX2837_DOUT_SEL_ZERO 7
+__MREG__(MAX2837_fuse_sh,9,8,1) // ???
+__MREG__(MAX2837_fuse_burn_gkt,9,9,1) // enable (don't)
+
+/* REG 10 */
+__MREG__(MAX2837_TXCAL_GAIN,10,2,2) // 00=default, steps of +10dB
+__MREG__(MAX2837_TXCAL_V2I_FILT,10,5,3) // 000=+12%, 111=-16%, 011=default
+__MREG__(MAX2837_TX_BIAS_ADJ,10,7,2) // 00=-10%, 01=default, 10=+10%, 11=+20%
+
+/* REG 11 */
+__MREG__(MAX2837_AMD_SPI_EN,11,0,1) // enable AM detector
+__MREG__(MAX2837_TXMXR_V2I_GAIN,11,4,4) // 0000=max, steps of -0.5dB
+
+/* REG 12 */
+__MREG__(MAX2837_HPC_10M,12,1,2) // steps of 0.4uS (0.0-1.2)
+__MREG__(MAX2837_HPC_10M_GAIN,12,3,2) // steps of 0.4uS (0.0-1.2)
+__MREG__(MAX2837_HPC_600K,12,6,3) // steps of 0.8uS (0.0-4.8), 7=stay 1
+__MREG__(MAX2837_HPC_600K_GAIN,12,9,3) // steps of 0.8uS (0.0-4.8), 7=stay 1
+
+/* REG 13 */
+__MREG__(MAX2837_HPC_100K,13,1,2) // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_100K_GAIN,13,3,2) // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_30K,13,5,2) // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_30K_GAIN,13,7,2) // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_1K,13,9,2) // steps of 3.2uS (0.0-9.6)
+
+/* REG 14 */
+__MREG__(MAX2837_HPC_1K_GAIN,14,1,2) // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_DELAY,14,3,2) // steps of 0.2uS (0.0-0.6)
+__MREG__(MAX2837_HPC_STOP,14,5,2)
+#define MAX2837_STOP_100 0
+#define MAX2837_STOP_1K 1
+#define MAX2837_STOP_30K 2
+#define MAX2837_STOP_100K 3
+__MREG__(MAX2837_HPC_STOP_M2,14,7,2)
+#define MAX2837_STOP_M2_1K 0
+#define MAX2837_STOP_M2_30K 1
+#define MAX2837_STOP_M2_100K 2
+#define MAX2837_STOP_M2_600K 3
+__MREG__(MAX2837_HPC_RXGAIN_EN,14,8,1) // RXVGA HPFSM re-triggered by B7 & B6
+__MREG__(MAX2837_HPC_MODE,14,9,1) // use RXHP
+
+/* REG 15 */
+__MREG__(MAX2837_HPC_DIVH,15,0,1)
+#define MAX2837_HPC_DIVH_20M 0
+#define MAX2837_HPC_DIVH_40M 1
+__MREG__(MAX2837_HPC_TST,15,5,5) // filter test modes ... see doc
+__MREG__(MAX2837_HPC_SEQ_BYP,15,6,1) // set to bypass programmed sequence
+__MREG__(MAX2837_DOUT_CSB_SEL,15,7,1) // set to tri state DOUT when CSB high
+
+/* REG 16 */
+__MREG__(MAX2837_EN_SPI,16,0,1) // enable overall chip
+__MREG__(MAX2837_CAL_SPI,16,1,1) // enable calibration mode
+__MREG__(MAX2837_LOGEN_SPI_EN,16,2,1) // ???
+__MREG__(MAX2837_SYN_SPI_EN,16,3,1) // enable synthesizer
+__MREG__(MAX2837_VAS_SPI_EN,16,4,1) // enable VCO autoselect
+__MREG__(MAX2837_PADRV_SPI_EN,16,5,1) // enable power amp
+__MREG__(MAX2837_PADAC_SPI_EN,16,6,1) // enable power amp bias DAC always
+__MREG__(MAX2837_PADAC_TX_EN,16,7,1) // enable power amp bias only if TX pin
+__MREG__(MAX2837_TXMX_SPI_EN,16,8,1) // enable TX mixer
+__MREG__(MAX2837_TXLO_SPI_EN,16,9,1) // enable TX LO
+
+/* REG 17 */
+__MREG__(MAX2837_SYN_FRAC_LO,17,9,10)
+
+/* REG 18 */
+__MREG__(MAX2837_SYN_FRAC_HI,18,9,10)
+
+/* REG 19 */
+__MREG__(MAX2837_SYN_INT,19,7,8)
+__MREG__(MAX2837_LOGEN_BSW,19,9,2)
+#define MAX2837_LOGEN_BSW_2_3 0 // 2300 - <2400 MHz
+#define MAX2837_LOGEN_BSW_2_4 1 // 2400 - <2500 MHz
+#define MAX2837_LOGEN_BSW_2_5 2 // 2500 - <2600 MHz
+#define MAX2837_LOGEN_BSW_2_6 3 // 2600 - <2700 MHz
+
+/* REG 20 */
+__MREG__(MAX2837_SYN_MODE,20,0,1)
+#define MAX2837_SYN_MODE_INTEGER 0
+#define MAX2837_SYN_MODE_FRACTIONAL 1
+__MREG__(MAX2837_SYN_REF_DIV,20,2,2)
+#define MAX2837_SYN_REF_DIV_1 0
+#define MAX2837_SYN_REF_DIV_2 1
+#define MAX2837_SYN_REF_DIV_4 2
+#define MAX2837_SYN_REF_DIV_8 3
+__MREG__(MAX2837_SYN_CURRENT_,20,4,2)
+#define MAX2837_SYN_CURRENT_3_2_DIFF 0 // 3.2mA differential
+#define MAX2837_SYN_CURRENT_1_6_DIFF 1 // 1.6mA differential
+#define MAX2837_SYN_CURRENT_1_6_SINGLE 2 // 1.6mA single-ended
+#define MAX2837_SYN_CURRENT_0_8_SINGLE 3 // 0.8mA single-ended
+__MREG__(MAX2837_SYN_CLOCKOUT_DRIVE,20,5,1)
+#define MAX2837_SYN_CLOCKOUT_DRIVE_1X 0
+#define MAX2837_SYN_CLOCKOUT_DRIVE_4X 1
+__MREG__(MAX2837_SYN_TURBO_EN,20,6,1) // ???
+__MREG__(MAX2837_SYN_BIAS_SPI,20,7,1) // Use trim value below
+__MREG__(MAX2837_SYN_BIAS_TRIM,20,9,2) // 00=max 10=default 11=min
+
+/* REG 21 */
+__MREG__(MAX2837_SYN_CP_COMMON_MODE_EN,21,0,1)
+__MREG__(MAX2837_SYN_PRESCALER_BIAS_BOOST,21,1,1) // 0=default 1=+20%
+__MREG__(MAX2837_SYN_CP_BETA_EN,21,2,0)
+__MREG__(MAX2837_SYN_SD_CLOCK_SEL,21,3,1)
+#define MAX2837_SYN_SD_CLOCK_PFD 0 // from PFD reset
+#define MAX2837_SYN_SD_CLOCK_PRE 1 // from prescaler
+__MREG__(MAX2837_SYN_CP_PULSE_WIDTH_ADJ,21,4,1) // 0=default 1=-20%
+__MREG__(MAX2837_SYN_CP_LIN_CUR,21,6,2) // +3% per step
+__MREG__(MAX2837_SYN_TEST_OUT,21,9,3) // high bit locks CP in test mode
+#define MAX2837_SYN_TEST_LOCK_DETECT 0b000
+#define MAX2837_SYN_TEST_SD 0b001
+#define MAX2837_SYN_TEST_REF_DIV 0b010
+#define MAX2837_SYN_TEST_MAIN_DIV 0b011
+#define MAX2837_SYN_TEST_CP_LO_Z_LOCK_DETECT 0b100
+#define MAX2837_SYN_TEST_CP_SOURCE_SD 0b101
+#define MAX2837_SYN_TEST_CP_SINK_REF_DIV 0b110
+#define MAX2837_SYN_TEST_CP_HI_Z_MAIN_DIV 0b111
+
+/* REG 22 */
+__MREG__(MAX2837_VAS_EN,22,0,1) // select VCO subband by VAS, vs. reg
+__MREG__(MAX2837_VAS_RELOCK_SEL,22,1,1)
+#define MAX2837_VAS_RELOCK_SELECTED 0
+#define MAX2837_VAS_RELOCK_PRESENT 1
+__MREG__(MAX2837_VAS_DIV,22,4,3)
+#define MAX2837_VAS_CLK_DIV_8 0
+#define MAX2837_VAS_CLK_DIV_9 1
+#define MAX2837_VAS_CLK_DIV_10 2
+#define MAX2837_VAS_CLK_DIV_11 3
+#define MAX2837_VAS_CLK_DIV_12 4
+#define MAX2837_VAS_CLK_DIV_13 5
+#define MAX2837_VAS_CLK_DIV_14 6
+#define MAX2837_VAS_CLK_DIV_2 7
+__MREG__(MAX2837_VAS_DLY,22,6,2) // Delay = Txtal * VAS_DIV * VAS_DLY * 7
+#define MAX2837_VAS_DLY_16
+#define MAX2837_VAS_DLY_32
+#define MAX2837_VAS_DLY_64
+#define MAX2837_VAS_DLY_128
+__MREG__(MAX2837_VAS_TRIG_EN,22,7,1)
+__MREG__(MAX2837_VAS_ADE,22,8,1)
+__MREG__(MAX2837_VAS_ADL_SPI,22,9,1)
+
+/* REG 23 */
+__MREG__(MAX2837_VAS_SPI,23,4,5) // subband selection default is center (15)
+__MREG__(MAX2837_XTAL_BIAS,23,6,2)
+#define MAX2837_XTAL_BIAS_240_20 0 // 240uA for 20MHz
+#define MAX2837_XTAL_BIAS_420_20 1
+#define MAX2837_XTAL_BIAS_600_40 2
+#define MAX2837_XTAL_BIAS_780_40 3
+__MREG__(MAX2837_XTAL_E2C_BIAS,23,7,1)
+#define MAX2837_XTAL_E2C_BIAS_360 0 // uA
+#define MAX2837_XTAL_E2C_BIAS_540 1
+__MREG__(MAX2837_VAS_SE,23,8,1)
+#define MAX2837_VAS_SE_DIFF 0
+#define MAX2837_VAS_SE_SINGLE 1
+__MREG__(MAX2837_VCO_SPI_EN,23,9,1) // set to override mode
+
+/* REG 24 */
+__MREG__(MAX2837_XTAL_TUNE,24,6,7) // 0=max 127=min freq
+__MREG__(MAX2837_CLKOUT_PIN_EN,24,7,1)
+__MREG__(MAX2837_CLKOUT_DIV,24,8,1)
+#define MAX2837_CLKOUT_DIV_1 0
+#define MAX2837_CLKOUT_DIV_2 1
+__MREG__(MAX2837_XTAL_CORE_EN,24,9,1) // set to override mode
+
+/* REG 25 */
+__MREG__(MAX2837_VCO_BIAS_SPI_EN,25,0,1) // enable override of vco bias trim
+__MREG__(MAX2837_VCO_BIAS,25,4,4) // 0b1000 nominal
+__MREG__(MAX2837_VCO_CMEN,25,5,1) // enable Miller capacitor
+__MREG__(MAX2837_VCO_PDET_TST,25,7,2) // peak detector test output select
+#define MAX2837_VCO_PDET_TST_NORMAL 0
+#define MAX2837_VCO_PDET_TST_PDOUT 1 // peak detector output
+#define MAX2837_VCO_PDET_TST_PDREF 2 // peak detector reference
+#define MAX2837_VCO_PDET_TST_TEMP 3 // VCO temperature sensor
+__MREG__(MAX2837_VCO_BUF_BIAS,25,9,2) // VCO buffer bias
+#define MAX2837_VCO_BUF_BIAS_800uA 0
+#define MAX2837_VCO_BUF_BIAS_1200uA 1 // default
+#define MAX2837_VCO_BUF_BIAS_1600uA 2
+#define MAX2837_VCO_BUF_BIAS_2000uA 3
+
+/* REG 26 */
+__MREG__(MAX2837_LOGEN_BIAS1,26,1,2) // LOGEN emitter follower bias
+#define MAX2837_LOGEN_BIAS1_400u 0
+#define MAX2837_LOGEN_BIAS1_600u 1
+#define MAX2837_LOGEN_BIAS1_800u 2
+#define MAX2837_LOGEN_BIAS1_1000u 3
+__MREG__(MAX2837_LOGEN_BIAS2,26,2,1) // LOGEN RX/TX Gm bias
+#define MAX2837_LOGEN_BIAS2_DEFAULT 0 // default
+#define MAX2837_LOGEN_BIAS2_PLUS25 1 // +25%
+__MREG__(MAX2837_LOGEN_2GM,26,3,1) //
+__MREG__(MAX2837_LOGEN_TRIM1,26,4,1) // mixer tank trim enable
+__MREG__(MAX2837_LOGEN_TRIM2,26,5,1) // bandpass filter trim enable
+__MREG__(MAX2837_VAS_TST,26,9,4) // DOUT test signal select
+#define MAX2837_VAS_TST_VCO_BSW0 0 // VAS band select output (5 bits)
+#define MAX2837_VAS_TST_VCO_BSW1 1
+#define MAX2837_VAS_TST_VCO_BSW2 2
+#define MAX2837_VAS_TST_VCO_BSW3 3
+#define MAX2837_VAS_TST_VCO_BSW4 4
+#define MAX2837_VAS_TST_Vtune_ADC0 5 // VCO Vtune ADC output (3 bits)
+#define MAX2837_VAS_TST_Vtune_ADC1 6
+#define MAX2837_VAS_TST_Vtune_ADC2 7
+#define MAX2837_VAS_TST_VASA 8 // VAS accomplish (success)
+#define MAX2837_VAS_TST_VASE 9 // VAS end (success or gave up)
+#define MAX2837_VAS_TST_ZERO 15 // default
+
+/* REG 27 */
+__MREG__(MAX2837_PADRV_BIAS,27,2,3) // PA driver bias (0-7), default 3
+__MREG__(MAX2837_PADRV_DOWN_SPI_EN,27,3,1) // PA drv down process select enable
+__MREG__(MAX2837_PADRV_DOWN,27,4,1) // PA driver down select
+#define MAX2837_PADRV_DOWN_DOWN 0
+#define MAX2837_PADRV_DOWN_UP 1 // default
+__MREG__(MAX2837_PADAC_IV,27,5,1) // PA DAC I/V output select
+#define MAX2837_PADAC_IV_VOLTAGE 0
+#define MAX2837_PADAC_IV_CURRENT 1 // default
+__MREG__(MAX2837_PADAC_VMODE,27,6,1) // set logic 0 or 1 for PADAC_IV out
+__MREG__(MAX2837_PADAC_DIV,27,7,1) // PA DAC clock divide ratio
+#define MAX2837_PADAC_DIV_20MHz 0
+#define MAX2837_PADAC_DIV_40MHz 1
+__MREG__(MAX2837_TXGATE_EN,27,8,1) // set to relock when TXOOL=1 or LD=0
+__MREG__(MAX2837_TXDCCORR_EN,27,9,1) // TX DC offset correction enable
+
+/* REG 28 */
+__MREG__(MAX2837_PADAC_BIAS,28,5,6) // PADAC output current control, 5uA step
+__MREG__(MAX2837_PADAC_DLY,28,9,4) // PADAC turn-on delay control
+ // 0,1 are both 0us
+ // then 0.5us steps to 7.0us
+
+/* REG 29 */
+__MREG__(MAX2837_TXVGA_GAIN_SPI_EN,29,0,1) // Enable SPI control of TXVGA gain
+__MREG__(MAX2837_TXVGA_GAIN_MSB_SPI_EN,29,1,1)
+__MREG__(MAX2837_TX_DCCORR_SPI_EN,29,2,1)
+__MREG__(MAX2837_FUSE_ARM,29,3,1) // Fuse burn enable
+__MREG__(MAX2837_TXVGA_GAIN,29,5,6) // 0 = min atten, 63 = max atten
+
+/* REG 30 */
+__MREG__(MAX2837_TXLO_IQ,30,4,5)
+__MREG__(MAX2837_TXLO_IQ_SPI_EN,30,5,5)
+__MREG__(MAX2837_TXLO_BUFF_BIAS,30,7,2)
+#define MAX2837_TXLO_BUFF_BIAS_1_0mA 0
+#define MAX2837_TXLO_BUFF_BIAS_1_5mA 1
+#define MAX2837_TXLO_BUFF_BIAS_2_0mA 2 // default
+#define MAX2837_TXLO_BUFF_BIAS_2_5mA 3
+__MREG__(MAX2837_FUSE_GKT,30,8,1)
+__MREG__(MAX2837_FUSE_RTH,30,9,1)
+
+/* REG 31 */
+// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_SPI_EN
+__MREG__(MAX2837_TX_DCCORR_I,31,4,5)
+__MREG__(MAX2837_TX_DCCORR_Q,31,9,5)
+
+#endif // __MAX2837_REGS_DEF
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2  test_max2837/ols_LPC43xx_SSP1_simpletx_capture.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html><head><title></title><meta http-equiv='Content-type' content='text/html;charset=UTF-8'><style type='text/css'>body { font-family: sans-serif; } table { border-width: 1px; border-spacing: 0px; border-color: gray; border-collapse: collapse; border-style: solid; margin-bottom: 15px; } table th { border-width: 1px; padding: 2px; border-style: solid; border-color: gray; background-color: #C0C0FF; text-align: left; font-weight: bold; font-family: sans-serif; } table td { border-width: 1px; padding: 2px; border-style: solid; border-color: gray; font-family: monospace; } .date { text-align: right; font-size: x-small; margin-bottom: 15px; } .w100 { width: 100%; } .w35 { width: 35%; } .w30 { width: 30%; } .w15 { width: 15%; } .w10 { width: 10%; } .w8 { width: 8%; } .w7 { width: 7%; } </style></head><body><h1>SPI Analysis results</h1><hr><div class='date'>Generated: 12 juin 2012</div><table class='w100'><tbody><tr><th colspan='2'>Configuration</th></tr><tr><td class='w30'>SPI mode</td><td>Mode 0 (CPOL = 0, CPHA = 0)</td></tr></tbody></table><table class='w100'><thead><tr><th class='w30' colspan='2'></th><th class='w35' colspan='4'>MOSI</th><th class='w35' colspan='4'>MISO</th></tr><tr><th class='w15'>Index</th><th class='w15'>Time</th><th class='w10'>Hex</th><th class='w10'>Bin</th><th class='w8'>Dec</th><th class='w7'>ASCII</th><th class='w10'>Hex</th><th class='w10'>Bin</th><th class='w8'>Dec</th><th class='w7'>ASCII</th></tr></thead><tbody><tr style='background-color: #c0ffc0;'><td>0</td><td>2,878 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>1</td><td>2,899 ms</td><td>0x0150</td><td>0b0000000101010000</td><td>336</td><td></td><td>0xcffb</td><td>0b1100111111111011</td><td>53243</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>3</td><td>3,230 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>4</td><td>3,240 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>5</td><td>3,261 ms</td><td>0x0402</td><td>0b0000010000000010</td><td>1026</td><td></td><td>0xfdff</td><td>0b1111110111111111</td><td>65023</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>7</td><td>3,592 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>8</td><td>3,602 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>9</td><td>3,623 ms</td><td>0x09f4</td><td>0b0000100111110100</td><td>2548</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>11</td><td>3,954 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>12</td><td>3,965 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>13</td><td>3,985 ms</td><td>0x0db9</td><td>0b0000110110111001</td><td>3513</td><td></td><td>0x9fff</td><td>0b1001111111111111</td><td>40959</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>15</td><td>4,317 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>16</td><td>4,327 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>17</td><td>4,348 ms</td><td>0x100a</td><td>0b0001000000001010</td><td>4106</td><td></td><td>0xfbfe</td><td>0b1111101111111110</td><td>64510</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>19</td><td>4,679 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>20</td><td>4,689 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>21</td><td>4,710 ms</td><td>0x1480</td><td>0b0001010010000000</td><td>5248</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>23</td><td>5,041 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>24</td><td>5,051 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>25</td><td>5,072 ms</td><td>0x1806</td><td>0b0001100000000110</td><td>6150</td><td></td><td>0x3fef</td><td>0b0011111111101111</td><td>16367</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>27</td><td>5,403 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>28</td><td>5,414 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>29</td><td>5,434 ms</td><td>0x1c00</td><td>0b0001110000000000</td><td>7168</td><td></td><td>0xfffd</td><td>0b1111111111111101</td><td>65533</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>31</td><td>5,766 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>32</td><td>5,776 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>33</td><td>5,797 ms</td><td>0x2080</td><td>0b0010000010000000</td><td>8320</td><td></td><td>0xfeff</td><td>0b1111111011111111</td><td>65279</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>35</td><td>6,128 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>36</td><td>6,138 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>37</td><td>6,159 ms</td><td>0x2418</td><td>0b0010010000011000</td><td>9240</td><td></td><td>0x7fdf</td><td>0b0111111111011111</td><td>32735</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>39</td><td>6,490 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>40</td><td>6,501 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>41</td><td>6,521 ms</td><td>0x2858</td><td>0b0010100001011000</td><td>10328</td><td></td><td>0xeffb</td><td>0b1110111111111011</td><td>61435</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>43</td><td>6,852 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>44</td><td>6,863 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>45</td><td>6,884 ms</td><td>0x2c16</td><td>0b0010110000010110</td><td>11286</td><td></td><td>0xfdff</td><td>0b1111110111111111</td><td>65023</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>47</td><td>7,215 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>48</td><td>7,225 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>49</td><td>7,246 ms</td><td>0x324f</td><td>0b0011001001001111</td><td>12879</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>51</td><td>7,577 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>52</td><td>7,587 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>53</td><td>7,608 ms</td><td>0x3550</td><td>0b0011010101010000</td><td>13648</td><td></td><td>0xfff7</td><td>0b1111111111110111</td><td>65527</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>55</td><td>7,939 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>56</td><td>7,950 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>57</td><td>7,970 ms</td><td>0x39c5</td><td>0b0011100111000101</td><td>14789</td><td></td><td>0xfbff</td><td>0b1111101111111111</td><td>64511</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>59</td><td>8,302 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>60</td><td>8,312 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>61</td><td>8,333 ms</td><td>0x3c81</td><td>0b0011110010000001</td><td>15489</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>63</td><td>8,664 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>64</td><td>8,674 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>65</td><td>8,695 ms</td><td>0x401c</td><td>0b0100000000011100</td><td>16412</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>67</td><td>9,026 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>68</td><td>9,036 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>69</td><td>9,057 ms</td><td>0x4555</td><td>0b0100010101010101</td><td>17749</td><td></td><td>0xf7fd</td><td>0b1111011111111101</td><td>63485</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>71</td><td>9,388 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>72</td><td>9,399 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>73</td><td>9,419 ms</td><td>0x4955</td><td>0b0100100101010101</td><td>18773</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>75</td><td>9,751 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>76</td><td>9,761 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>77</td><td>9,782 ms</td><td>0x4d53</td><td>0b0100110101010011</td><td>19795</td><td></td><td>0x7fdf</td><td>0b0111111111011111</td><td>32735</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>79</td><td>10,113 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>80</td><td>10,123 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>81</td><td>10,144 ms</td><td>0x5241</td><td>0b0101001001000001</td><td>21057</td><td></td><td>0xfff9</td><td>0b1111111111111001</td><td>65529</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>83</td><td>10,475 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>84</td><td>10,485 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>85</td><td>10,506 ms</td><td>0x542c</td><td>0b0101010000101100</td><td>21548</td><td></td><td>0xfdff</td><td>0b1111110111111111</td><td>65023</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>87</td><td>10,837 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>88</td><td>10,848 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>89</td><td>10,868 ms</td><td>0x59a9</td><td>0b0101100110101001</td><td>22953</td><td></td><td>0xffbf</td><td>0b1111111110111111</td><td>65471</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>91</td><td>11,200 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>92</td><td>11,210 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>93</td><td>11,231 ms</td><td>0x5e4f</td><td>0b0101111001001111</td><td>24143</td><td></td><td>0xdfff</td><td>0b1101111111111111</td><td>57343</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>95</td><td>11,562 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>96</td><td>11,572 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>97</td><td>11,593 ms</td><td>0x6180</td><td>0b0110000110000000</td><td>24960</td><td></td><td>0xf9fe</td><td>0b1111100111111110</td><td>63998</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>99</td><td>11,924 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>100</td><td>11,935 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>101</td><td>11,955 ms</td><td>0x6500</td><td>0b0110010100000000</td><td>25856</td><td></td><td>0xff3f</td><td>0b1111111100111111</td><td>65343</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>103</td><td>12,286 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>104</td><td>12,297 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>105</td><td>12,318 ms</td><td>0x6bca</td><td>0b0110101111001010</td><td>27594</td><td></td><td>0xffef</td><td>0b1111111111101111</td><td>65519</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>107</td><td>12,649 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>108</td><td>12,659 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>109</td><td>12,680 ms</td><td>0x6fe3</td><td>0b0110111111100011</td><td>28643</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>111</td><td>13,011 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>112</td><td>13,021 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>113</td><td>13,042 ms</td><td>0x70c0</td><td>0b0111000011000000</td><td>28864</td><td></td><td>0xfeff</td><td>0b1111111011111111</td><td>65279</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>115</td><td>13,373 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>116</td><td>13,384 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>117</td><td>13,404 ms</td><td>0x77f0</td><td>0b0111011111110000</td><td>30704</td><td></td><td>0x7fff</td><td>0b0111111111111111</td><td>32767</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>119</td><td>13,736 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>120</td><td>13,746 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>121</td><td>13,767 ms</td><td>0x7880</td><td>0b0111100010000000</td><td>30848</td><td></td><td>0xfff9</td><td>0b1111111111111001</td><td>65529</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>123</td><td>14,098 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>124</td><td>14,108 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>125</td><td>14,129 ms</td><td>0x7c00</td><td>0b0111110000000000</td><td>31744</td><td></td><td>0xfcff</td><td>0b1111110011111111</td><td>64767</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>127</td><td>14,460 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>128</td><td>14,470 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>129</td><td>14,491 ms</td><td>0x0402</td><td>0b0000010000000010</td><td>1026</td><td></td><td>0x7f9f</td><td>0b0111111110011111</td><td>32671</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>131</td><td>14,822 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>132</td><td>14,833 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>133</td><td>14,853 ms</td><td>0x1480</td><td>0b0001010010000000</td><td>5248</td><td></td><td>0x9ff3</td><td>0b1001111111110011</td><td>40947</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>135</td><td>15,185 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>136</td><td>15,195 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>137</td><td>15,216 ms</td><td>0x2081</td><td>0b0010000010000001</td><td>8321</td><td></td><td>0xf9ff</td><td>0b1111100111111111</td><td>63999</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>139</td><td>15,547 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>140</td><td>15,557 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>141</td><td>15,578 ms</td><td>0x77ff</td><td>0b0111011111111111</td><td>30719</td><td></td><td>0xffff</td><td>0b1111111111111111</td><td>65535</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>143</td><td>15,909 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>144</td><td>15,919 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>145</td><td>15,940 ms</td><td>0x0150</td><td>0b0000000101010000</td><td>336</td><td></td><td>0x1ff7</td><td>0b0001111111110111</td><td>8183</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>147</td><td>16,271 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>148</td><td>16,282 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>149</td><td>16,302 ms</td><td>0x4977</td><td>0b0100100101110111</td><td>18807</td><td></td><td>0xfbff</td><td>0b1111101111111111</td><td>64511</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>151</td><td>16,634 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>152</td><td>16,644 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>153</td><td>16,665 ms</td><td>0x4d51</td><td>0b0100110101010001</td><td>19793</td><td></td><td>0xff7f</td><td>0b1111111101111111</td><td>65407</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>155</td><td>16,996 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>156</td><td>17,006 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>157</td><td>17,027 ms</td><td>0x45de</td><td>0b0100010111011110</td><td>17886</td><td></td><td>0x7fdf</td><td>0b0111111111011111</td><td>32735</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>159</td><td>17,358 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr><tr style='background-color: #c0ffc0;'><td>160</td><td>17,369 ms</td><td>CS_LOW</td><td></td><td></td><td></td><td>CS_LOW</td><td></td><td></td><td></td></tr><tr><td>161</td><td>17,389 ms</td><td>0x401d</td><td>0b0100000000011101</td><td>16413</td><td></td><td>0xe7fd</td><td>0b1110011111111101</td><td>59389</td><td></td></tr><tr style='background-color: #e0e0e0;'><td>163</td><td>17,720 ms</td><td>CS_HIGH</td><td></td><td></td><td></td><td>CS_HIGH</td><td></td><td></td><td></td></tr></tbody></table></body></html>
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7,292 test_max2837/ols_LPC43xx_SSP1_simpletx_capture.ols
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