From 9e994b1b24ac5bd66b1ed6be2c5000aa0765caeb Mon Sep 17 00:00:00 2001 From: cainm Date: Sat, 12 Nov 2011 09:17:57 -0500 Subject: [PATCH] Added CONFIG_TEGRA_OVERCLOCK --- arch/arm/Kconfig | 7 ++++ arch/arm/mach-tegra/tegra2_clocks.c | 50 +++++++++++++++++++++++++++-- arch/arm/mach-tegra/tegra2_dvfs.c | 30 +++++++++++++++-- 3 files changed, 82 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cd2c427f..b79890ad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1709,6 +1709,13 @@ config CPU_FREQ_S3C24XX_DEBUGFS depends on CPU_FREQ_S3C24XX && DEBUG_FS help Export status information via debugfs. + +config TEGRA_OVERCLOCK + bool "TEGRA_OVERCLOCK - Overclocking" + depends on CPU_FREQ + default n + help + This enables overclocking to 1.4GHZ. endif diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 1461d350..ae87e0ca 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -1693,6 +1693,13 @@ static struct clk tegra_pll_u = { }; static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { +#if defined(CONFIG_TEGRA_OVERCLOCK) + /* 1.4 GHz */ + { 12000000, 1400000000, 700, 6, 1, 12}, + { 13000000, 1400000000, 969, 9, 1, 12}, + { 19200000, 1400000000, 875, 12, 1, 8}, + { 26000000, 1400000000, 700, 13, 1, 12}, +#endif /* 1.2 GHz */ { 12000000, 1200000000, 600, 6, 1, 12}, { 13000000, 1200000000, 923, 10, 1, 12}, @@ -1756,7 +1763,11 @@ static struct clk tegra_pll_x = { .ops = &tegra_pll_ops, .reg = 0xe0, .parent = &tegra_clk_m, +#if defined(CONFIG_TEGRA_OVERCLOCK) + .max_rate = 1400000000, +#else .max_rate = 1000000000, +#endif .u.pll = { .input_min = 2000000, .input_max = 31000000, @@ -1883,7 +1894,11 @@ static struct clk tegra_clk_cclk = { .inputs = mux_cclk, .reg = 0x20, .ops = &tegra_super_ops, +#if defined(CONFIG_TEGRA_OVERCLOCK) + .max_rate = 1400000000, +#else .max_rate = 1000000000, +#endif }; static struct clk tegra_clk_sclk = { @@ -1899,7 +1914,11 @@ static struct clk tegra_clk_virtual_cpu = { .name = "cpu", .parent = &tegra_clk_cclk, .ops = &tegra_cpu_ops, +#if defined(CONFIG_TEGRA_OVERCLOCK) + .max_rate = 1400000000, +#else .max_rate = 1000000000, +#endif .u.cpu = { .main = &tegra_pll_x, .backup = &tegra_pll_p, @@ -2292,9 +2311,15 @@ static struct tegra_sku_rate_limit sku_limits[] = RATE_LIMIT("cclk", 750000000, 0x07, 0x10), RATE_LIMIT("pll_x", 750000000, 0x07, 0x10), - RATE_LIMIT("cpu", 1000000000, 0x04, 0x08, 0x0F), - RATE_LIMIT("cclk", 1000000000, 0x04, 0x08, 0x0F), - RATE_LIMIT("pll_x", 1000000000, 0x04, 0x08, 0x0F), +#if defined(CONFIG_TEGRA_OVERCLOCK) + RATE_LIMIT("cpu", 1400000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("cclk", 1400000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("pll_x", 1400000000, 0x04, 0x08, 0x0F), +#else + RATE_LIMIT("cpu", 1000000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("cclk", 1000000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("pll_x", 1000000000, 0x04, 0x08, 0x0F), +#endif RATE_LIMIT("cpu", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("cclk", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), @@ -2424,10 +2449,29 @@ static struct cpufreq_frequency_table freq_table_1p2GHz[] = { { 9, CPUFREQ_TABLE_END }, }; +#if defined(CONFIG_TEGRA_OVERCLOCK) +static struct cpufreq_frequency_table freq_table_1p4GHz[] = { + { 0, 216000 }, + { 1, 312000 }, + { 2, 456000 }, + { 3, 608000 }, + { 4, 760000 }, + { 5, 816000 }, + { 6, 912000 }, + { 7, 1000000 }, + { 8, 1200000 }, + { 9, 1400000 }, + { 10, CPUFREQ_TABLE_END }, +}; +#endif + static struct tegra_cpufreq_table_data cpufreq_tables[] = { { freq_table_750MHz, 1, 4 }, { freq_table_1p0GHz, 2, 6 }, { freq_table_1p2GHz, 2, 7 }, +#if defined(CONFIG_TEGRA_OVERCLOCK) + { freq_table_1p4GHz, 2, 6 }, +#endif }; struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c index 0984b6d4..ef64943a 100644 --- a/arch/arm/mach-tegra/tegra2_dvfs.c +++ b/arch/arm/mach-tegra/tegra2_dvfs.c @@ -40,24 +40,43 @@ static bool tegra_dvfs_cpu_disabled = true; static const int core_millivolts[MAX_DVFS_FREQS] = {950, 1000, 1100, 1200, 1225, 1275, 1300}; static const int cpu_millivolts[MAX_DVFS_FREQS] = - {750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1100, 1125}; +#if defined(CONFIG_TEGRA_OVERCLOCK) + {750, 775, 800, 825, 850, 875, 950, 975, 975, 1025, 1075, 1125, 1175, 1200, 1225}; +#else + {750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1100, 1125}; +#endif + static const int cpu_speedo_nominal_millivolts[] = /* spedo_id 0, 1, 2 */ +#if defined(CONFIG_TEGRA_OVERCLOCK) + { 1100, 1175, 1125 }; +#else { 1100, 1025, 1125 }; +#endif static const int core_speedo_nominal_millivolts[] = /* spedo_id 0, 1, 2 */ +#if defined(CONFIG_TEGRA_OVERCLOCK) + { 1225, 1275, 1300 }; +#else { 1225, 1225, 1300 }; +#endif #define KHZ 1000 #define MHZ 1000000 static struct dvfs_rail tegra2_dvfs_rail_vdd_cpu = { .reg_id = "vdd_cpu", +#if defined(CONFIG_TEGRA_OVERCLOCK) + .max_millivolts = 1225, + .min_millivolts = 750, + .nominal_millivolts = 1225, +#else .max_millivolts = 1125, .min_millivolts = 750, .nominal_millivolts = 1125, +#endif }; static struct dvfs_rail tegra2_dvfs_rail_vdd_core = { @@ -158,11 +177,18 @@ static struct dvfs dvfs_init[] = { CPU_DVFS("cpu", 0, 1, MHZ, 314, 314, 314, 456, 456, 456, 618, 618, 618, 770, 827, 827, 922, 1000), CPU_DVFS("cpu", 0, 2, MHZ, 494, 494, 494, 675, 675, 817, 817, 922, 922, 1000), CPU_DVFS("cpu", 0, 3, MHZ, 730, 760, 845, 845, 940, 1000), - +#if defined(CONFIG_TEGRA_OVERCLOCK) + /* Cpu voltages (mV): 750, 775, 800, 825, 850, 875, 950, 975, 975, 1025, 1075, 1125, 1175, 1200, 1225 */ + CPU_DVFS("cpu", 1, 0, MHZ, 380, 380, 503, 503, 655, 655, 798, 798, 902, 902, 960, 1000, 1200, 1400), + CPU_DVFS("cpu", 1, 1, MHZ, 389, 389, 503, 503, 655, 760, 798, 798, 950, 950, 1000, 1200, 1400), + CPU_DVFS("cpu", 1, 2, MHZ, 598, 598, 750, 750, 893, 893, 1000, 1200, 1400), + CPU_DVFS("cpu", 1, 3, MHZ, 730, 760, 845, 845, 940, 1000, 1200, 1400), +#else CPU_DVFS("cpu", 1, 0, MHZ, 380, 380, 503, 503, 655, 655, 798, 798, 902, 902, 960, 1000), CPU_DVFS("cpu", 1, 1, MHZ, 389, 389, 503, 503, 655, 760, 798, 798, 950, 950, 1000), CPU_DVFS("cpu", 1, 2, MHZ, 598, 598, 750, 750, 893, 893, 1000), CPU_DVFS("cpu", 1, 3, MHZ, 730, 760, 845, 845, 940, 1000), +#endif CPU_DVFS("cpu", 2, 0, MHZ, 0, 0, 0, 0, 655, 655, 798, 798, 902, 902, 960, 1000, 1100, 1100, 1200), CPU_DVFS("cpu", 2, 1, MHZ, 0, 0, 0, 0, 655, 760, 798, 798, 950, 950, 1015, 1015, 1100, 1200),