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ARM: tegra: clock: Auto-detect PLLP rate in kernel uncompress

Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, and debug uart
configuration during kernel uncompressing.
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commit 57aa55822d00bd326bbc1669fd09a669d4986307 1 parent a67780a
authored April 12, 2012 motley-git committed April 12, 2012
48  arch/arm/mach-tegra/include/mach/uncompress.h
@@ -7,7 +7,7 @@
7 7
  *	Colin Cross <ccross@google.com>
8 8
  *	Erik Gilling <konkers@google.com>
9 9
  *
10  
- * Copyright (C) 2010-2011 NVIDIA Corporation
  10
+ * Copyright (C) 2010-2012 NVIDIA Corporation
11 11
  *
12 12
  * This software is licensed under the terms of the GNU General Public
13 13
  * License version 2, as published by the Free Software Foundation, and
@@ -65,12 +65,16 @@
65 65
 #define DEBUG_UART_RST_CLR_REG		0
66 66
 #define DEBUG_UART_RST_CLR_BIT		0
67 67
 #endif
  68
+#define PLLP_BASE			(TEGRA_CLK_RESET_BASE + 0x0a0)
  69
+#define PLLP_BASE_OVERRIDE		(1 << 28)
  70
+#define PLLP_BASE_DIVP_SHIFT		20
  71
+#define PLLP_BASE_DIVP_MASK		(0x7 << 20)
  72
+#define PLLP_BASE_DIVN_SHIFT		8
  73
+#define PLLP_BASE_DIVN_MASK		(0x3FF << 8)
68 74
 
69  
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
70  
-#define DEBUG_UART_DLL			0x75
71  
-#else
72  
-#define DEBUG_UART_DLL			0xdd
73  
-#endif
  75
+#define DEBUG_UART_DLL_216		0x75
  76
+#define DEBUG_UART_DLL_408		0xdd
  77
+#define DEBUG_UART_DLL_204		0x6f
74 78
 
75 79
 static void putc(int c)
76 80
 {
@@ -104,6 +108,8 @@ static inline void arch_decomp_setup(void)
104 108
 	volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
105 109
 	int shift = 2;
106 110
 	volatile u32 *addr;
  111
+	u8 uart_dll = DEBUG_UART_DLL_216;
  112
+	u32 val;
107 113
 
108 114
 	if (uart == NULL)
109 115
 		return;
@@ -124,9 +130,37 @@ static inline void arch_decomp_setup(void)
124 130
 
125 131
 	konk_delay(5);
126 132
 
  133
+	/*
  134
+	 * On Tegra2 platforms PLLP always run at 216MHz
  135
+	 * On Tegra3 platforms PLLP can run at 216MHz, 204MHz, or 408MHz
  136
+	 * Discrimantion algorithm below assumes that PLLP is configured
  137
+	 * according to h/w recomendations with update rate 1MHz or 1.2MHz
  138
+	 * depending on oscillator frequency
  139
+	 */
  140
+	addr = (volatile u32 *)PLLP_BASE;
  141
+	val = *addr;
  142
+	if (val & PLLP_BASE_OVERRIDE) {
  143
+		u32 p = (val & PLLP_BASE_DIVP_MASK) >> PLLP_BASE_DIVP_SHIFT;
  144
+		val = (val & PLLP_BASE_DIVN_MASK) >> (PLLP_BASE_DIVN_SHIFT + p);
  145
+		switch (val) {
  146
+		case 170:
  147
+		case 204:
  148
+			uart_dll = DEBUG_UART_DLL_204;
  149
+			break;
  150
+		case 340:
  151
+		case 408:
  152
+			uart_dll = DEBUG_UART_DLL_408;
  153
+			break;
  154
+		case 180:
  155
+		case 216:
  156
+		default:
  157
+			break;
  158
+		}
  159
+	}
  160
+
127 161
 	/* Set up debug UART. */
128 162
 	uart[UART_LCR << shift] |= UART_LCR_DLAB;
129  
-	uart[UART_DLL << shift] = DEBUG_UART_DLL;
  163
+	uart[UART_DLL << shift] = uart_dll;
130 164
 	uart[UART_DLM << shift] = 0x0;
131 165
 	uart[UART_LCR << shift] = 3;
132 166
 }

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