mrLSD · mrLSD · Sep 23, 2023 · Sep 23, 2023 · Sep 23, 2023
diff --git a/README.md b/README.md
@@ -1,10 +1,31 @@
-# FPGA
-FPGA samples. Most of them base on Verilog or SystemVerilog.
-Implemented for Altera Development Board with Quartus CAD.
+# FPGA Research & Development
 
-## Projects
+## Supported boards
+
+- Altera devboard Cyclone IV E - `EP4CE10E22C8`
+- Sipeed TangNano 9k
+
+## Sipeed TangNano 9k
+
+- Usefull getting started guides:
+    - Sipeed [website]()
+    - [Lushat Labs articles](https://learn.lushaylabs.com/getting-setup-with-the-tang-nano-9k/#creating-a-new-project)
+- github examples:
+    - https://github.com/lushaylabs/tangnano9k-series-examples
+    - https://github.com/sipeed/TangNano-9K-example
+- required: [OSS Cad Suite](https://github.com/YosysHQ/oss-cad-suite-build) or just install [Gowin EDA](https://www.gowinsemi.com/en/support/download_eda/).
+
+### Altera Devboard
+
+- Devboard: `Cyclone IV E EP4CE10E22C8`
+- Quartus CAD required
+FPGA project mostly base on Verilog or SystemVerilog. And implemented for Altera DevelopmentBoard with Quartus CAD.
+
+#### Altera based projects
+
+* **VGA** - output via VGA interfact to motinors. Can draw multy line text with specific fonts.
 * **led4_highreg** - 12 LED circle sequence
-* **timer** - count down timer with ability set timer time. 
+* **timer** - onboard digital LED count down timer with ability set timer time. 
 Digital LED and Keys used for I/O.
 
 ### LICENSE MIT
diff --git a/led4_highreg/Makefile → altera-cyclone-IV/led4_highreg/Makefile b/led4_highreg/Makefile → altera-cyclone-IV/led4_highreg/Makefile
diff --git a/led4_highreg/README.md → altera-cyclone-IV/led4_highreg/README.md b/led4_highreg/README.md → altera-cyclone-IV/led4_highreg/README.md
diff --git a/led4_highreg/led4_reg.qpf → altera-cyclone-IV/led4_highreg/led4_reg.qpf b/led4_highreg/led4_reg.qpf → altera-cyclone-IV/led4_highreg/led4_reg.qpf
diff --git a/led4_highreg/led4_reg.qsf → altera-cyclone-IV/led4_highreg/led4_reg.qsf b/led4_highreg/led4_reg.qsf → altera-cyclone-IV/led4_highreg/led4_reg.qsf
diff --git a/led4_highreg/led4_reg.v → altera-cyclone-IV/led4_highreg/led4_reg.v b/led4_highreg/led4_reg.v → altera-cyclone-IV/led4_highreg/led4_reg.v
diff --git a/led4_highreg/led4_reg_test → altera-cyclone-IV/led4_highreg/led4_reg_test b/led4_highreg/led4_reg_test → altera-cyclone-IV/led4_highreg/led4_reg_test
diff --git a/led4_highreg/led4_reg_test.v → ...a-cyclone-IV/led4_highreg/led4_reg_test.v b/led4_highreg/led4_reg_test.v → ...a-cyclone-IV/led4_highreg/led4_reg_test.v
diff --git a/timer/Makefile → altera-cyclone-IV/timer/Makefile b/timer/Makefile → altera-cyclone-IV/timer/Makefile
diff --git a/timer/README.md → altera-cyclone-IV/timer/README.md b/timer/README.md → altera-cyclone-IV/timer/README.md
diff --git a/timer/const.sv → altera-cyclone-IV/timer/const.sv b/timer/const.sv → altera-cyclone-IV/timer/const.sv
diff --git a/timer/libs/keys.sv → altera-cyclone-IV/timer/libs/keys.sv b/timer/libs/keys.sv → altera-cyclone-IV/timer/libs/keys.sv
diff --git a/timer/libs/tools.sv → altera-cyclone-IV/timer/libs/tools.sv b/timer/libs/tools.sv → altera-cyclone-IV/timer/libs/tools.sv
diff --git a/timer/timer.qpf → altera-cyclone-IV/timer/timer.qpf b/timer/timer.qpf → altera-cyclone-IV/timer/timer.qpf
diff --git a/timer/timer.qsf → altera-cyclone-IV/timer/timer.qsf b/timer/timer.qsf → altera-cyclone-IV/timer/timer.qsf
diff --git a/timer/timer.sv → altera-cyclone-IV/timer/timer.sv b/timer/timer.sv → altera-cyclone-IV/timer/timer.sv
diff --git a/timer/timer_test → altera-cyclone-IV/timer/timer_test b/timer/timer_test → altera-cyclone-IV/timer/timer_test
diff --git a/timer/timer_test.sv → altera-cyclone-IV/timer/timer_test.sv b/timer/timer_test.sv → altera-cyclone-IV/timer/timer_test.sv
diff --git a/vga/Font_Rom.vhd → altera-cyclone-IV/vga/Font_Rom.vhd b/vga/Font_Rom.vhd → altera-cyclone-IV/vga/Font_Rom.vhd
diff --git a/vga/Makefile → altera-cyclone-IV/vga/Makefile b/vga/Makefile → altera-cyclone-IV/vga/Makefile
diff --git a/vga/Pixel_On_Text.vhd → altera-cyclone-IV/vga/Pixel_On_Text.vhd b/vga/Pixel_On_Text.vhd → altera-cyclone-IV/vga/Pixel_On_Text.vhd
diff --git a/vga/Pixel_On_Text2.vhd → altera-cyclone-IV/vga/Pixel_On_Text2.vhd b/vga/Pixel_On_Text2.vhd → altera-cyclone-IV/vga/Pixel_On_Text2.vhd
diff --git a/vga/vga.qpf → altera-cyclone-IV/vga/VGA.qpf b/vga/vga.qpf → altera-cyclone-IV/vga/VGA.qpf
diff --git a/vga/commonPak.vhd → altera-cyclone-IV/vga/commonPak.vhd b/vga/commonPak.vhd → altera-cyclone-IV/vga/commonPak.vhd
diff --git a/vga/font.inc → altera-cyclone-IV/vga/font.inc b/vga/font.inc → altera-cyclone-IV/vga/font.inc
diff --git a/vga/text/fonts.sv → altera-cyclone-IV/vga/text/fonts.sv b/vga/text/fonts.sv → altera-cyclone-IV/vga/text/fonts.sv
diff --git a/vga/text/text.sv → altera-cyclone-IV/vga/text/text.sv b/vga/text/text.sv → altera-cyclone-IV/vga/text/text.sv
diff --git a/vga/timer.qpf → altera-cyclone-IV/vga/timer.qpf b/vga/timer.qpf → altera-cyclone-IV/vga/timer.qpf
diff --git a/vga/vga.qsf → altera-cyclone-IV/vga/vga.qsf b/vga/vga.qsf → altera-cyclone-IV/vga/vga.qsf
diff --git a/vga/vga.sv → altera-cyclone-IV/vga/vga.sv b/vga/vga.sv → altera-cyclone-IV/vga/vga.sv
diff --git a/vga/wrapper.vhd → altera-cyclone-IV/vga/wrapper.vhd b/vga/wrapper.vhd → altera-cyclone-IV/vga/wrapper.vhd
diff --git a/sipeed-tangnano-9k/lcd_screen/.DS_Store b/sipeed-tangnano-9k/lcd_screen/.DS_Store
diff --git a/sipeed-tangnano-9k/lcd_screen/Makefile b/sipeed-tangnano-9k/lcd_screen/Makefile
@@ -0,0 +1,36 @@
+BOARD=tangnano9k
+FAMILY=GW1N-9C
+DEVICE=GW1NR-LV9QN88PC6/I5
+
+all: app.fs
+
+# Synthesis
+app.json: top.v lcd.v gowin_rpll/gowin_rpll.v
+	yosys -p "read_verilog lcd.v top.v gowin_rpll/gowin_rpll.v; synth_gowin -top top -json app.json"
+
+# Place and Route
+app_pnr.json: app.json
+	nextpnr-gowin --json app.json --write app_pnr.json --freq 27 --device ${DEVICE} --family ${FAMILY} --cst ${BOARD}.cst
+
+# Generate Bitstream
+app.fs: app_pnr.json
+	gowin_pack -d ${FAMILY} -o app.fs app_pnr.json
+
+# Program Board
+load: app.fs
+	openFPGALoader -b ${BOARD} app.fs -f
+
+# Generate Simulation
+screen_test.o: app.v app_tb.v
+	iverilog -o app_test.o -s test app.v app_tb.v
+
+# Run Simulation
+test: app_test.o
+	vvp app_test.o
+
+# Cleanup build artifacts
+clean:
+	rm app.vcd app.fs app_test.o
+
+.PHONY: load clean test
+.INTERMEDIATE: app_pnr.json app.json app_test.o
diff --git a/sipeed-tangnano-9k/lcd_screen/app.fs b/sipeed-tangnano-9k/lcd_screen/app.fs