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S-DD1 support by Magno

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mrehkopf committed Feb 28, 2019
1 parent 4379f0e commit 077692350c539c500236e8b23af0fc900e9be839
Showing with 12,334 additions and 6 deletions.
  1. +1 −0 src/fpga.h
  2. +5 −6 src/smc.c
  3. +84 −0 verilog/sd2snes_sdd1/DCM_Scope.v
  4. +166 −0 verilog/sd2snes_sdd1/FIFO_AXIS.vhd
  5. +125 −0 verilog/sd2snes_sdd1/FIFO_B2B.vhd
  6. +60 −0 verilog/sd2snes_sdd1/Golomb_0_Decoder.vhd
  7. +124 −0 verilog/sd2snes_sdd1/Golomb_N_Decoder.vhd
  8. +510 −0 verilog/sd2snes_sdd1/Input_Manager.vhd
  9. +5 −0 verilog/sd2snes_sdd1/Makefile
  10. +953 −0 verilog/sd2snes_sdd1/Output_Manager.vhd
  11. +348 −0 verilog/sd2snes_sdd1/Probability_Estimator.vhd
  12. +794 −0 verilog/sd2snes_sdd1/SDD1.vhd
  13. +204 −0 verilog/sd2snes_sdd1/SDD1_Core.vhd
  14. +237 −0 verilog/sd2snes_sdd1/Serializer.vhd
  15. +1,618 −0 verilog/sd2snes_sdd1/Test_Main.vhd
  16. +1,533 −0 verilog/sd2snes_sdd1/Test_Top_SDD1.vhd
  17. +233 −0 verilog/sd2snes_sdd1/address.v
  18. +382 −0 verilog/sd2snes_sdd1/cheat.v
  19. +52 −0 verilog/sd2snes_sdd1/clk_test.v
  20. +275 −0 verilog/sd2snes_sdd1/dac.v
  21. +3 −0 verilog/sd2snes_sdd1/ipcore_dir/DCM_Scope.xaw
  22. +184 −0 verilog/sd2snes_sdd1/ipcore_dir/dac_buf.v
  23. +108 −0 verilog/sd2snes_sdd1/ipcore_dir/dac_buf.xco
  24. +388 −0 verilog/sd2snes_sdd1/ipcore_dir/dac_buf.xise
  25. +184 −0 verilog/sd2snes_sdd1/ipcore_dir/msu_databuf.v
  26. +108 −0 verilog/sd2snes_sdd1/ipcore_dir/msu_databuf.xco
  27. +388 −0 verilog/sd2snes_sdd1/ipcore_dir/msu_databuf.xise
  28. +190 −0 verilog/sd2snes_sdd1/ipcore_dir/snescmd_buf.v
  29. +108 −0 verilog/sd2snes_sdd1/ipcore_dir/snescmd_buf.xco
  30. +74 −0 verilog/sd2snes_sdd1/ipcore_dir/snescmd_buf.xise
  31. +637 −0 verilog/sd2snes_sdd1/main.ucf
  32. +826 −0 verilog/sd2snes_sdd1/main.v
  33. +471 −0 verilog/sd2snes_sdd1/mcu_cmd.v
  34. +193 −0 verilog/sd2snes_sdd1/msu.v
  35. +481 −0 verilog/sd2snes_sdd1/sd2snes.xise
  36. +155 −0 verilog/sd2snes_sdd1/sd_dma.v
  37. +127 −0 verilog/sd2snes_sdd1/spi.v
@@ -48,6 +48,7 @@ const uint8_t *fpga_config;
#define FPGA_OBC1 ((const uint8_t*)"/sd2snes/fpga_obc1." FPGA_CONF_EXT)
#define FPGA_GSU ((const uint8_t*)"/sd2snes/fpga_gsu." FPGA_CONF_EXT)
#define FPGA_SA1 ((const uint8_t*)"/sd2snes/fpga_sa1." FPGA_CONF_EXT)
#define FPGA_SDD1 ((const uint8_t*)"/sd2snes/fpga_sdd1." FPGA_CONF_EXT)
#define FPGA_BASE ((const uint8_t*)"/sd2snes/fpga_base." FPGA_CONF_EXT)
#define FPGA_ROM ((const uint8_t*)"rom")

@@ -72,6 +72,7 @@ void smc_id(snes_romprops_t* props) {
props->has_obc1 = 0;
props->has_gsu = 0;
props->has_sa1 = 0;
props->has_sdd1 = 0;
props->srambase = 0;
props->sramsize_bytes = 0;
props->fpga_features = 0;
@@ -215,11 +216,11 @@ void smc_id(snes_romprops_t* props) {
}
/* S-DD1 */
else if(header->carttype == 0x43 || header->carttype == 0x45) {
props->mapper_id = 4;
props->has_sdd1 = 1;
props->error = MENU_ERR_NOIMPL;
props->error_param = (uint8_t*)"S-DD1";
props->fpga_conf = FPGA_SDD1;
}
/* Standard ExLoROM */
/* Standard LoROM */
else {
props->mapper_id = 1;
}
@@ -254,10 +255,8 @@ void smc_id(snes_romprops_t* props) {
case 3:
if(file_handle.fsize > 0x800200) {
props->mapper_id = 6; /* SO96 interleaved */
} else if(file_handle.fsize > 0x400200) {
props->mapper_id = 1; /* ExLoROM */
} else {
props->mapper_id = 1; /* LoROM */
props->mapper_id = 1; /* (Ex)LoROM */
}
break;
case 4:
@@ -0,0 +1,84 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : DCM_Scope.v
// /___/ /\ Timestamp : 12/02/2018 21:05:41
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle D:/sd2snes/verilog/sd2snes_sdd1/ipcore_dir/DCM_Scope.xaw -st DCM_Scope.v
//Design Name: DCM_Scope
//Device: xc3s400-4pq208
//
// Module DCM_Scope
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_INST = 0.07 UI
// Period Jitter (Peak-to-Peak) for block DCM_INST = 0.75 ns
`timescale 1ns / 1ps

module DCM_Scope(CLKIN_IN,
RST_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);

input CLKIN_IN;
input RST_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;

wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;

assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(41.667), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("TRUE") )
DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
@@ -0,0 +1,166 @@
----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 20:49:09
-- Design Name:
-- Module Name: FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FIFO_AXIS is
Generic( FIFO_DEPTH : integer := 32 );
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
din_tkeep : IN STD_LOGIC_VECTOR(1 downto 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC );
end FIFO_AXIS;


architecture Behavioral of FIFO_AXIS is

type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal data_cnt : integer range 0 to FIFO_DEPTH := 0;

signal din_tready_i : STD_LOGIC := '0';
signal dout_tvalid_i : STD_LOGIC := '0';

begin

Process( clk )
Begin
if rising_edge( clk ) then
if( srst = '1' ) then
FIFO_Array <= (others => (others => '0'));
wr_ptr <= 0;
rd_ptr <= 0;
data_cnt <= 0;
else
-- write command
if( din_tready_i = '1' AND din_tvalid = '1' ) then
-- write 2 bytes
if( din_tkeep = "11" ) then
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
FIFO_Array(0) <= din_tdata(15 downto 8);
wr_ptr <= 1;
elsif( wr_ptr = (FIFO_DEPTH-2) ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
FIFO_Array(wr_ptr+1) <= din_tdata(15 downto 8);
wr_ptr <= 0;
else
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
FIFO_Array(wr_ptr+1) <= din_tdata(15 downto 8);
wr_ptr <= wr_ptr + 2;
end if;
-- write 1 byte
elsif( din_tkeep = "01" ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);

-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
-- write 1 byte
elsif( din_tkeep = "10" ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(15 downto 8);

-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
end if;

-- read command
if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
-- check read pointer limits
if( rd_ptr = (FIFO_DEPTH-1) ) then
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end if;
end if;

-- occupancy control
-- read and write colision
if((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
if( din_tkeep = "11" ) then
data_cnt <= data_cnt + 1;
elsif( din_tkeep = "00" ) then
data_cnt <= data_cnt - 1;
end if;
-- write only
elsif((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '0' OR dout_tvalid_i = '0')) then
if( din_tkeep = "11" ) then
data_cnt <= data_cnt + 2;
elsif( din_tkeep = "01" OR din_tkeep = "10" ) then
data_cnt <= data_cnt + 1;
end if;
-- read only
elsif((din_tready_i = '0' OR din_tvalid = '0') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
data_cnt <= data_cnt - 1;
end if;
end if;
end if;
End Process;

-- first word fall-through
dout_tdata <= FIFO_Array(rd_ptr);
dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
dout_tvalid <= dout_tvalid_i;

-- flow control signals
empty <= '1' when data_cnt = 0 else '0';
full <= NOT din_tready_i;
din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-2) OR srst = '1') else '1';
din_tready <= din_tready_i;
end Behavioral;
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