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Move some hw config to config.h

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mrehkopf committed Dec 6, 2018
1 parent 447bb19 commit 4c17bd5997ad79aaadf8d5b0dee5f2fc18add425
Showing with 202 additions and 130 deletions.
  1. +1 −5 src/clock.c
  2. +105 −6 src/config.h
  3. +28 −27 src/fpga.c
  4. +11 −28 src/fpga.h
  5. +31 −40 src/led.c
  6. +25 −23 src/main.c
  7. +1 −1 src/memory.c
@@ -18,11 +18,7 @@ void clock_init() {
/* set flash access time to 5 clks (80<f<=100MHz) */
setFlashAccessTime(5);

/* setup PLL0 for 86MHz
Base clock: 12MHz
Multiplier: 23
Pre-Divisor: 2
Divisor: 6
/* setup PLL0 for 96MHz
First, disable and disconnect PLL0.
*/
clock_disconnect();
@@ -24,11 +24,18 @@

#define SD_DT_REG LPC_GPIO0
#define SD_DT_BIT 8
#define SD_HAS_WP
#define SD_WP_REG LPC_GPIO0
#define SD_WP_BIT 6

#define SDCARD_DETECT (!(BITBAND(SD_DT_REG->FIOPIN, SD_DT_BIT)))
#define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT))

#ifdef SD_HAS_WP
#define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT))
#else
#define SDCARD_WP (0)
#endif

#define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */
#define CONFIG_SD_BLOCKTRANSFER 1
#define CONFIG_SD_AUTO_RETRIES 10
@@ -45,6 +52,8 @@
//#define CONFIG_UART_BAUDRATE 115200
#define CONFIG_UART_DEADLOCKABLE

#define DEVICE_NAME "sd2snes Mk.II"

/* PLL0 96MHz
Base clock: 12MHz
Multiplier: 16
@@ -72,9 +81,52 @@
#define SNES_CIC_PAIR_REG LPC_GPIO1
#define SNES_CIC_PAIR_BIT 25

#define SNES_CIC_D0_MODEREG LPC_PINCON->PINMODE0
#define SNES_CIC_D0_MODEBIT 1

#define SNES_CIC_D1_MODEREG LPC_PINCON->PINMODE0
#define SNES_CIC_D1_MODEBIT 3

/*
FPGA pin mapping
================
CCLK P0.11 out
PROG_B P1.15 out
INIT_B P2.9 in
DIN P2.8 out
DONE P0.22 in
*/

#define FPGA_CONF_EXT "bit"

#define FPGA_CCLKREG LPC_GPIO0
#define FPGA_PROGBREG LPC_GPIO1
#define FPGA_INITBREG LPC_GPIO2
#define FPGA_DINREG LPC_GPIO2
#define FPGA_DONEREG LPC_GPIO0

#define FPGA_CCLKBIT (11)
#define FPGA_PROGBBIT (15)
#define FPGA_INITBBIT (9)
#define FPGA_DINBIT (8)
#define FPGA_DONEBIT (22)

#define FPGA_SEND_BYTE_SERIAL(data) do {SET_FPGA_DIN(data>>7); CCLK();\
SET_FPGA_DIN(data>>6); CCLK(); SET_FPGA_DIN(data>>5); CCLK();\
SET_FPGA_DIN(data>>4); CCLK(); SET_FPGA_DIN(data>>3); CCLK();\
SET_FPGA_DIN(data>>2); CCLK(); SET_FPGA_DIN(data>>1); CCLK();\
SET_FPGA_DIN(data); CCLK();} while (0)

#define FPGA_MCU_RDY_REG LPC_GPIO2
#define FPGA_MCU_RDY_BIT 9

#define FPGA_CLK_PINSEL LPC_PINCON->PINSEL0
#define FPGA_CLK_PINSELBIT 21

#define EMR_FPGACLK_EMCxTOGGLE (3<<4) /* EMC0TOGGLE */
#define MCR_FPGACLK_MRxR (1<<1) /* MR0R */
#define TMR_FPGACLK_MR LPC_TIM3->MR0

#define QSORT_MAXELEM 2048
#define SORT_STRLEN 256
#define CLTBL_SIZE 100
@@ -83,13 +135,9 @@

#define SSP_REGS LPC_SSP0
#define SSP_PCLKREG PCLKSEL1
// 1: PCLKSEL0
#define SSP_PCLKBIT 10
// 1: 20
#define SSP_DMAID_TX 0
// 1: 2
#define SSP_DMAID_RX 1
// 1: 3
#define SSP_DMACH LPC_GPDMACH0

#define SD_CLKREG LPC_GPIO0
@@ -106,9 +154,60 @@
#define SD_DAT2PIN (2)
#define SD_DAT3PIN (3)

#define SD_DAT (LPC_GPIO2->FIOPIN0)
#define SD_DAT (SD_DAT0REG->FIOPIN0)

#define USB_CONNREG LPC_GPIO4
#define USB_CONNBIT 28
#define USB_CONN_MODEREG LPC_PINCON->PINMODE9
#define USB_CONN_MODEBIT 25
#define USB_VBUS_PINSEL LPC_PINCON->PINSEL3
#define USB_VBUS_PINSELBIT 29
#define USB_VBUS_MODEREG LPC_PINCON->PINMODE3
#define USB_VBUS_MODEBIT 29

#define DAC_DEMREG LPC_GPIO1
#define DAC_DEMBIT 24

/* LED connections Mk.II
LED color IO PWM
---------------------------
ready green P2.4 PWM1[5]
read yellow P2.5 PWM1[6]
write red P1.23 PWM1[4]
*/


#define LED_READY_REG LPC_GPIO2
#define LED_READY_BIT 4
#define LED_READ_REG LPC_GPIO2
#define LED_READ_BIT 5
#define LED_WRITE_REG LPC_GPIO1
#define LED_WRITE_BIT 23

#define LED_READY_PINSEL LPC_PINCON->PINSEL4
#define LED_READ_PINSEL LPC_PINCON->PINSEL4
#define LED_WRITE_PINSEL LPC_PINCON->PINSEL3

#define LED_READY_PINSELSHIFT 8
#define LED_READ_PINSELSHIFT 10
#define LED_WRITE_PINSELSHIFT 14

#define LED_READY_PINSELVAL (0b01)
#define LED_READ_PINSELVAL (0b01)
#define LED_WRITE_PINSELVAL (0b10)

#define LED_READY_PCRBIT 13
#define LED_READ_PCRBIT 14
#define LED_WRITE_PCRBIT 12

#define LED_READY_MRNUM 5
#define LED_READ_MRNUM 6
#define LED_WRITE_MRNUM 4

#define LED_READY_MR LPC_PWM1->MR5
#define LED_READ_MR LPC_PWM1->MR6
#define LED_WRITE_MR LPC_PWM1->MR4

#define BOOTLDR_SIZE 8192
#endif
@@ -25,16 +25,6 @@
*/


/*
FPGA pin mapping
================
CCLK P0.11 out
PROG_B P1.15 out
INIT_B P2.9 in
DIN P2.8 out
DONE P0.22 in
*/

#include <arm/NXP/LPC17xx/LPC17xx.h>
#include "bits.h"

@@ -54,29 +44,29 @@

void fpga_set_prog_b(uint8_t val) {
if(val)
BITBAND(PROGBREG->FIOSET, PROGBBIT) = 1;
BITBAND(FPGA_PROGBREG->FIOSET, FPGA_PROGBBIT) = 1;
else
BITBAND(PROGBREG->FIOCLR, PROGBBIT) = 1;
BITBAND(FPGA_PROGBREG->FIOCLR, FPGA_PROGBBIT) = 1;
}

void fpga_set_cclk(uint8_t val) {
if(val)
BITBAND(CCLKREG->FIOSET, CCLKBIT) = 1;
BITBAND(FPGA_CCLKREG->FIOSET, FPGA_CCLKBIT) = 1;
else
BITBAND(CCLKREG->FIOCLR, CCLKBIT) = 1;
BITBAND(FPGA_CCLKREG->FIOCLR, FPGA_CCLKBIT) = 1;
}

int fpga_get_initb() {
return BITBAND(INITBREG->FIOPIN, INITBBIT);
return BITBAND(FPGA_INITBREG->FIOPIN, FPGA_INITBBIT);
}

void fpga_init() {
/* mainly GPIO directions */
BITBAND(CCLKREG->FIODIR, CCLKBIT) = 1; /* CCLK */
BITBAND(DONEREG->FIODIR, DONEBIT) = 0; /* DONE */
BITBAND(PROGBREG->FIODIR, PROGBBIT) = 1; /* PROG_B */
BITBAND(DINREG->FIODIR, DINBIT) = 1; /* DIN */
BITBAND(INITBREG->FIODIR, INITBBIT) = 0; /* INIT_B */
BITBAND(FPGA_CCLKREG->FIODIR, FPGA_CCLKBIT) = 1; /* CCLK */
BITBAND(FPGA_DONEREG->FIODIR, FPGA_DONEBIT) = 0; /* DONE */
BITBAND(FPGA_PROGBREG->FIODIR, FPGA_PROGBBIT) = 1; /* PROG_B */
BITBAND(FPGA_DINREG->FIODIR, FPGA_DINBIT) = 1; /* DIN */
BITBAND(FPGA_INITBREG->FIODIR, FPGA_INITBBIT) = 0; /* INIT_B */

LPC_GPIO2->FIOMASK1 = 0;

@@ -85,11 +75,12 @@ void fpga_init() {
}

int fpga_get_done(void) {
return BITBAND(DONEREG->FIOPIN, DONEBIT);
return BITBAND(FPGA_DONEREG->FIOPIN, FPGA_DONEBIT);
}

void fpga_postinit() {
LPC_GPIO2->FIOMASK1 = 0;
BITBAND(FPGA_DINREG->FIODIR, FPGA_DINBIT) = 0; /* DATA0 -> MCU_RDY */
}

void fpga_pgm(uint8_t* filename) {
@@ -105,14 +96,15 @@ void fpga_pgm(uint8_t* filename) {
uart_putc(0x30+file_res);
return;
}

fpga_init();
do {
printf("fpga_pgm: configuring FPGA, attempts left: %d\n", retries);
i=0;
timeout = getticks() + 1;
fpga_set_prog_b(0);
while(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
while(BITBAND(FPGA_PROGBREG->FIOPIN, FPGA_PROGBBIT)) {
if(getticks() > timeout) {
printf("PROGB is stuck high!\n");
printf("fpga_pgm: PROGB is stuck high!\n");
led_panic(LED_PANIC_FPGA_PROGB_STUCK);
}
}
@@ -121,14 +113,14 @@ void fpga_pgm(uint8_t* filename) {
fpga_set_prog_b(1);
while(!fpga_get_initb()){
if(getticks() > timeout) {
printf("no response from FPGA trying to initiate configuration!\n");
printf("fpga_pgm: no response from FPGA trying to initiate configuration!\n");
led_panic(LED_PANIC_FPGA_NO_INITB);
}
};
timeout = getticks() + 100;
while(fpga_get_done()) {
if(getticks() > timeout) {
printf("DONE is stuck high!\n");
printf("fpga_pgm: DONE is stuck high!\n");
led_panic(LED_PANIC_FPGA_DONE_STUCK);
}
}
@@ -145,10 +137,18 @@ void fpga_pgm(uint8_t* filename) {
uart_putc('c');
file_close();
printf("fpga_pgm: %d bytes programmed\n", i);
timeout = getticks() + 100;
while(!fpga_get_done()) {
if(getticks() > timeout) {
printf("fpga_pgm: no DONE from FPGA! Retrying\n");
break;
}
}
CCLK(); CCLK(); CCLK();
delay_ms(1);
} while (!fpga_get_done() && retries--);
if(!fpga_get_done()) {
printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
printf("fpga_pgm: FPGA failed to configure after %d tries.\n", MAXRETRIES);
led_panic(LED_PANIC_FPGA_NOCONF);
}
printf("FPGA configured\n");
@@ -162,6 +162,7 @@ void fpga_rompgm() {
uint8_t data;
int i;
tick_t timeout;
fpga_init();
do {
i=0;
timeout = getticks() + 100;
@@ -29,6 +29,7 @@

#include <arm/NXP/LPC17xx/LPC17xx.h>
#include "bits.h"
#include "config.h"

void fpga_set_prog_b(uint8_t val);
void fpga_set_cclk(uint8_t val);
@@ -43,36 +44,18 @@ uint8_t SPI_OFFLOAD;

const uint8_t *fpga_config;

#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4.bit")
#define FPGA_OBC1 ((const uint8_t*)"/sd2snes/fpga_obc1.bit")
#define FPGA_GSU ((const uint8_t*)"/sd2snes/fpga_gsu.bit")
#define FPGA_SA1 ((const uint8_t*)"/sd2snes/fpga_sa1.bit")
#define FPGA_BASE ((const uint8_t*)"/sd2snes/fpga_base.bit")
#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4." FPGA_CONF_EXT)
#define FPGA_OBC1 ((const uint8_t*)"/sd2snes/fpga_obc1." FPGA_CONF_EXT)
#define FPGA_GSU ((const uint8_t*)"/sd2snes/fpga_gsu." FPGA_CONF_EXT)
#define FPGA_SA1 ((const uint8_t*)"/sd2snes/fpga_sa1." FPGA_CONF_EXT)
#define FPGA_BASE ((const uint8_t*)"/sd2snes/fpga_base." FPGA_CONF_EXT)
#define FPGA_ROM ((const uint8_t*)"rom")

#define CCLKREG LPC_GPIO0
#define PROGBREG LPC_GPIO1
#define INITBREG LPC_GPIO2
#define DINREG LPC_GPIO2
#define DONEREG LPC_GPIO0

#define CCLKBIT (11)
#define PROGBBIT (15)
#define INITBBIT (9)
#define DINBIT (8)
#define DONEBIT (22)


#define FPGA_TEST_TOKEN (0xa5)

// some macros for bulk transfers (faster)
#define FPGA_SEND_BYTE_SERIAL(data) do {SET_FPGA_DIN(data>>7); CCLK();\
SET_FPGA_DIN(data>>6); CCLK(); SET_FPGA_DIN(data>>5); CCLK();\
SET_FPGA_DIN(data>>4); CCLK(); SET_FPGA_DIN(data>>3); CCLK();\
SET_FPGA_DIN(data>>2); CCLK(); SET_FPGA_DIN(data>>1); CCLK();\
SET_FPGA_DIN(data); CCLK();} while (0)
#define SET_CCLK() do {BITBAND(LPC_GPIO0->FIOSET, 11) = 1;} while (0)
#define CLR_CCLK() do {BITBAND(LPC_GPIO0->FIOCLR, 11) = 1;} while (0)
#define CCLK() do {SET_CCLK(); CLR_CCLK();} while (0)
#define SET_FPGA_DIN(data) do {LPC_GPIO2->FIOPIN1 = data;} while (0)
#endif
#define SET_CCLK() do {BITBAND(FPGA_CCLKREG->FIOSET, FPGA_CCLKBIT) = 1;} while (0)
#define CLR_CCLK() do {BITBAND(FPGA_CCLKREG->FIOCLR, FPGA_CCLKBIT) = 1;} while (0)
#define CCLK() do {SET_CCLK(); CLR_CCLK();} while (0)
#define SET_FPGA_DIN(data) do {FPGA_DINREG->FIOPIN1 = data;} while (0)
#endif
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