From 4c17bd5997ad79aaadf8d5b0dee5f2fc18add425 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 7 Dec 2018 00:28:00 +0100 Subject: [PATCH] Move some hw config to config.h --- src/clock.c | 6 +-- src/config.h | 111 ++++++++++++++++++++++++++++++++++++++++++++++++--- src/fpga.c | 55 ++++++++++++------------- src/fpga.h | 39 +++++------------- src/led.c | 71 ++++++++++++++------------------ src/main.c | 48 +++++++++++----------- src/memory.c | 2 +- 7 files changed, 202 insertions(+), 130 deletions(-) diff --git a/src/clock.c b/src/clock.c index 370ad1ed..0e4e1e20 100644 --- a/src/clock.c +++ b/src/clock.c @@ -18,11 +18,7 @@ void clock_init() { /* set flash access time to 5 clks (80FIOPIN, SD_DT_BIT))) -#define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT)) + +#ifdef SD_HAS_WP + #define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT)) +#else + #define SDCARD_WP (0) +#endif + #define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */ #define CONFIG_SD_BLOCKTRANSFER 1 #define CONFIG_SD_AUTO_RETRIES 10 @@ -45,6 +52,8 @@ //#define CONFIG_UART_BAUDRATE 115200 #define CONFIG_UART_DEADLOCKABLE +#define DEVICE_NAME "sd2snes Mk.II" + /* PLL0 96MHz Base clock: 12MHz Multiplier: 16 @@ -72,9 +81,52 @@ #define SNES_CIC_PAIR_REG LPC_GPIO1 #define SNES_CIC_PAIR_BIT 25 +#define SNES_CIC_D0_MODEREG LPC_PINCON->PINMODE0 +#define SNES_CIC_D0_MODEBIT 1 + +#define SNES_CIC_D1_MODEREG LPC_PINCON->PINMODE0 +#define SNES_CIC_D1_MODEBIT 3 + +/* + FPGA pin mapping + ================ + CCLK P0.11 out + PROG_B P1.15 out + INIT_B P2.9 in + DIN P2.8 out + DONE P0.22 in + */ + +#define FPGA_CONF_EXT "bit" + +#define FPGA_CCLKREG LPC_GPIO0 +#define FPGA_PROGBREG LPC_GPIO1 +#define FPGA_INITBREG LPC_GPIO2 +#define FPGA_DINREG LPC_GPIO2 +#define FPGA_DONEREG LPC_GPIO0 + +#define FPGA_CCLKBIT (11) +#define FPGA_PROGBBIT (15) +#define FPGA_INITBBIT (9) +#define FPGA_DINBIT (8) +#define FPGA_DONEBIT (22) + +#define FPGA_SEND_BYTE_SERIAL(data) do {SET_FPGA_DIN(data>>7); CCLK();\ +SET_FPGA_DIN(data>>6); CCLK(); SET_FPGA_DIN(data>>5); CCLK();\ +SET_FPGA_DIN(data>>4); CCLK(); SET_FPGA_DIN(data>>3); CCLK();\ +SET_FPGA_DIN(data>>2); CCLK(); SET_FPGA_DIN(data>>1); CCLK();\ +SET_FPGA_DIN(data); CCLK();} while (0) + #define FPGA_MCU_RDY_REG LPC_GPIO2 #define FPGA_MCU_RDY_BIT 9 +#define FPGA_CLK_PINSEL LPC_PINCON->PINSEL0 +#define FPGA_CLK_PINSELBIT 21 + +#define EMR_FPGACLK_EMCxTOGGLE (3<<4) /* EMC0TOGGLE */ +#define MCR_FPGACLK_MRxR (1<<1) /* MR0R */ +#define TMR_FPGACLK_MR LPC_TIM3->MR0 + #define QSORT_MAXELEM 2048 #define SORT_STRLEN 256 #define CLTBL_SIZE 100 @@ -83,13 +135,9 @@ #define SSP_REGS LPC_SSP0 #define SSP_PCLKREG PCLKSEL1 -// 1: PCLKSEL0 #define SSP_PCLKBIT 10 -// 1: 20 #define SSP_DMAID_TX 0 -// 1: 2 #define SSP_DMAID_RX 1 -// 1: 3 #define SSP_DMACH LPC_GPDMACH0 #define SD_CLKREG LPC_GPIO0 @@ -106,9 +154,60 @@ #define SD_DAT2PIN (2) #define SD_DAT3PIN (3) -#define SD_DAT (LPC_GPIO2->FIOPIN0) +#define SD_DAT (SD_DAT0REG->FIOPIN0) #define USB_CONNREG LPC_GPIO4 #define USB_CONNBIT 28 +#define USB_CONN_MODEREG LPC_PINCON->PINMODE9 +#define USB_CONN_MODEBIT 25 +#define USB_VBUS_PINSEL LPC_PINCON->PINSEL3 +#define USB_VBUS_PINSELBIT 29 +#define USB_VBUS_MODEREG LPC_PINCON->PINMODE3 +#define USB_VBUS_MODEBIT 29 + +#define DAC_DEMREG LPC_GPIO1 +#define DAC_DEMBIT 24 + +/* LED connections Mk.II + + LED color IO PWM + --------------------------- + ready green P2.4 PWM1[5] + read yellow P2.5 PWM1[6] + write red P1.23 PWM1[4] +*/ + + +#define LED_READY_REG LPC_GPIO2 +#define LED_READY_BIT 4 +#define LED_READ_REG LPC_GPIO2 +#define LED_READ_BIT 5 +#define LED_WRITE_REG LPC_GPIO1 +#define LED_WRITE_BIT 23 + +#define LED_READY_PINSEL LPC_PINCON->PINSEL4 +#define LED_READ_PINSEL LPC_PINCON->PINSEL4 +#define LED_WRITE_PINSEL LPC_PINCON->PINSEL3 + +#define LED_READY_PINSELSHIFT 8 +#define LED_READ_PINSELSHIFT 10 +#define LED_WRITE_PINSELSHIFT 14 + +#define LED_READY_PINSELVAL (0b01) +#define LED_READ_PINSELVAL (0b01) +#define LED_WRITE_PINSELVAL (0b10) + +#define LED_READY_PCRBIT 13 +#define LED_READ_PCRBIT 14 +#define LED_WRITE_PCRBIT 12 + +#define LED_READY_MRNUM 5 +#define LED_READ_MRNUM 6 +#define LED_WRITE_MRNUM 4 + +#define LED_READY_MR LPC_PWM1->MR5 +#define LED_READ_MR LPC_PWM1->MR6 +#define LED_WRITE_MR LPC_PWM1->MR4 +#define BOOTLDR_SIZE 8192 #endif diff --git a/src/fpga.c b/src/fpga.c index 62445cc6..d4ab8300 100644 --- a/src/fpga.c +++ b/src/fpga.c @@ -25,16 +25,6 @@ */ -/* - FPGA pin mapping - ================ - CCLK P0.11 out - PROG_B P1.15 out - INIT_B P2.9 in - DIN P2.8 out - DONE P0.22 in - */ - #include #include "bits.h" @@ -54,29 +44,29 @@ void fpga_set_prog_b(uint8_t val) { if(val) - BITBAND(PROGBREG->FIOSET, PROGBBIT) = 1; + BITBAND(FPGA_PROGBREG->FIOSET, FPGA_PROGBBIT) = 1; else - BITBAND(PROGBREG->FIOCLR, PROGBBIT) = 1; + BITBAND(FPGA_PROGBREG->FIOCLR, FPGA_PROGBBIT) = 1; } void fpga_set_cclk(uint8_t val) { if(val) - BITBAND(CCLKREG->FIOSET, CCLKBIT) = 1; + BITBAND(FPGA_CCLKREG->FIOSET, FPGA_CCLKBIT) = 1; else - BITBAND(CCLKREG->FIOCLR, CCLKBIT) = 1; + BITBAND(FPGA_CCLKREG->FIOCLR, FPGA_CCLKBIT) = 1; } int fpga_get_initb() { - return BITBAND(INITBREG->FIOPIN, INITBBIT); + return BITBAND(FPGA_INITBREG->FIOPIN, FPGA_INITBBIT); } void fpga_init() { /* mainly GPIO directions */ - BITBAND(CCLKREG->FIODIR, CCLKBIT) = 1; /* CCLK */ - BITBAND(DONEREG->FIODIR, DONEBIT) = 0; /* DONE */ - BITBAND(PROGBREG->FIODIR, PROGBBIT) = 1; /* PROG_B */ - BITBAND(DINREG->FIODIR, DINBIT) = 1; /* DIN */ - BITBAND(INITBREG->FIODIR, INITBBIT) = 0; /* INIT_B */ + BITBAND(FPGA_CCLKREG->FIODIR, FPGA_CCLKBIT) = 1; /* CCLK */ + BITBAND(FPGA_DONEREG->FIODIR, FPGA_DONEBIT) = 0; /* DONE */ + BITBAND(FPGA_PROGBREG->FIODIR, FPGA_PROGBBIT) = 1; /* PROG_B */ + BITBAND(FPGA_DINREG->FIODIR, FPGA_DINBIT) = 1; /* DIN */ + BITBAND(FPGA_INITBREG->FIODIR, FPGA_INITBBIT) = 0; /* INIT_B */ LPC_GPIO2->FIOMASK1 = 0; @@ -85,11 +75,12 @@ void fpga_init() { } int fpga_get_done(void) { - return BITBAND(DONEREG->FIOPIN, DONEBIT); + return BITBAND(FPGA_DONEREG->FIOPIN, FPGA_DONEBIT); } void fpga_postinit() { LPC_GPIO2->FIOMASK1 = 0; + BITBAND(FPGA_DINREG->FIODIR, FPGA_DINBIT) = 0; /* DATA0 -> MCU_RDY */ } void fpga_pgm(uint8_t* filename) { @@ -105,14 +96,15 @@ void fpga_pgm(uint8_t* filename) { uart_putc(0x30+file_res); return; } - + fpga_init(); do { + printf("fpga_pgm: configuring FPGA, attempts left: %d\n", retries); i=0; timeout = getticks() + 1; fpga_set_prog_b(0); - while(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) { + while(BITBAND(FPGA_PROGBREG->FIOPIN, FPGA_PROGBBIT)) { if(getticks() > timeout) { - printf("PROGB is stuck high!\n"); + printf("fpga_pgm: PROGB is stuck high!\n"); led_panic(LED_PANIC_FPGA_PROGB_STUCK); } } @@ -121,14 +113,14 @@ void fpga_pgm(uint8_t* filename) { fpga_set_prog_b(1); while(!fpga_get_initb()){ if(getticks() > timeout) { - printf("no response from FPGA trying to initiate configuration!\n"); + printf("fpga_pgm: no response from FPGA trying to initiate configuration!\n"); led_panic(LED_PANIC_FPGA_NO_INITB); } }; timeout = getticks() + 100; while(fpga_get_done()) { if(getticks() > timeout) { - printf("DONE is stuck high!\n"); + printf("fpga_pgm: DONE is stuck high!\n"); led_panic(LED_PANIC_FPGA_DONE_STUCK); } } @@ -145,10 +137,18 @@ void fpga_pgm(uint8_t* filename) { uart_putc('c'); file_close(); printf("fpga_pgm: %d bytes programmed\n", i); + timeout = getticks() + 100; + while(!fpga_get_done()) { + if(getticks() > timeout) { + printf("fpga_pgm: no DONE from FPGA! Retrying\n"); + break; + } + } + CCLK(); CCLK(); CCLK(); delay_ms(1); } while (!fpga_get_done() && retries--); if(!fpga_get_done()) { - printf("FPGA failed to configure after %d tries.\n", MAXRETRIES); + printf("fpga_pgm: FPGA failed to configure after %d tries.\n", MAXRETRIES); led_panic(LED_PANIC_FPGA_NOCONF); } printf("FPGA configured\n"); @@ -162,6 +162,7 @@ void fpga_rompgm() { uint8_t data; int i; tick_t timeout; + fpga_init(); do { i=0; timeout = getticks() + 100; diff --git a/src/fpga.h b/src/fpga.h index 49e4c4ce..e11a659f 100644 --- a/src/fpga.h +++ b/src/fpga.h @@ -29,6 +29,7 @@ #include #include "bits.h" +#include "config.h" void fpga_set_prog_b(uint8_t val); void fpga_set_cclk(uint8_t val); @@ -43,36 +44,18 @@ uint8_t SPI_OFFLOAD; const uint8_t *fpga_config; -#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4.bit") -#define FPGA_OBC1 ((const uint8_t*)"/sd2snes/fpga_obc1.bit") -#define FPGA_GSU ((const uint8_t*)"/sd2snes/fpga_gsu.bit") -#define FPGA_SA1 ((const uint8_t*)"/sd2snes/fpga_sa1.bit") -#define FPGA_BASE ((const uint8_t*)"/sd2snes/fpga_base.bit") +#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4." FPGA_CONF_EXT) +#define FPGA_OBC1 ((const uint8_t*)"/sd2snes/fpga_obc1." FPGA_CONF_EXT) +#define FPGA_GSU ((const uint8_t*)"/sd2snes/fpga_gsu." FPGA_CONF_EXT) +#define FPGA_SA1 ((const uint8_t*)"/sd2snes/fpga_sa1." FPGA_CONF_EXT) +#define FPGA_BASE ((const uint8_t*)"/sd2snes/fpga_base." FPGA_CONF_EXT) #define FPGA_ROM ((const uint8_t*)"rom") -#define CCLKREG LPC_GPIO0 -#define PROGBREG LPC_GPIO1 -#define INITBREG LPC_GPIO2 -#define DINREG LPC_GPIO2 -#define DONEREG LPC_GPIO0 - -#define CCLKBIT (11) -#define PROGBBIT (15) -#define INITBBIT (9) -#define DINBIT (8) -#define DONEBIT (22) - - #define FPGA_TEST_TOKEN (0xa5) // some macros for bulk transfers (faster) -#define FPGA_SEND_BYTE_SERIAL(data) do {SET_FPGA_DIN(data>>7); CCLK();\ -SET_FPGA_DIN(data>>6); CCLK(); SET_FPGA_DIN(data>>5); CCLK();\ -SET_FPGA_DIN(data>>4); CCLK(); SET_FPGA_DIN(data>>3); CCLK();\ -SET_FPGA_DIN(data>>2); CCLK(); SET_FPGA_DIN(data>>1); CCLK();\ -SET_FPGA_DIN(data); CCLK();} while (0) -#define SET_CCLK() do {BITBAND(LPC_GPIO0->FIOSET, 11) = 1;} while (0) -#define CLR_CCLK() do {BITBAND(LPC_GPIO0->FIOCLR, 11) = 1;} while (0) -#define CCLK() do {SET_CCLK(); CLR_CCLK();} while (0) -#define SET_FPGA_DIN(data) do {LPC_GPIO2->FIOPIN1 = data;} while (0) -#endif +#define SET_CCLK() do {BITBAND(FPGA_CCLKREG->FIOSET, FPGA_CCLKBIT) = 1;} while (0) +#define CLR_CCLK() do {BITBAND(FPGA_CCLKREG->FIOCLR, FPGA_CCLKBIT) = 1;} while (0) +#define CCLK() do {SET_CCLK(); CLR_CCLK();} while (0) +#define SET_FPGA_DIN(data) do {FPGA_DINREG->FIOPIN1 = data;} while (0) +#endif \ No newline at end of file diff --git a/src/led.c b/src/led.c index 2fe7b375..5d26d08d 100644 --- a/src/led.c +++ b/src/led.c @@ -7,6 +7,7 @@ #include "cli.h" #include "fileops.h" #include "cfg.h" +#include "config.h" static uint16_t led_bright[16]={60000, 59920, 59871, 59794, 59669, 59469, 59148, 58633, @@ -20,20 +21,11 @@ int led_pwmstate = 0; extern cfg_t CFG; -/* LED connections (Rev.C) - - LED color IO PWM - --------------------------- - ready green P2.4 PWM1[5] - read yellow P2.5 PWM1[6] - write red P1.23 PWM1[4] -*/ - void rdyled(unsigned int state) { if(led_pwmstate) { rdybright(state ? CFG.led_brightness : 0); } else { - BITBAND(LPC_GPIO2->FIODIR, 4) = state; + BITBAND(LED_READY_REG->FIODIR, LED_READY_BIT) = state; } led_rdyledstate = state; } @@ -42,7 +34,7 @@ void readled(unsigned int state) { if(led_pwmstate) { readbright(state ? CFG.led_brightness : 0); } else { - BITBAND(LPC_GPIO2->FIODIR, 5) = state; + BITBAND(LED_READ_REG->FIODIR, LED_READ_BIT) = state; } led_readledstate = state; } @@ -51,22 +43,24 @@ void writeled(unsigned int state) { if(led_pwmstate) { writebright(state ? CFG.led_brightness : 0); } else { - BITBAND(LPC_GPIO1->FIODIR, 23) = state; + BITBAND(LED_WRITE_REG->FIODIR, LED_WRITE_BIT) = state; } led_writeledstate = state; } void rdybright(uint8_t bright) { - LPC_PWM1->MR5 = led_bright[(bright & 15)]; - BITBAND(LPC_PWM1->LER, 5) = 1; + LED_READY_MR = led_bright[(bright & 15)]; + BITBAND(LPC_PWM1->LER, LED_READY_MRNUM) = 1; } + void readbright(uint8_t bright) { - LPC_PWM1->MR6 = led_bright[(bright & 15)]; - BITBAND(LPC_PWM1->LER, 6) = 1; + LED_READ_MR = led_bright[(bright & 15)]; + BITBAND(LPC_PWM1->LER, LED_READ_MRNUM) = 1; } + void writebright(uint8_t bright) { - LPC_PWM1->MR4 = led_bright[(bright & 15)]; - BITBAND(LPC_PWM1->LER, 4) = 1; + LED_WRITE_MR = led_bright[(bright & 15)]; + BITBAND(LPC_PWM1->LER, LED_WRITE_MRNUM) = 1; } void led_clkout32(uint32_t val) { @@ -108,43 +102,40 @@ void led_panic(uint8_t led_states) { } void led_pwm() { -/* Rev.C P2.4, P2.5, P1.23 */ - BITBAND(LPC_PINCON->PINSEL4, 9) = 0; - BITBAND(LPC_PINCON->PINSEL4, 8) = 1; + LED_READY_PINSEL = (LED_READY_PINSEL & ~(0b11 << LED_READY_PINSELSHIFT)) + | (LED_READY_PINSELVAL << LED_READY_PINSELSHIFT); + LED_READ_PINSEL = (LED_READ_PINSEL & ~(0b11 << LED_READ_PINSELSHIFT)) + | (LED_READ_PINSELVAL << LED_READ_PINSELSHIFT); + LED_WRITE_PINSEL = (LED_WRITE_PINSEL & ~(0b11 << LED_WRITE_PINSELSHIFT)) + | (LED_WRITE_PINSELVAL << LED_WRITE_PINSELSHIFT); - BITBAND(LPC_PINCON->PINSEL4, 11) = 0; - BITBAND(LPC_PINCON->PINSEL4, 10) = 1; + BITBAND(LPC_PWM1->PCR, LED_READY_PCRBIT) = 1; + BITBAND(LPC_PWM1->PCR, LED_READ_PCRBIT) = 1; + BITBAND(LPC_PWM1->PCR, LED_WRITE_PCRBIT) = 1; - BITBAND(LPC_PINCON->PINSEL3, 15) = 1; - BITBAND(LPC_PINCON->PINSEL3, 14) = 0; + BITBAND(LED_READY_REG->FIODIR, LED_READY_BIT) = 1; + BITBAND(LED_READ_REG->FIODIR, LED_READ_BIT) = 1; + BITBAND(LED_WRITE_REG->FIODIR, LED_WRITE_BIT) = 1; - BITBAND(LPC_PWM1->PCR, 12) = 1; - BITBAND(LPC_PWM1->PCR, 13) = 1; - BITBAND(LPC_PWM1->PCR, 14) = 1; led_pwmstate = 1; } void led_std() { - BITBAND(LPC_PINCON->PINSEL4, 9) = 0; - BITBAND(LPC_PINCON->PINSEL4, 8) = 0; - - BITBAND(LPC_PINCON->PINSEL4, 11) = 0; - BITBAND(LPC_PINCON->PINSEL4, 10) = 0; - - BITBAND(LPC_PINCON->PINSEL3, 15) = 0; - BITBAND(LPC_PINCON->PINSEL3, 14) = 0; + LED_READY_PINSEL = (LED_READY_PINSEL & ~(0b11 << LED_READY_PINSELSHIFT)); + LED_READ_PINSEL = (LED_READ_PINSEL & ~(0b11 << LED_READ_PINSELSHIFT)); + LED_WRITE_PINSEL = (LED_WRITE_PINSEL & ~(0b11 << LED_WRITE_PINSELSHIFT)); - BITBAND(LPC_PWM1->PCR, 12) = 0; - BITBAND(LPC_PWM1->PCR, 13) = 0; - BITBAND(LPC_PWM1->PCR, 14) = 0; + BITBAND(LPC_PWM1->PCR, LED_READY_PCRBIT) = 0; + BITBAND(LPC_PWM1->PCR, LED_READ_PCRBIT) = 0; + BITBAND(LPC_PWM1->PCR, LED_WRITE_PCRBIT) = 0; led_pwmstate = 0; } void led_init() { /* power is already connected by default */ -/* set PCLK divider to 8 */ +/* set PCLK divider for PWM1 to CCLK / 8 */ BITBAND(LPC_SC->PCLKSEL0, 13) = 1; BITBAND(LPC_SC->PCLKSEL0, 12) = 1; /* PWM rate 200Hz -> 60000 counts */ diff --git a/src/main.c b/src/main.c index 371a9298..6aedd037 100644 --- a/src/main.c +++ b/src/main.c @@ -28,9 +28,7 @@ #include "rtc.h" #include "sysinfo.h" #include "cfg.h" - -#define EMC0TOGGLE (3<<4) -#define MR0R (1<<1) +#include "check.h" int i; @@ -65,24 +63,28 @@ uart_putc('\n'); } int main(void) { - LPC_GPIO2->FIODIR = BV(4) | BV(5); - LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT); + SNES_CIC_PAIR_REG->FIODIR = BV(SNES_CIC_PAIR_BIT); BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1; - LPC_GPIO0->FIODIR = BV(16); - /* disable pull-up on fake USB_CONNECT pin (P4.28), set P1.30 function to VBUS */ - LPC_PINCON->PINMODE9 |= BV(25); - LPC_PINCON->PINSEL3 |= BV(29); - LPC_PINCON->PINMODE3 |= BV(29); + BITBAND(DAC_DEMREG->FIODIR, DAC_DEMBIT) = 1; + BITBAND(DAC_DEMREG->FIOSET, DAC_DEMBIT) = 1; + + /* disable pull-up on fake USB_CONNECT pin, set P1.30 function to VBUS */ + USB_CONN_MODEREG |= BV(USB_CONN_MODEBIT); + USB_VBUS_PINSEL |= BV(USB_VBUS_PINSELBIT); + USB_VBUS_MODEREG |= BV(USB_VBUS_MODEBIT); - /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */ + /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] */ LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */ | BV(3) | BV(5); /* SSP0 (FPGA) except SS */ - LPC_PINCON->PINSEL0 = BV(31); /* SSP0 */ -/* | BV(13) | BV(15) | BV(17) | BV(19) SSP1 (SD) */ + LPC_PINCON->PINSEL0 = BV(31); /* SSP0 */ + LPC_GPIO0->FIODIR = BV(16); /* SSP0 SS */ /* pull-down CIC data lines */ - LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3); + BITBAND(SNES_CIC_D0_MODEREG, SNES_CIC_D0_MODEBIT) = 1; + BITBAND(SNES_CIC_D0_MODEREG, SNES_CIC_D0_MODEBIT - 1) = 1; + BITBAND(SNES_CIC_D1_MODEREG, SNES_CIC_D1_MODEBIT) = 1; + BITBAND(SNES_CIC_D1_MODEREG, SNES_CIC_D1_MODEBIT - 1) = 1; clock_disconnect(); snes_init(); @@ -95,22 +97,22 @@ int main(void) { led_init(); /* do this last because the peripheral init()s change PCLK dividers */ clock_init(); - LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ + FPGA_CLK_PINSEL |= BV(FPGA_CLK_PINSELBIT) | BV(FPGA_CLK_PINSELBIT - 1); /* MAT3.x (FPGA clock) */ led_std(); sdn_init(); - printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY); + printf("\n\n" DEVICE_NAME "\n===============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY); printf("PCONP=%lx\n", LPC_SC->PCONP); file_init(); cic_init(0); /* setup timer (fpga clk) */ - LPC_TIM3->TCR=2; - LPC_TIM3->CTCR=0; - LPC_TIM3->PR=0; - LPC_TIM3->EMR=EMC0TOGGLE; - LPC_TIM3->MCR=MR0R; - LPC_TIM3->MR0=1; - LPC_TIM3->TCR=1; + LPC_TIM3->TCR=2; // counter reset + LPC_TIM3->CTCR=0; // increment TC on PCLK + LPC_TIM3->PR=0; // prescale = 1:1 (increment TC every PCLK) + LPC_TIM3->EMR=EMR_FPGACLK_EMCxTOGGLE; // toggle MAT3 output every time TC == MR + LPC_TIM3->MCR=MCR_FPGACLK_MRxR; // reset TC when == MR + TMR_FPGACLK_MR=1; // MR = 1 -> toggle MAT3 output every 2 PCLK -> FPGA_CLK = PCLK / 4 + LPC_TIM3->TCR=1; // start the counter fpga_init(); firstboot = 1; while(1) { diff --git a/src/memory.c b/src/memory.c index 6e2c2852..9af1e91d 100644 --- a/src/memory.c +++ b/src/memory.c @@ -663,7 +663,7 @@ uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) { crc_valid=1; set_mcu_addr(base_addr); FPGA_SELECT(); - FPGA_TX_BYTE(0x88); + FPGA_TX_BYTE(FPGA_CMD_READMEM | FPGA_MEM_AUTOINC); for(count=0; count