Permalink
Browse files

Updated timing parameters.

Added support for ingame hooks.  Disabled for Doom.
  • Loading branch information...
RedGuyyyy committed May 2, 2018
1 parent 11dcb3b commit 4d033bf76d991902977d87a33407cf16057b6e69
@@ -73,7 +73,7 @@ int cfg_save() {
f_puts("\n# Enhancement chip settings\n", &file_handle);
f_printf(&file_handle, "# %s: Cx4 core speed (0: original, 1: fast, all instructions are single cycle)\n", CFG_CX4_SPEED);
f_printf(&file_handle, "%s: %d\n", CFG_CX4_SPEED, CFG.cx4_speed);
f_printf(&file_handle, "# %s: GSU core speed (0: original, 1: fast, all instructions are single cycle)\n", CFG_GSU_SPEED);
f_printf(&file_handle, "# %s: GSU core speed (0: original, 1: fast, instructions execute as fast as the implementation allows)\n", CFG_GSU_SPEED);
f_printf(&file_handle, "%s: %d\n", CFG_GSU_SPEED, CFG.gsu_speed);
f_printf(&file_handle, "# %s: MSU audio volume boost\n# (0: none; 1: +3.5dBFS; 2: +6dBFS; 3: +9.5dBFS; 4: +12dBFS)\n", CFG_MSU_VOLUME_BOOST);
f_printf(&file_handle, "%s: %d\n", CFG_MSU_VOLUME_BOOST, CFG.msu_volume_boost);
@@ -56,10 +56,10 @@ void cheat_program() {
printf("enable mask=%02x\n", enable_mask);
fpga_write_cheat(6, enable_mask);
cheat_enable(1);
cheat_nmi_enable(romprops.has_gsu ? 0 : CFG.enable_irq_hook);
//cheat_nmi_enable(CFG.enable_irq_hook);
cheat_irq_enable(romprops.has_gsu ? 0 : CFG.enable_irq_hook);
//cheat_irq_enable(CFG.enable_irq_hook);
//cheat_nmi_enable(romprops.has_gsu ? 0 : CFG.enable_irq_hook);
cheat_nmi_enable(CFG.enable_irq_hook);
//cheat_irq_enable(romprops.has_gsu ? 0 : CFG.enable_irq_hook);
cheat_irq_enable((romprops.has_gsu && !strncmp((char *)romprops.header.name, "DOOM", strlen("DOOM"))) ? 0 : CFG.enable_irq_hook);
cheat_holdoff_enable(CFG.enable_irq_holdoff);
cheat_buttons_enable(CFG.enable_irq_buttons);
cheat_wram_present(wram_index);
@@ -1,5 +1,5 @@
CONFIG_VERSION="0.1.7e-gsu-v08"
CONFIG_VERSION="0.1.7e-gsu-v09"
#CONFIG_FWVER=0x01010705
CONFIG_FWVER=0xFFFFFFF0
CONFIG_FWVER=0xFFFFFFEE
#CONFIG_FWVER=0x44534E53
CONFIG_MCU_FOSC=12000000
@@ -331,7 +331,7 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
printf("gsu=%x gsu_sram=%x\n", romprops.has_gsu, romprops.has_gsu_sram);
if(flags & LOADROM_WITH_SRAM) {
if(romprops.ramsize_bytes) {
sram_memset(SRAM_SAVE_ADDR, romprops.ramsize_bytes, romprops.has_gsu ? 0x00 : 0xFF);
sram_memset(SRAM_SAVE_ADDR, romprops.ramsize_bytes, 0xFF);
if (!romprops.has_gsu || romprops.has_gsu_sram) migrate_and_load_srm(filename, SRAM_SAVE_ADDR);
/* file not found error is ok (SRM file might not exist yet) */
if(file_res == FR_NO_FILE) file_res = 0;
@@ -44,6 +44,9 @@ module cheat(
output snescmd_unlock
);
reg [23:0] snes_addr_d1;
always @(posedge clk) snes_addr_d1 <= SNES_ADDR;
wire snescmd_wr_strobe = snescmd_enable & SNES_wr_strobe;
reg cheat_enable = 0;
@@ -98,7 +101,7 @@ wire [5:0] cheat_match_bits ={(cheat_enable_mask[5] & (SNES_ADDR == cheat_addr[5
(cheat_enable_mask[0] & (SNES_ADDR == cheat_addr[0]))};
wire cheat_addr_match = |cheat_match_bits;
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB} | ({SNES_ADDR[3:0] == 4'hA, SNES_ADDR[3:0] == 4'hB} & {2{gsu_vec_enable}});
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB};
wire [1:0] irq_match_bits = {SNES_ADDR == 24'h00FFEE, SNES_ADDR == 24'h00FFEF};
wire [1:0] rst_match_bits = {SNES_ADDR == 24'h00FFFC, SNES_ADDR == 24'h00FFFD};
@@ -203,13 +206,19 @@ always @(posedge clk) begin
// remember where we came from (IRQ/NMI) for hook exit
return_vector <= SNES_ADDR[7:0];
snescmd_unlock_r <= 1;
// clear unlock countdown if we are entering the snescmd region. this is to avoid a prior snescmd lock countdown re-locking before we are done
snescmd_unlock_disable <= 0;
snescmd_unlock_disable_countdown <= 0;
end
if(rst_match_bits[1] & |reset_unlock_r) begin
else if(rst_match_bits[1] & |reset_unlock_r) begin
snescmd_unlock_r <= 1;
// clear unlock countdown if we are entering the snescmd region. this is to avoid a prior snescmd lock countdown re-locking before we are done
snescmd_unlock_disable <= 0;
snescmd_unlock_disable_countdown <= 0;
end
end
end
// give some time to exit snescmd memory and jump to original vector
if(SNES_cycle_start) begin
else if(SNES_cycle_start) begin
if(snescmd_unlock_disable) begin
if(|snescmd_unlock_disable_countdown) begin
snescmd_unlock_disable_countdown <= snescmd_unlock_disable_countdown - 1;
@@ -219,7 +228,7 @@ always @(posedge clk) begin
end
end
end
if(snescmd_unlock_disable_strobe) begin
else if(snescmd_unlock_disable_strobe) begin
snescmd_unlock_disable_countdown <= 7'd72;
snescmd_unlock_disable <= 1;
end
@@ -269,7 +278,7 @@ end
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd960000000;
hook_enable_count <= 30'd960000000; // FIXME: adjust for different frequency
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
@@ -447,11 +447,11 @@ reg [3:0] lat_mult_r;
always @(posedge CLK) begin
// pipeline latencies for multi-cycle operations. starfox is the only game that
// doesn't set CLS.
lat_fetch_r <= SPEED ? 0 : CLSR_CLS ? 0 : 1;
lat_rom_r <= SPEED ? 2 : CLSR_CLS ? 5-2 : 6-2;
lat_ram_r <= SPEED ? 1 : CLSR_CLS ? 5 : 6-3;
lat_fmult_r <= SPEED ? 2 : CLSR_CLS ? (CFGR_MS0 ? 3 : 7) : (CFGR_MS0 ? 6 : 14); // minimum 2
lat_mult_r <= SPEED ? 0 : CLSR_CLS ? (CFGR_MS0 ? 0 : 1) : (CFGR_MS0 ? 0 : 2);
lat_fetch_r <= SPEED ? 0 : CLSR_CLS ? 0 : 1;
lat_rom_r <= SPEED ? 2 : CLSR_CLS ? 5-1 : 6-2;
lat_ram_r <= SPEED ? 1 : CLSR_CLS ? 5-1 : 6-3;
lat_fmult_r <= SPEED ? 2 : CLSR_CLS ? (CFGR_MS0 ? 7 : 7) : (CFGR_MS0 ? 7 : 14-6); // minimum 2. starfox2 uses slow ms0 for some reason...
lat_mult_r <= SPEED ? 0 : CLSR_CLS ? (CFGR_MS0 ? 0 : 1) : (CFGR_MS0 ? 0 : 2-0);
end
//-------------------------------------------------------------------
@@ -558,13 +558,15 @@ gsu_cache cache (
.wea(cache_wren), // input [0 : 0] wea
.addra(cache_addr), // input [8 : 0] addra
.dina(cache_wrdata), // input [7 : 0] dina
.douta(cache_rddata), // output [7 : 0] douta
.douta(cache_rddata) // output [7 : 0] douta
`ifdef CACHE_DEBUG_PORT
,
.clkb(CLK), // input clkb
.web(debug_cache_wren), // input [0 : 0] web
.addrb(debug_cache_addr), // input [8 : 0] addrb
.dinb(debug_cache_wrdata), // input [7 : 0] dinb
.doutb(debug_cache_rddata) // output [7 : 0] doutb
`endif
);
//-------------------------------------------------------------------
@@ -1952,6 +1954,9 @@ always @(posedge CLK) begin
e2r_g_r <= 0;
// mask interrupt write into SFR
e2r_irq_r <= ~CFGR_IRQ;
// clear POR
//e2r_wpor_r <= 1;
//e2r_por_r <= 0;
end
//OP_NOP : begin end
`OP_CACHE : begin
@@ -41,24 +41,14 @@ module gsu_cache(
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
douta
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [8 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
@@ -70,7 +60,7 @@ output [7 : 0] doutb;
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
@@ -96,7 +86,7 @@ output [7 : 0] doutb;
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
@@ -131,17 +121,17 @@ output [7 : 0] doutb;
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Mar 28 11:04:18 2018
# Date: Tue May 01 15:48:03 2018
#
##############################################################
#
@@ -41,7 +41,7 @@ SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
@@ -61,7 +61,7 @@ CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET memory_type=Single_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
@@ -70,9 +70,9 @@ CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET port_b_clock=0
CSET port_b_enable_rate=0
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
@@ -105,4 +105,4 @@ CSET write_width_b=8
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 9b093993
# CRC: 3c3e5a1
@@ -52,8 +52,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="gsu_cache" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-03-28T04:04:56" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8726621958994C0B811F8E3E987E0BD4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-04-26T04:55:59" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="222E3EC560DB496AB27A4F0F199C58BE" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
Oops, something went wrong.

0 comments on commit 4d033bf

Please sign in to comment.