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Update plethora of generated Xilinx files...

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mrehkopf committed Feb 28, 2019
1 parent fed4deb commit 6cccbe9ac71ab214618d3956d9a66383179586c7
Showing with 338 additions and 337 deletions.
  1. +1 −1 verilog/sd2snes/ipcore_dir/dac_buf.v
  2. +1 −1 verilog/sd2snes/ipcore_dir/dac_buf.xco
  3. +2 −2 verilog/sd2snes/ipcore_dir/dac_buf.xise
  4. +1 −1 verilog/sd2snes/ipcore_dir/msu_databuf.v
  5. +1 −1 verilog/sd2snes/ipcore_dir/msu_databuf.xco
  6. +2 −2 verilog/sd2snes/ipcore_dir/msu_databuf.xise
  7. +1 −1 verilog/sd2snes/ipcore_dir/snescmd_buf.v
  8. +1 −1 verilog/sd2snes/ipcore_dir/snescmd_buf.xco
  9. +2 −2 verilog/sd2snes/ipcore_dir/snescmd_buf.xise
  10. +1 −1 verilog/sd2snes/ipcore_dir/upd77c25_datram.v
  11. +1 −1 verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
  12. +2 −2 verilog/sd2snes/ipcore_dir/upd77c25_datram.xise
  13. +1 −1 verilog/sd2snes/ipcore_dir/upd77c25_datrom.v
  14. +1 −1 verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco
  15. +2 −2 verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise
  16. +1 −1 verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v
  17. +1 −1 verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco
  18. +2 −2 verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xise
  19. +3 −2 verilog/sd2snes/sd2snes.xise
  20. +2 −2 verilog/sd2snes_cx4/sd2snes_cx4.xise
  21. +1 −1 verilog/sd2snes_gsu/ipcore_dir/dac_buf.xco
  22. +2 −2 verilog/sd2snes_gsu/ipcore_dir/dac_buf.xise
  23. +1 −1 verilog/sd2snes_gsu/ipcore_dir/gsu_cache.xco
  24. +5 −5 verilog/sd2snes_gsu/ipcore_dir/gsu_fmult.v
  25. +1 −1 verilog/sd2snes_gsu/ipcore_dir/gsu_fmult.xco
  26. +5 −5 verilog/sd2snes_gsu/ipcore_dir/gsu_mult.v
  27. +1 −1 verilog/sd2snes_gsu/ipcore_dir/gsu_mult.xco
  28. +5 −5 verilog/sd2snes_gsu/ipcore_dir/gsu_umult.v
  29. +1 −1 verilog/sd2snes_gsu/ipcore_dir/gsu_umult.xco
  30. +1 −1 verilog/sd2snes_gsu/ipcore_dir/msu_databuf.xco
  31. +2 −2 verilog/sd2snes_gsu/ipcore_dir/msu_databuf.xise
  32. +1 −1 verilog/sd2snes_gsu/ipcore_dir/snescmd_buf.xco
  33. +1 −1 verilog/sd2snes_gsu/ipcore_dir/upd77c25_datram.v
  34. +1 −1 verilog/sd2snes_gsu/ipcore_dir/upd77c25_datram.xco
  35. +2 −2 verilog/sd2snes_gsu/ipcore_dir/upd77c25_datram.xise
  36. +1 −1 verilog/sd2snes_gsu/ipcore_dir/upd77c25_datrom.v
  37. +1 −1 verilog/sd2snes_gsu/ipcore_dir/upd77c25_datrom.xco
  38. +2 −2 verilog/sd2snes_gsu/ipcore_dir/upd77c25_datrom.xise
  39. +1 −1 verilog/sd2snes_gsu/ipcore_dir/upd77c25_pgmrom.v
  40. +1 −1 verilog/sd2snes_gsu/ipcore_dir/upd77c25_pgmrom.xco
  41. +2 −2 verilog/sd2snes_gsu/ipcore_dir/upd77c25_pgmrom.xise
  42. +1 −1 verilog/sd2snes_sa1/ipcore_dir/dbg_state.xco
  43. +255 −255 verilog/sd2snes_sa1/ipcore_dir/dec_table.mif
  44. +2 −2 verilog/sd2snes_sa1/ipcore_dir/dec_table.xco
  45. +2 −2 verilog/sd2snes_sa1/ipcore_dir/sa1_div.v
  46. +1 −1 verilog/sd2snes_sa1/ipcore_dir/sa1_div.xco
  47. +1 −1 verilog/sd2snes_sa1/ipcore_dir/sa1_iram.xco
  48. +5 −5 verilog/sd2snes_sa1/ipcore_dir/sa1_mult.v
  49. +1 −1 verilog/sd2snes_sa1/ipcore_dir/sa1_mult.xco
  50. +1 −1 verilog/sd2snes_sa1/ipcore_dir/snescmd_buf.xco
  51. +2 −2 verilog/sd2snes_sa1/sd2snes.xise
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Apr 18 23:03:01 2016
# Date: Sun Aug 12 11:06:59 2018
#
##############################################################
#
@@ -366,8 +366,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-04-19T01:04:00" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0EC66BE8FABE4E0DB881BCADED566709" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-12T13:07:57" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="63662EB410CB4F1188A32166A7C2A75D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 10 07:56:42 2016
# Date: Sun Aug 12 11:08:07 2018
#
##############################################################
#
@@ -366,8 +366,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-10T08:58:01" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A383E0F9E71B4E53A8B51E4454A14D51" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-12T13:09:13" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AF09BFE2E40A4CC5A3770D35C19C539F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file snescmd_buf.v when simulating
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 10 07:52:27 2016
# Date: Sun Aug 12 11:09:22 2018
#
##############################################################
#
@@ -52,8 +52,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="snescmd_buf" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-10T08:53:36" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5E87EAD004A145B593ED7E41A8E8D636" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-12T13:10:19" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2430E776D87F400393D50C11C073F746" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datram.v when simulating
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 10 08:04:07 2016
# Date: Sun Aug 12 11:03:26 2018
#
##############################################################
#
@@ -366,8 +366,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-10T09:05:15" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2ACEEF5B476947749FBB4632630FA688" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-12T13:04:27" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF12BD10EBCF4A57A0A3E651785733F7" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datrom.v when simulating
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 10 08:01:54 2016
# Date: Sun Aug 12 11:04:38 2018
#
##############################################################
#
@@ -366,8 +366,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-10T09:03:02" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="31921FE65E03472D9D7E87B4F045E8F8" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-12T13:05:38" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1EDBC969BF3D4A89BD8444749E9E958F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_pgmrom.v when simulating
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 10 07:58:54 2016
# Date: Sun Aug 12 11:05:49 2018
#
##############################################################
#
@@ -366,8 +366,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-10T09:00:09" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="97E0E19E1D714772AD8CABCF0903C235" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-12T13:06:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C85C6B5A7672462991266C2252888346" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -388,8 +388,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -471,6 +471,7 @@
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="config.vh" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>

</project>
@@ -362,8 +362,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="13" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="13" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sat Feb 17 16:25:02 2018
# Date: Wed Jun 06 23:08:02 2018
#
##############################################################
#
@@ -366,8 +366,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-02-17T08:25:44" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C25D1C68B11412EA625B54E06E77C5F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-06-07T01:09:05" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0B120F24368248A3A58C4771FD76DFE9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Tue May 01 15:48:03 2018
# Date: Wed Jun 06 23:11:38 2018
#
##############################################################
#
@@ -7,17 +7,17 @@
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_fmult.v
// /___/ /\ Timestamp: Sat Mar 31 13:59:30 2018
// /___/ /\ Timestamp: Thu Jun 07 01:15:08 2018
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.ngc C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.v
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.v
// Device : 3s400pq208-4
// Input file : C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.ngc
// Output file : C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.v
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_fmult.v
// # of Modules : 1
// Design Name : gsu_fmult
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
// Xilinx : E:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sat Mar 31 20:58:59 2018
# Date: Wed Jun 06 23:14:28 2018
#
##############################################################
#
@@ -7,17 +7,17 @@
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_mult.v
// /___/ /\ Timestamp: Sun Apr 22 08:48:28 2018
// /___/ /\ Timestamp: Thu Jun 07 01:14:16 2018
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.ngc C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.v
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.v
// Device : 3s400pq208-4
// Input file : C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.ngc
// Output file : C:/Users/O/dev/sd2snes-gsu/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.v
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_mult.v
// # of Modules : 1
// Design Name : gsu_mult
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
// Xilinx : E:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sun Apr 22 15:47:57 2018
# Date: Wed Jun 06 23:13:35 2018
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