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Merge pull request #112 from RedGuyyyy/sa1b

- SA1 (RedGuyyyy)
- PPU phase alignment in reset hook, including menu item to disable (ikari+RedGuyyyy)
- Selective SRAM checking ranges for games that use SRAM as work RAM (RedGuyyyy)
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mrehkopf committed Oct 2, 2018
2 parents 24245f4 + d4f49ac commit 6fc41ede2deabdfe3a67dce69257a3db4cf84756
Showing with 23,279 additions and 28 deletions.
  1. +2 −0 snes/const.a65
  2. +1 −0 snes/memmap.i65
  3. +14 −0 snes/menudata.a65
  4. +10 −5 snes/nmihook.a65
  5. +6 −1 src/cfg.c
  6. +2 −0 src/cfg.h
  7. +3 −2 src/config
  8. +1 −0 src/fpga.h
  9. +3 −0 src/main.c
  10. +25 −5 src/memory.c
  11. +1 −0 src/memory.h
  12. +4 −0 src/msu1.c
  13. +19 −7 src/smc.c
  14. +2 −1 src/smc.h
  15. +106 −7 src/snes.c
  16. +5 −0 src/snes.h
  17. +126 −0 verilog/sd2snes_sa1/address.v
  18. +281 −0 verilog/sd2snes_sa1/bsx.v
  19. +418 −0 verilog/sd2snes_sa1/cheat.v
  20. +52 −0 verilog/sd2snes_sa1/clk_test.v
  21. +284 −0 verilog/sd2snes_sa1/dac.v
  22. +76 −0 verilog/sd2snes_sa1/dcm.v
  23. +306 −0 verilog/sd2snes_sa1/decoder.py
  24. +256 −0 verilog/sd2snes_sa1/ipcore_dir/blk_mem_gen_v7_3.mif
  25. +176 −0 verilog/sd2snes_sa1/ipcore_dir/blk_mem_gen_v7_3.v
  26. +108 −0 verilog/sd2snes_sa1/ipcore_dir/blk_mem_gen_v7_3.xco
  27. +388 −0 verilog/sd2snes_sa1/ipcore_dir/blk_mem_gen_v7_3.xise
  28. +184 −0 verilog/sd2snes_sa1/ipcore_dir/dac_buf.v
  29. +108 −0 verilog/sd2snes_sa1/ipcore_dir/dac_buf.xco
  30. +388 −0 verilog/sd2snes_sa1/ipcore_dir/dac_buf.xise
  31. +184 −0 verilog/sd2snes_sa1/ipcore_dir/dbg_state.v
  32. +108 −0 verilog/sd2snes_sa1/ipcore_dir/dbg_state.xco
  33. +74 −0 verilog/sd2snes_sa1/ipcore_dir/dbg_state.xise
  34. +261 −0 verilog/sd2snes_sa1/ipcore_dir/dec_table.coe
  35. +256 −0 verilog/sd2snes_sa1/ipcore_dir/dec_table.mif
  36. +176 −0 verilog/sd2snes_sa1/ipcore_dir/dec_table.v
  37. +108 −0 verilog/sd2snes_sa1/ipcore_dir/dec_table.xco
  38. +74 −0 verilog/sd2snes_sa1/ipcore_dir/dec_table.xise
  39. +184 −0 verilog/sd2snes_sa1/ipcore_dir/msu_databuf.v
  40. +108 −0 verilog/sd2snes_sa1/ipcore_dir/msu_databuf.xco
  41. +388 −0 verilog/sd2snes_sa1/ipcore_dir/msu_databuf.xise
  42. +5,817 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_div.v
  43. +61 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_div.xco
  44. +74 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_div.xise
  45. +190 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_iram.v
  46. +108 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_iram.xco
  47. +74 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_iram.xise
  48. +395 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_mult.v
  49. +68 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_mult.xco
  50. +74 −0 verilog/sd2snes_sa1/ipcore_dir/sa1_mult.xise
  51. +190 −0 verilog/sd2snes_sa1/ipcore_dir/snescmd_buf.v
  52. +108 −0 verilog/sd2snes_sa1/ipcore_dir/snescmd_buf.xco
  53. +74 −0 verilog/sd2snes_sa1/ipcore_dir/snescmd_buf.xise
  54. +190 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_datram.v
  55. +108 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_datram.xco
  56. +388 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_datram.xise
  57. +184 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_datrom.v
  58. +108 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_datrom.xco
  59. +388 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_datrom.xise
  60. +184 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_pgmrom.v
  61. +108 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_pgmrom.xco
  62. +388 −0 verilog/sd2snes_sa1/ipcore_dir/upd77c25_pgmrom.xise
  63. +637 −0 verilog/sd2snes_sa1/main.ucf
  64. +1,218 −0 verilog/sd2snes_sa1/main.v
  65. +151 −0 verilog/sd2snes_sa1/main_tf.v
  66. +575 −0 verilog/sd2snes_sa1/mcu_cmd.v
  67. +210 −0 verilog/sd2snes_sa1/msu.v
  68. +257 −0 verilog/sd2snes_sa1/optable.txt
  69. +392 −0 verilog/sd2snes_sa1/rtc.v
  70. +3,529 −0 verilog/sd2snes_sa1/sa1.v
  71. +500 −0 verilog/sd2snes_sa1/sd2snes.xise
  72. +155 −0 verilog/sd2snes_sa1/sd_dma.v
  73. +127 −0 verilog/sd2snes_sa1/spi.v
  74. +185 −0 verilog/sd2snes_sa1/srtc.v
  75. +638 −0 verilog/sd2snes_sa1/upd77c25.v
  76. +150 −0 verilog/sd2snes_sa1/updtest_tf.v
View
@@ -214,6 +214,7 @@ mtext_ingame_holdoff .byt " ",129,"Initial holdoff", 0
mtext_ingame_regionpatch .byt "Auto region patch", 0
mtext_ingame_1chiptransientfixes .byt "1CHIP transient fixes", 0
mtext_ingame_brightlimit .byt "Brightness limit", 0
mtext_ingame_resetpatch .byt "Reset patch for clock phase", 0
mtext_chip_cx4_speed .byt "Cx4 speed", 0
mtext_chip_gsu_speed .byt "SuperFX speed", 0
mtext_chip_msu1_volume_boost .byt "MSU-1 volume boost", 0
@@ -245,6 +246,7 @@ mdesc_ingame_holdoff .byt "Wait 10 seconds before enabling hook (he
mdesc_ingame_regionpatch .byt "Bypass simple region protection by games", 0
mdesc_ingame_1chiptransientfixes .byt "Patch brightness changes to fix sync glitches, fading scanlines and missing shadow on 1CHIP/Jr. consoles", 0
mdesc_ingame_brightlimit .byt "Limit overall brightness (e.g. on 1CHIP consoles to meet RGB line levels)", 0
mdesc_ingame_resetpatch .byt "Enable reset patch to align clocks. Fixes graphical issues in some games", 0
mdesc_chip_cx4_speed .byt "Set speed of Cx4 soft core", 0
mdesc_chip_gsu_speed .byt "Set speed of SuperFX soft core", 0
mdesc_chip_msu1_volume_boost .byt "Set volume boost for MSU1 audio if your sd2snes is too quiet (Rev. E-G)", 0
View
@@ -104,6 +104,7 @@
#define CFG_ENABLE_RST_TO_MENU CFG_ADDR+$009F
#define CFG_LED_BRIGHTNESS CFG_ADDR+$00A0
#define CFG_ENABLE_CHEATS CFG_ADDR+$00A1
#define CFG_RESET_PATCH CFG_ADDR+$00A2
#define MENU_ENTRY_SIZE 23
View
@@ -475,6 +475,20 @@ menu_enttab_ingame:
.byt ^(mfunc_chg_brightness-1)
.byt 0,0,0
.byt 0,0,0
.byt MTYPE_VALUE
.word !mtext_ingame_resetpatch
.byt ^mtext_ingame_resetpatch
.word !kv_onoff
.byt ^kv_onoff
.byt OPTTYPE_KVBYTE
.word !CFG_RESET_PATCH
.byt ^CFG_RESET_PATCH
.word !mdesc_ingame_resetpatch
.byt ^mdesc_ingame_resetpatch
.byt 0,0,0
.byt 0,0,0
.byt 0,0,0
.byt 0
View
@@ -86,7 +86,7 @@ nmi_stop:
resethook: ; EMULATION MODE
.as : .xs
bra resethook_skip
; mask interrupt handler call
sei
; x stores the count of scanlines
@@ -120,16 +120,21 @@ resethook: ; EMULATION MODE
bne -
; stop interrupts and check if we have any errors
stz $4200
dex
stx $4207
dey
bmi +
; perform reset
lda #$80
lda #$85
sta @MCU_CMD
- bra -
; clean up state
+ dex
stx $4207
+ inx
iny
resethook_skip:
lda #$86
sta @MCU_CMD
resethook_loop:
- lda $4212
bpl -
View
@@ -32,7 +32,8 @@ cfg_t CFG_DEFAULT = {
.brightness_limit = 15,
.gsu_speed = 0,
.reset_to_menu = 0,
.led_brightness = 15
.led_brightness = 15,
.reset_patch = 0,
};
cfg_t CFG;
@@ -72,6 +73,7 @@ int cfg_save() {
f_printf(&file_handle, "%s: %s\n", CFG_ENABLE_INGAME_HOOK, CFG.enable_ingame_hook ? "true" : "false");
f_printf(&file_handle, "%s: %s\n", CFG_ENABLE_INGAME_BUTTONS, CFG.enable_ingame_buttons ? "true" : "false");
f_printf(&file_handle, "%s: %s\n", CFG_ENABLE_HOOK_HOLDOFF, CFG.enable_hook_holdoff ? "true" : "false");
f_printf(&file_handle, "%s: %s\n", CFG_RESET_PATCH, CFG.reset_patch ? "true" : "false");
f_puts("\n# Screensaver settings\n", &file_handle);
f_printf(&file_handle, "# %s: Enable screensaver\n", CFG_ENABLE_SCREENSAVER);
// f_printf(&file_handle, "# %s: Dim screen after n seconds\n", CFG_SCREENSAVER_TIMEOUT);
@@ -170,6 +172,9 @@ int cfg_load() {
if(yaml_get_itemvalue(CFG_ENABLE_CHEATS, &tok)) {
CFG.enable_cheats = tok.boolvalue ? 1 : 0;
}
if(yaml_get_itemvalue(CFG_RESET_PATCH, &tok)) {
CFG.reset_patch = tok.boolvalue ? 1 : 0;
}
}
yaml_file_close();
return err;
View
@@ -30,6 +30,7 @@
#define CFG_ENABLE_RST_TO_MENU ("ShortReset2Menu")
#define CFG_LED_BRIGHTNESS ("LEDBrightness")
#define CFG_ENABLE_CHEATS ("EnableCheats")
#define CFG_RESET_PATCH ("ResetPatch")
typedef enum {
VIDMODE_60 = 0,
@@ -61,6 +62,7 @@ typedef struct __attribute__ ((__packed__)) _cfg_block {
uint8_t reset_to_menu; /* Go back to menu on short reset */
uint8_t led_brightness; /* LED brightness (0..15) */
uint8_t enable_cheats; /* initial cheat enable state */
uint8_t reset_patch; /* enable reset patch */
} cfg_t;
int cfg_save(void);
View
@@ -1,3 +1,4 @@
CONFIG_VERSION="1.8.0-reset"
CONFIG_FWVER=0x11080000
CONFIG_VERSION="1.8.0-sa1-v07"
CONFIG_FWVER=0xFEFFFFE9
#CONFIG_FWVER=0x44534E53
CONFIG_MCU_FOSC=12000000
View
@@ -46,6 +46,7 @@ const uint8_t *fpga_config;
#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4.bit")
#define FPGA_OBC1 ((const uint8_t*)"/sd2snes/fpga_obc1.bit")
#define FPGA_GSU ((const uint8_t*)"/sd2snes/fpga_gsu.bit")
#define FPGA_SA1 ((const uint8_t*)"/sd2snes/fpga_sa1.bit")
#define FPGA_BASE ((const uint8_t*)"/sd2snes/fpga_base.bit")
#define FPGA_ROM ((const uint8_t*)"rom")
View
@@ -366,6 +366,9 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
cmd=snes_main_loop();
if(cmd) {
switch(cmd) {
case SNES_CMD_RESET_LOOP_FAIL:
snes_reset_loop();
break;
case SNES_CMD_RESET:
snes_reset_pulse();
break;
View
@@ -54,6 +54,8 @@ char* hex = "0123456789ABCDEF";
extern snes_romprops_t romprops;
extern uint32_t saveram_crc_old;
extern uint8_t sram_crc_valid;
extern uint32_t sram_crc_romsize;
extern cfg_t CFG;
extern status_t ST;
@@ -271,7 +273,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
uart_putc('.');
}
}
uart_putc('\n');
file_close();
printf("rom header map: %02x; mapper id: %d\n", romprops.header.map, romprops.mapper_id);
ticks_total=getticks()-ticksstart;
printf("%u ticks total\n", ticks_total);
@@ -318,7 +322,15 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
romprops.romsize_bytes <<= 1;
}
if(romprops.header.ramsize == 0) {
if (romprops.has_sa1 && romprops.header.carttype == 0x36 && romprops.header.ramsize) {
// move iram into saveram for special carts with no bwram
romprops.header.ramsize = 1;
romprops.ramsize_bytes = 0x800;
// override any changes to this so we capture full sram
romprops.srambase = 0;
romprops.sramsize_bytes = romprops.ramsize_bytes;
rammask = 1;
} else if(romprops.header.ramsize == 0) {
rammask = 0;
} else {
rammask = romprops.ramsize_bytes - 1;
@@ -329,15 +341,15 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
set_rom_mask(rommask);
readled(0);
printf("gsu=%x gsu_sram=%x\n", romprops.has_gsu, romprops.has_gsu_sram);
printf("gsu=%x sa1=%x srambase=%lx sramsize=%lx\n", romprops.has_gsu, romprops.has_sa1, romprops.srambase, romprops.sramsize_bytes);
if(flags & LOADROM_WITH_SRAM) {
if(romprops.ramsize_bytes) {
// powerslide relies on the init value to be 00.
sram_memset(SRAM_SAVE_ADDR, romprops.ramsize_bytes, romprops.has_gsu ? 0x00 : 0xFF);
if (!romprops.has_gsu || romprops.has_gsu_sram) migrate_and_load_srm(filename, SRAM_SAVE_ADDR);
if (romprops.sramsize_bytes) migrate_and_load_srm(filename, SRAM_SAVE_ADDR);
/* file not found error is ok (SRM file might not exist yet) */
if(file_res == FR_NO_FILE) file_res = 0;
saveram_crc_old = calc_sram_crc(SRAM_SAVE_ADDR, romprops.ramsize_bytes);
saveram_crc_old = calc_sram_crc(SRAM_SAVE_ADDR + romprops.srambase, romprops.sramsize_bytes);
} else {
printf("No SRAM\n");
}
@@ -398,13 +410,22 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
delay_ms(SNES_RESET_PULSELEN_MS);
}
snescmd_prepare_nmihook();
if (CFG.reset_patch) snescmd_writebyte(0, SNESCMD_RESET_HOOK+1);
cheat_yaml_load(filename);
// XXX cheat_yaml_save(filename);
cheat_program();
fpga_set_features(romprops.fpga_features);
snes_set_mcu_cmd(0);
snes_reset(0);
fpga_dspx_reset(0);
// handle reset loop from hook
snes_reset_loop();
}
// loading a new rom implies the previous crc is no longer valid
sram_crc_valid = 0;
sram_crc_romsize = filesize - romprops.offset;
return (uint32_t)filesize;
}
@@ -634,7 +655,6 @@ void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
file_close();
}
uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
uint8_t data;
uint32_t count;
View
@@ -88,6 +88,7 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size);
void save_srm(uint8_t* filename, uint32_t sram_size, uint32_t base_addr);
void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr);
uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size);
uint16_t calc_sram_sum(uint32_t base_addr, uint32_t size);
uint8_t sram_reliable(void);
void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val);
View
@@ -179,6 +179,10 @@ int msu1_loop() {
cmd = snes_get_mcu_cmd();
if(cmd) {
switch(cmd) {
case SNES_CMD_RESET_LOOP_FAIL:
msu_res = SNES_RESET_SHORT;
snes_reset_loop();
break;
case SNES_CMD_RESET:
msu_res = SNES_RESET_SHORT;
snes_reset_pulse();
View
@@ -71,7 +71,9 @@ void smc_id(snes_romprops_t* props) {
props->has_cx4 = 0;
props->has_obc1 = 0;
props->has_gsu = 0;
props->has_gsu_sram = 0;
props->has_sa1 = 0;
props->srambase = 0;
props->sramsize_bytes = 0;
props->fpga_features = 0;
props->fpga_dspfeat = 0;
props->fpga_conf = NULL;
@@ -100,8 +102,9 @@ void smc_id(snes_romprops_t* props) {
if(header->licensee == 0x33 || header->licensee == 0xff) {
props->mapper_id = 0;
/*XXX do this properly */
props->ramsize_bytes = 0x8000;
props->romsize_bytes = 0x100000;
props->ramsize_bytes = 0x8000;
props->sramsize_bytes = props->ramsize_bytes;
props->romsize_bytes = 0x100000;
props->expramsize_bytes = 0;
props->mapper_id = 3; /* BS-X Memory Map */
props->region = 0; /* BS-X only existed in Japan */
@@ -189,7 +192,6 @@ void smc_id(snes_romprops_t* props) {
else if (header->map == 0x20 && ((header->carttype >= 0x13 && header->carttype <= 0x15) ||
header->carttype == 0x1a)) {
props->has_gsu = 1;
props->has_gsu_sram = (header->carttype == 0x15 || header->carttype == 0x1a) ? 1 : 0;
props->fpga_conf = FPGA_GSU;
props->fpga_dspfeat = CFG.gsu_speed;
header->ramsize = header->expramsize & 0x7;
@@ -224,10 +226,9 @@ void smc_id(snes_romprops_t* props) {
break;
case 0x23: /* SA1 */
if(header->carttype == 0x32 || header->carttype == 0x34 || header->carttype == 0x35) {
if(header->carttype == 0x32 || header->carttype == 0x34 || header->carttype == 0x35 || header->carttype == 0x36) {
props->has_sa1 = 1;
props->error = MENU_ERR_NOIMPL;
props->error_param = (uint8_t*)"SA-1";
props->fpga_conf = FPGA_SA1;
}
break;
@@ -286,6 +287,17 @@ void smc_id(snes_romprops_t* props) {
}
props->region = (header->destcode <= 1 || header->destcode >= 13) ? 0 : 1;
// adjust sram size for special cart types
if ( (props->has_gsu && (header->carttype != 0x15 && header->carttype != 0x1a))
|| (props->has_sa1 && (header->carttype == 0x34) )
) {
// no sram in ram
props->sramsize_bytes = 0;
}
else {
props->sramsize_bytes = props->ramsize_bytes;
}
if(header->carttype == 0x55) {
props->fpga_features |= FEAT_SRTC;
}
View
@@ -84,10 +84,11 @@ typedef struct __attribute__ ((__packed__)) _snes_romprops {
uint8_t has_cx4; /* CX4 presence flag */
uint8_t has_obc1; /* OBC1 presence flag */
uint8_t has_gsu; /* GSU presence flag */
uint8_t has_gsu_sram; /* GSU saveram presence flag */
uint8_t has_sa1; /* SA-1 presence flag */
uint8_t has_sdd1; /* S-DD1 presence flag */
uint8_t has_spc7110; /* SPC7110 presence flag */
uint32_t srambase; /* saveram base address */
uint32_t sramsize_bytes; /* saveram size in bytes */
uint16_t fpga_features; /* feature/peripheral enable bits */
uint16_t fpga_dspfeat; /* DSP configuration bits */
uint8_t region; /* game region (derived from destination code) */
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