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MCU command interface: Some state simplifications

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mrehkopf committed Apr 30, 2017
1 parent ff8b0a5 commit 71c2824ccdc99ce9bb9c597d4b8bd1794546604e
Showing with 48 additions and 174 deletions.
  1. +13 −44 verilog/sd2snes/mcu_cmd.v
  2. +13 −44 verilog/sd2snes_cx4/mcu_cmd.v
  3. +12 −44 verilog/sd2snes_obc1/mcu_cmd.v
  4. +10 −42 verilog/sd2sneslite/mcu_cmd.v
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@@ -25,9 +25,9 @@ module mcu_cmd(
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
- output mcu_rrq,
+ output reg mcu_rrq = 0,
output mcu_write,
- output mcu_wrq,
+ output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
@@ -143,7 +143,7 @@ reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
-reg msu_status_reset_we_buf;
+reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [7:0] bsx_regs_set_out_buf;
@@ -208,6 +208,8 @@ always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
+ MSU_RESET_OUT_BUF <= 1'b0;
+
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
@@ -330,8 +332,6 @@ always @(posedge clk) begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
- 32'h4:
- MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'he5:
case (spi_byte_cnt)
@@ -534,54 +534,23 @@ always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
-parameter ST_RQ = 2'b01;
-parameter ST_IDLE = 2'b10;
-
-reg [1:0] rrq_state;
-initial rrq_state = ST_IDLE;
-reg mcu_rrq_r;
-
-reg [1:0] wrq_state;
-initial wrq_state = ST_IDLE;
-reg mcu_wrq_r;
-
always @(posedge clk) begin
- case(rrq_state)
- ST_IDLE: begin
- if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
- mcu_rrq_r <= 1'b1;
- rrq_state <= ST_RQ;
- end else
- rrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_rrq_r <= 1'b0;
- rrq_state <= ST_IDLE;
- end
- endcase
+ mcu_rrq <= 1'b0;
+ if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
+ mcu_rrq <= 1'b1;
+ end
end
always @(posedge clk) begin
- case(wrq_state)
- ST_IDLE: begin
- if(param_ready && cmd_data[7:4] == 4'h9) begin
- mcu_wrq_r <= 1'b1;
- wrq_state <= ST_RQ;
- end else
- wrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_wrq_r <= 1'b0;
- wrq_state <= ST_IDLE;
- end
- endcase
+ mcu_wrq <= 1'b0;
+ if(param_ready && cmd_data[7:4] == 4'h9) begin
+ mcu_wrq <= 1'b1;
+ end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
-assign mcu_rrq = mcu_rrq_r;
-assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
@@ -25,9 +25,9 @@ module mcu_cmd(
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
- output mcu_rrq,
+ output reg mcu_rrq = 0,
output mcu_write,
- output mcu_wrq,
+ output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
@@ -122,7 +122,7 @@ reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
-reg msu_status_reset_we_buf;
+reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
@@ -176,6 +176,8 @@ always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
+ MSU_RESET_OUT_BUF <= 1'b0;
+
if (cmd_ready) begin
case (cmd_data[7:4])
4'h4: begin// SD DMA
@@ -296,8 +298,6 @@ always @(posedge clk) begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
- 32'h4:
- MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'heb: // put cx4 into reset
cx4_reset_out <= param_data[0];
@@ -429,54 +429,23 @@ always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
-parameter ST_RQ = 2'b01;
-parameter ST_IDLE = 2'b10;
-
-reg [1:0] rrq_state;
-initial rrq_state = ST_IDLE;
-reg mcu_rrq_r;
-
-reg [1:0] wrq_state;
-initial wrq_state = ST_IDLE;
-reg mcu_wrq_r;
-
always @(posedge clk) begin
- case(rrq_state)
- ST_IDLE: begin
- if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
- mcu_rrq_r <= 1'b1;
- rrq_state <= ST_RQ;
- end else
- rrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_rrq_r <= 1'b0;
- rrq_state <= ST_IDLE;
- end
- endcase
+ mcu_rrq <= 1'b0;
+ if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
+ mcu_rrq <= 1'b1;
+ end
end
always @(posedge clk) begin
- case(wrq_state)
- ST_IDLE: begin
- if(param_ready && cmd_data[7:4] == 4'h9) begin
- mcu_wrq_r <= 1'b1;
- wrq_state <= ST_RQ;
- end else
- wrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_wrq_r <= 1'b0;
- wrq_state <= ST_IDLE;
- end
- endcase
+ mcu_wrq <= 1'b0;
+ if(param_ready && cmd_data[7:4] == 4'h9) begin
+ mcu_wrq <= 1'b1;
+ end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
-assign mcu_rrq = mcu_rrq_r;
-assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
@@ -25,9 +25,9 @@ module mcu_cmd(
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
- output mcu_rrq,
+ output reg mcu_rrq = 0,
output mcu_write,
- output mcu_wrq,
+ output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
@@ -117,7 +117,7 @@ reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
-reg msu_status_reset_we_buf;
+reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
@@ -170,6 +170,7 @@ always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
+ MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
@@ -292,8 +293,6 @@ always @(posedge clk) begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
- 32'h4:
- MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'hec: // set DAC properties
begin
@@ -414,54 +413,23 @@ always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
-parameter ST_RQ = 2'b01;
-parameter ST_IDLE = 2'b10;
-
-reg [1:0] rrq_state;
-initial rrq_state = ST_IDLE;
-reg mcu_rrq_r;
-
-reg [1:0] wrq_state;
-initial wrq_state = ST_IDLE;
-reg mcu_wrq_r;
-
always @(posedge clk) begin
- case(rrq_state)
- ST_IDLE: begin
- if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
- mcu_rrq_r <= 1'b1;
- rrq_state <= ST_RQ;
- end else
- rrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_rrq_r <= 1'b0;
- rrq_state <= ST_IDLE;
- end
- endcase
+ mcu_rrq <= 1'b0;
+ if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
+ mcu_rrq <= 1'b1;
+ end
end
always @(posedge clk) begin
- case(wrq_state)
- ST_IDLE: begin
- if(param_ready && cmd_data[7:4] == 4'h9) begin
- mcu_wrq_r <= 1'b1;
- wrq_state <= ST_RQ;
- end else
- wrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_wrq_r <= 1'b0;
- wrq_state <= ST_IDLE;
- end
- endcase
+ mcu_wrq <= 1'b0;
+ if(param_ready && cmd_data[7:4] == 4'h9) begin
+ mcu_wrq <= 1'b1;
+ end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
-assign mcu_rrq = mcu_rrq_r;
-assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
? (SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
@@ -24,8 +24,8 @@ module mcu_cmd(
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
- output mcu_rrq,
- output mcu_wrq,
+ output reg mcu_rrq = 0,
+ output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
@@ -119,55 +119,23 @@ always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
-parameter ST_RQ = 2'b01;
-parameter ST_IDLE = 2'b10;
-
-reg [1:0] rrq_state;
-initial rrq_state = ST_IDLE;
-reg mcu_rrq_r;
-
-reg [1:0] wrq_state;
-initial wrq_state = ST_IDLE;
-reg mcu_wrq_r;
-
always @(posedge clk) begin
- case(rrq_state)
- ST_IDLE: begin
- if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
- mcu_rrq_r <= 1'b1;
- rrq_state <= ST_RQ;
- end else
- rrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_rrq_r <= 1'b0;
- rrq_state <= ST_IDLE;
- end
- endcase
+ mcu_rrq <= 1'b0;
+ if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
+ mcu_rrq <= 1'b1;
+ end
end
always @(posedge clk) begin
- case(wrq_state)
- ST_IDLE: begin
- if(param_ready && cmd_data[7:4] == 4'h9) begin
- mcu_wrq_r <= 1'b1;
- wrq_state <= ST_RQ;
- end else
- wrq_state <= ST_IDLE;
- end
- ST_RQ: begin
- mcu_wrq_r <= 1'b0;
- wrq_state <= ST_IDLE;
- end
- endcase
+ mcu_wrq <= 1'b0;
+ if(param_ready && cmd_data[7:4] == 4'h9) begin
+ mcu_wrq <= 1'b1;
+ end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
-assign mcu_rrq = mcu_rrq_r;
-assign mcu_wrq = mcu_wrq_r;
-
assign addr_out = ADDR_OUT_BUF;
assign mcu_data_out = MCU_DATA_OUT_BUF;

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