FPGA: apply recent changes to bootstrap config

mrehkopf · Sep 13, 2016 · 7ace919 · 7ace919
1 parent 76eea82
commit 7ace919
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Showing 2 changed files with 7 additions and 4 deletions.
diff --git a/verilog/sd2sneslite/main.ucf b/verilog/sd2sneslite/main.ucf
@@ -1,13 +1,13 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.05 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
 
 NET "p113_out" IOSTANDARD = LVCMOS33;
 NET "p113_out" LOC = P113;
 
 NET "SPI_SCK" LOC = P71;
 NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
 NET "SPI_SCK" TNM_NET = "SPI_SCK";
-TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 88.2MHz HIGH 50 %;
+TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48.1MHz HIGH 50 %;
 
 NET "SPI_SCK" IOSTANDARD = LVCMOS33;
 NET "SPI_SCK" DRIVE = 8;

diff --git a/verilog/sd2sneslite/main.v b/verilog/sd2sneslite/main.v
@@ -102,7 +102,7 @@ reg [7:0] SNES_PARDr;
 reg [7:0] SNES_READr;
 reg [7:0] SNES_WRITEr;
 reg [7:0] SNES_CPU_CLKr;
-reg [23:0] SNES_ADDRr [3:0];
+reg [23:0] SNES_ADDRr [5:0];
 
 reg SNES_DEADr = 1;
 reg SNES_reset_strobe = 0;
@@ -120,7 +120,8 @@ wire SNES_READ = SNES_READr[2] & SNES_READr[1];
 wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
 wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
 
-wire [23:0] SNES_ADDR = (SNES_ADDRr[3] & SNES_ADDRr[2]);
+wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
+
 wire free_slot = SNES_cycle_end | free_strobe;
 
 wire ROM_HIT;
@@ -137,6 +138,8 @@ always @(posedge CLK2) begin
   SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
   SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
   SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
+  SNES_ADDRr[5] <= SNES_ADDRr[4];
+  SNES_ADDRr[4] <= SNES_ADDRr[3];
   SNES_ADDRr[3] <= SNES_ADDRr[2];
   SNES_ADDRr[2] <= SNES_ADDRr[1];
   SNES_ADDRr[1] <= SNES_ADDRr[0];