FPGA: misc cleanup

mrehkopf · Jul 5, 2019 · ab41f61 · ab41f61
1 parent 899c813
commit ab41f61
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Showing 13 changed files with 125 additions and 131 deletions.
diff --git a/verilog/sd2snes_base/main.qsf b/verilog/sd2snes_base/main.qsf
@@ -525,7 +525,7 @@ set_global_assignment -name QIP_FILE msu_databuf.qip
 set_global_assignment -name QIP_FILE dac_buf.qip
 set_global_assignment -name SDC_FILE main.sdc
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
 set_location_assignment PIN_T5 -to PT5_in
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PT5_in
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to PT5_in

diff --git a/verilog/sd2snes_cx4/msu.v b/verilog/sd2snes_cx4/msu.v
@@ -142,7 +142,7 @@ assign reg_data_out = data_out_r;
 always @(posedge clkin) begin
   if(msu_address_ext_write_rising)
     msu_address_r <= msu_address_ext;
-  else if(reg_oe_falling & enable & (reg_addr == 3'h1)) begin
+  else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
     msu_address_r <= msu_address_r + 1;
   end
 end

diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise
diff --git a/verilog/sd2snes_cx4/spi.v b/verilog/sd2snes_cx4/spi.v
@@ -73,10 +73,10 @@ always @(posedge SCK) begin
 end
 
 always @(posedge SCK) begin
-  if(~SSELSCKr[1]) begin
+  if(~SSELSCKr[1])
     byte_data_received <= {byte_data_received[6:0], MOSI};
-  end
+  if(~SSELSCKr[1] && bitcnt==3'b111)
-  if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
+    byte_received <= 1'b1;
   else byte_received <= 1'b0;
 end
 
@@ -85,11 +85,10 @@ end
 //wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
 
 always @(posedge clk) begin
-  if(SSEL_inactive) begin
+  if(SSEL_inactive)
     byte_cnt_r <= 16'h0000;
-  end else if(byte_received_sync) begin
+  else if(byte_received_sync)
     byte_cnt_r <= byte_cnt_r + 16'h0001;
-  end
 end
 
 reg [7:0] byte_data_sent;

diff --git a/verilog/sd2snes_gsu/mcu_cmd.v b/verilog/sd2snes_gsu/mcu_cmd.v
@@ -115,15 +115,6 @@ initial begin
   SD_DMA_END_MID_BLOCK = 0;
 end
 
-wire [31:0] snes_sysclk_freq;
-
-clk_test snes_clk_test (
-    .clk(clk),
-    .sysclk(snes_sysclk),
-    .snes_sysclk_freq(snes_sysclk_freq)
-);
-
-
 reg [2:0] MAPPER_BUF;
 reg [23:0] ADDR_OUT_BUF;
 reg [10:0] DAC_ADDR_OUT_BUF;
@@ -149,7 +140,6 @@ reg reg_we_buf; initial reg_we_buf = 0;
 reg [55:0] rtc_data_out_buf;
 reg rtc_pgm_we_buf;
 
-reg [31:0] SNES_SYSCLK_FREQ_BUF;
 
 reg [7:0] MCU_DATA_OUT_BUF;
 reg [7:0] MCU_DATA_IN_BUF;
@@ -489,19 +479,6 @@ always @(posedge clk) begin
       MCU_DATA_IN_BUF <= msu_volumerq;
     else if (cmd_data[7:0] == 8'hF5)
       MCU_DATA_IN_BUF <= gsu_data;
-    else if (cmd_data[7:0] == 8'hFE)
-      case (spi_byte_cnt)
-        32'h1:
-          SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
-        32'h2:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
-        32'h3:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
-        32'h4:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
-        32'h5:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
-      endcase
     else if (cmd_data[7:0] == 8'hF9)
       case (spi_byte_cnt)
         32'h2: begin

diff --git a/verilog/sd2snes_gsu/sd2snes_gsu.xise b/verilog/sd2snes_gsu/sd2snes_gsu.xise
@@ -19,10 +19,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
-    <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-    </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
@@ -377,8 +373,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default" xil_pn:x_locked="true"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -460,6 +456,7 @@
     <!-- Do not hand-edit this section, as it will be overwritten when the    -->
     <!-- project is analyzed based on files automatically identified as       -->
     <!-- include files.                                                       -->
+    <file xil_pn:name="config.vh" xil_pn:type="FILE_VERILOG"/>
   </autoManagedFiles>
 
 </project>
diff --git a/verilog/sd2snes_gsu/spi.v b/verilog/sd2snes_gsu/spi.v
@@ -86,9 +86,9 @@ end
 
 always @(posedge clk) begin
   if(SSEL_inactive)
-    byte_cnt_r <= 0;
+    byte_cnt_r <= 16'h0000;
   else if(byte_received_sync)
-    byte_cnt_r <= byte_cnt_r + 1;
+    byte_cnt_r <= byte_cnt_r + 16'h0001;
 end
 
 reg [7:0] byte_data_sent;

diff --git a/verilog/sd2snes_mini/sd2snes_mini.xise b/verilog/sd2snes_mini/sd2snes_mini.xise
@@ -31,10 +31,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
-    <file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
@@ -76,7 +72,7 @@
     <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>

diff --git a/verilog/sd2snes_mini/spi.v b/verilog/sd2snes_mini/spi.v
@@ -69,10 +69,10 @@ always @(posedge SCK) begin
 end
 
 always @(posedge SCK) begin
-  if(~SSELSCKr[1]) begin
+  if(~SSELSCKr[1])
     byte_data_received <= {byte_data_received[6:0], MOSI};
-  end
+  if(~SSELSCKr[1] && bitcnt==3'b111)
-  if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
+    byte_received <= 1'b1;
   else byte_received <= 1'b0;
 end
 
@@ -81,11 +81,10 @@ end
 //wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
 
 always @(posedge clk) begin
-  if(SSEL_inactive) begin
+  if(SSEL_inactive)
     byte_cnt_r <= 16'h0000;
-  end else if(byte_received_sync) begin
+  else if(byte_received_sync)
     byte_cnt_r <= byte_cnt_r + 16'h0001;
-  end
 end
 
 reg [7:0] byte_data_sent;

diff --git a/verilog/sd2snes_sa1/sd2snes_sa1.xise b/verilog/sd2snes_sa1/sd2snes_sa1.xise
@@ -19,10 +19,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
-    <file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
@@ -59,40 +55,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
-    <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_datram.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
@@ -116,10 +78,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="ipcore_dir/dbg_state.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="ipcore_dir/sa1_mult.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
@@ -137,9 +95,6 @@
     <file xil_pn:name="ipcore_dir/dec_table.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/dbg_state.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="ipcore_dir/sa1_mult.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>

diff --git a/verilog/sd2snes_sa1/spi.v b/verilog/sd2snes_sa1/spi.v
@@ -86,9 +86,9 @@ end
 
 always @(posedge clk) begin
   if(SSEL_inactive)
-    byte_cnt_r <= 0;
+    byte_cnt_r <= 16'h0000;
   else if(byte_received_sync)
-    byte_cnt_r <= byte_cnt_r + 1;
+    byte_cnt_r <= byte_cnt_r + 16'h0001;
 end
 
 reg [7:0] byte_data_sent;

diff --git a/verilog/sd2snes_sdd1/mcu_cmd.v b/verilog/sd2snes_sdd1/mcu_cmd.v
@@ -100,15 +100,6 @@ initial begin
   SD_DMA_END_MID_BLOCK = 0;
 end
 
-wire [31:0] snes_sysclk_freq;
-
-clk_test snes_clk_test (
-    .clk(clk),
-    .sysclk(snes_sysclk),
-    .snes_sysclk_freq(snes_sysclk_freq)
-);
-
-
 reg [2:0] MAPPER_BUF;
 reg [23:0] ADDR_OUT_BUF;
 reg [10:0] DAC_ADDR_OUT_BUF;
@@ -120,8 +111,6 @@ reg [5:0] msu_status_reset_out_buf;
 reg msu_status_reset_we_buf = 0;
 reg MSU_RESET_OUT_BUF;
 
-reg [31:0] SNES_SYSCLK_FREQ_BUF;
-
 reg [7:0] MCU_DATA_OUT_BUF;
 reg [7:0] MCU_DATA_IN_BUF;
 reg [2:0] mcu_nextaddr_buf;
@@ -404,19 +393,6 @@ always @(posedge clk) begin
       endcase
     else if (cmd_data[7:0] == 8'hF4)
       MCU_DATA_IN_BUF <= msu_volumerq;
-    else if (cmd_data[7:0] == 8'hFE)
-      case (spi_byte_cnt)
-        32'h1:
-          SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
-        32'h2:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
-        32'h3:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
-        32'h4:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
-        32'h5:
-          MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
-      endcase
     else if (cmd_data[7:0] == 8'hFF)
       MCU_DATA_IN_BUF <= param_data;
     else if (cmd_data[7:0] == 8'hD1)

diff --git a/verilog/sd2snes_sdd1/sd2snes_sdd1.xise b/verilog/sd2snes_sdd1/sd2snes_sdd1.xise
@@ -19,10 +19,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
-    <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
-    </file>
     <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
@@ -47,12 +43,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
-    <file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
-    </file>
     <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>