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Actually run PLL0 within spec (oops)

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mrehkopf committed Nov 5, 2018
1 parent bfc82ba commit c5fa746df3c888ab9cd9da070bf84b76ebf84c03
Showing with 8 additions and 6 deletions.
  1. +8 −6 src/config.h
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@@ -45,13 +45,15 @@
//#define CONFIG_UART_BAUDRATE 115200
#define CONFIG_UART_DEADLOCKABLE
/* PLL0 96MHz
Base clock: 12MHz
Multiplier: 16
Pre-Divisor: 1
Divisor: 4
*/
#define CONFIG_CLK_MULT 16
#define CONFIG_CLK_PREDIV 2
#define CONFIG_CLK_CCLKDIV 2
//#define CONFIG_CLK_MULT 43
//#define CONFIG_CLK_PREDIV 2
//#define CONFIG_CLK_CCLKDIV 6
#define CONFIG_CLK_PREDIV 1
#define CONFIG_CLK_CCLKDIV 4
#define SSP_CLK_DIVISOR 2

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