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Add ChipScope debugging to main core

Can be enabled/disabled in config.vh, due to Spartan 3 space constraints
some block RAMs have to be disabled in order to use it...
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mrehkopf committed Feb 28, 2019
1 parent 43451bf commit fed4deb0983f184800e021b688dbee8c71252f9f
@@ -0,0 +1,27 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:31:19 01/19/2019
// Design Name:
// Module Name: config
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

`ifndef _config_vh
`define _config_vh

// `define DEBUG
`endif

@@ -18,6 +18,8 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"

module dac(
input clkin,
input sysclk,
@@ -55,6 +57,7 @@ always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end

`ifndef DEBUG
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
@@ -63,6 +66,7 @@ dac_buf snes_dac_buf (
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif

reg [10:0] cnt;
reg [15:0] smpcnt;
@@ -0,0 +1,9 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
@@ -0,0 +1,27 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2019 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.7
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Sat Jan 19 00:09:12 Mitteleuropäische Zeit 2019
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead

`timescale 1ns/1ps

module chipscope_icon(
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;


inout [35 : 0] CONTROL0;

endmodule
@@ -0,0 +1,56 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Fri Jan 18 23:08:35 2019
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T14:12:40Z
# END Extra information
GENERATE
# CRC: a85061ec
@@ -0,0 +1,7 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
@@ -0,0 +1,74 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>

<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>

<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="chipscope_icon.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>

<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_icon.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-01-19T00:09:14" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A3070ABEED50481695F288656C93C31B" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>

<bindings/>

<libraries/>

<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>

</project>
@@ -0,0 +1,162 @@
#ChipScope Core Generator Project File Version 3.0
#Mon Jan 21 22:21:47 Mitteleurop�ische Zeit 2019
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
SignalExport.bus<0000>.precision=0
SignalExport.bus<0000>.radix=Bin
SignalExport.bus<0000>.scaleFactor=1.0
SignalExport.bus<0001>.channelList=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SignalExport.bus<0001>.name=TRIG1
SignalExport.bus<0001>.offset=0.0
SignalExport.bus<0001>.precision=0
SignalExport.bus<0001>.radix=Bin
SignalExport.bus<0001>.scaleFactor=1.0
SignalExport.bus<0002>.channelList=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
SignalExport.bus<0002>.name=TRIG2
SignalExport.bus<0002>.offset=0.0
SignalExport.bus<0002>.precision=0
SignalExport.bus<0002>.radix=Bin
SignalExport.bus<0002>.scaleFactor=1.0
SignalExport.bus<0003>.channelList=80 81 82 83
SignalExport.bus<0003>.name=TRIG3
SignalExport.bus<0003>.offset=0.0
SignalExport.bus<0003>.precision=0
SignalExport.bus<0003>.radix=Bin
SignalExport.bus<0003>.scaleFactor=1.0
SignalExport.bus<0004>.channelList=84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
SignalExport.bus<0004>.name=TRIG4
SignalExport.bus<0004>.offset=0.0
SignalExport.bus<0004>.precision=0
SignalExport.bus<0004>.radix=Bin
SignalExport.bus<0004>.scaleFactor=1.0
SignalExport.clockChannel=CLK
SignalExport.dataEqualsTrigger=true
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerChannel<0001><0000>=TRIG1[0]
SignalExport.triggerChannel<0001><0001>=TRIG1[1]
SignalExport.triggerChannel<0001><0002>=TRIG1[2]
SignalExport.triggerChannel<0001><0003>=TRIG1[3]
SignalExport.triggerChannel<0001><0004>=TRIG1[4]
SignalExport.triggerChannel<0001><0005>=TRIG1[5]
SignalExport.triggerChannel<0001><0006>=TRIG1[6]
SignalExport.triggerChannel<0001><0007>=TRIG1[7]
SignalExport.triggerChannel<0001><0008>=TRIG1[8]
SignalExport.triggerChannel<0001><0009>=TRIG1[9]
SignalExport.triggerChannel<0001><0010>=TRIG1[10]
SignalExport.triggerChannel<0001><0011>=TRIG1[11]
SignalExport.triggerChannel<0001><0012>=TRIG1[12]
SignalExport.triggerChannel<0001><0013>=TRIG1[13]
SignalExport.triggerChannel<0001><0014>=TRIG1[14]
SignalExport.triggerChannel<0001><0015>=TRIG1[15]
SignalExport.triggerChannel<0001><0016>=TRIG1[16]
SignalExport.triggerChannel<0001><0017>=TRIG1[17]
SignalExport.triggerChannel<0001><0018>=TRIG1[18]
SignalExport.triggerChannel<0001><0019>=TRIG1[19]
SignalExport.triggerChannel<0001><0020>=TRIG1[20]
SignalExport.triggerChannel<0001><0021>=TRIG1[21]
SignalExport.triggerChannel<0001><0022>=TRIG1[22]
SignalExport.triggerChannel<0001><0023>=TRIG1[23]
SignalExport.triggerChannel<0001><0024>=TRIG1[24]
SignalExport.triggerChannel<0001><0025>=TRIG1[25]
SignalExport.triggerChannel<0001><0026>=TRIG1[26]
SignalExport.triggerChannel<0001><0027>=TRIG1[27]
SignalExport.triggerChannel<0001><0028>=TRIG1[28]
SignalExport.triggerChannel<0001><0029>=TRIG1[29]
SignalExport.triggerChannel<0001><0030>=TRIG1[30]
SignalExport.triggerChannel<0001><0031>=TRIG1[31]
SignalExport.triggerChannel<0002><0000>=TRIG2[0]
SignalExport.triggerChannel<0002><0001>=TRIG2[1]
SignalExport.triggerChannel<0002><0002>=TRIG2[2]
SignalExport.triggerChannel<0002><0003>=TRIG2[3]
SignalExport.triggerChannel<0002><0004>=TRIG2[4]
SignalExport.triggerChannel<0002><0005>=TRIG2[5]
SignalExport.triggerChannel<0002><0006>=TRIG2[6]
SignalExport.triggerChannel<0002><0007>=TRIG2[7]
SignalExport.triggerChannel<0002><0008>=TRIG2[8]
SignalExport.triggerChannel<0002><0009>=TRIG2[9]
SignalExport.triggerChannel<0002><0010>=TRIG2[10]
SignalExport.triggerChannel<0002><0011>=TRIG2[11]
SignalExport.triggerChannel<0002><0012>=TRIG2[12]
SignalExport.triggerChannel<0002><0013>=TRIG2[13]
SignalExport.triggerChannel<0002><0014>=TRIG2[14]
SignalExport.triggerChannel<0002><0015>=TRIG2[15]
SignalExport.triggerChannel<0002><0016>=TRIG2[16]
SignalExport.triggerChannel<0002><0017>=TRIG2[17]
SignalExport.triggerChannel<0002><0018>=TRIG2[18]
SignalExport.triggerChannel<0002><0019>=TRIG2[19]
SignalExport.triggerChannel<0002><0020>=TRIG2[20]
SignalExport.triggerChannel<0002><0021>=TRIG2[21]
SignalExport.triggerChannel<0002><0022>=TRIG2[22]
SignalExport.triggerChannel<0002><0023>=TRIG2[23]
SignalExport.triggerChannel<0002><0024>=TRIG2[24]
SignalExport.triggerChannel<0002><0025>=TRIG2[25]
SignalExport.triggerChannel<0002><0026>=TRIG2[26]
SignalExport.triggerChannel<0002><0027>=TRIG2[27]
SignalExport.triggerChannel<0002><0028>=TRIG2[28]
SignalExport.triggerChannel<0002><0029>=TRIG2[29]
SignalExport.triggerChannel<0002><0030>=TRIG2[30]
SignalExport.triggerChannel<0002><0031>=TRIG2[31]
SignalExport.triggerChannel<0002><0032>=TRIG2[32]
SignalExport.triggerChannel<0002><0033>=TRIG2[33]
SignalExport.triggerChannel<0002><0034>=TRIG2[34]
SignalExport.triggerChannel<0002><0035>=TRIG2[35]
SignalExport.triggerChannel<0002><0036>=TRIG2[36]
SignalExport.triggerChannel<0002><0037>=TRIG2[37]
SignalExport.triggerChannel<0002><0038>=TRIG2[38]
SignalExport.triggerChannel<0002><0039>=TRIG2[39]
SignalExport.triggerChannel<0003><0000>=TRIG3[0]
SignalExport.triggerChannel<0003><0001>=TRIG3[1]
SignalExport.triggerChannel<0003><0002>=TRIG3[2]
SignalExport.triggerChannel<0003><0003>=TRIG3[3]
SignalExport.triggerChannel<0004><0000>=TRIG4[0]
SignalExport.triggerChannel<0004><0001>=TRIG4[1]
SignalExport.triggerChannel<0004><0002>=TRIG4[2]
SignalExport.triggerChannel<0004><0003>=TRIG4[3]
SignalExport.triggerChannel<0004><0004>=TRIG4[4]
SignalExport.triggerChannel<0004><0005>=TRIG4[5]
SignalExport.triggerChannel<0004><0006>=TRIG4[6]
SignalExport.triggerChannel<0004><0007>=TRIG4[7]
SignalExport.triggerChannel<0004><0008>=TRIG4[8]
SignalExport.triggerChannel<0004><0009>=TRIG4[9]
SignalExport.triggerChannel<0004><0010>=TRIG4[10]
SignalExport.triggerChannel<0004><0011>=TRIG4[11]
SignalExport.triggerChannel<0004><0012>=TRIG4[12]
SignalExport.triggerChannel<0004><0013>=TRIG4[13]
SignalExport.triggerChannel<0004><0014>=TRIG4[14]
SignalExport.triggerChannel<0004><0015>=TRIG4[15]
SignalExport.triggerChannel<0004><0016>=TRIG4[16]
SignalExport.triggerChannel<0004><0017>=TRIG4[17]
SignalExport.triggerChannel<0004><0018>=TRIG4[18]
SignalExport.triggerChannel<0004><0019>=TRIG4[19]
SignalExport.triggerChannel<0004><0020>=TRIG4[20]
SignalExport.triggerChannel<0004><0021>=TRIG4[21]
SignalExport.triggerChannel<0004><0022>=TRIG4[22]
SignalExport.triggerChannel<0004><0023>=TRIG4[23]
SignalExport.triggerChannel<0004><0024>=TRIG4[24]
SignalExport.triggerChannel<0004><0025>=TRIG4[25]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPort<0001>.name=TRIG1
SignalExport.triggerPort<0002>.name=TRIG2
SignalExport.triggerPort<0003>.name=TRIG3
SignalExport.triggerPort<0004>.name=TRIG4
SignalExport.triggerPortCount=5
SignalExport.triggerPortIsData<0000>=true
SignalExport.triggerPortIsData<0001>=true
SignalExport.triggerPortIsData<0002>=true
SignalExport.triggerPortIsData<0003>=true
SignalExport.triggerPortIsData<0004>=true
SignalExport.triggerPortWidth<0000>=8
SignalExport.triggerPortWidth<0001>=32
SignalExport.triggerPortWidth<0002>=40
SignalExport.triggerPortWidth<0003>=4
SignalExport.triggerPortWidth<0004>=26
SignalExport.type=ila

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