diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
diff --git a/verilog/sd2snes_cx4/main.ucf b/verilog/sd2snes_cx4/main.ucf
@@ -4,8 +4,6 @@ TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
 NET "p113_out" IOSTANDARD = LVCMOS33;
 NET "p113_out" LOC = P113;
 
-NET "SNES_SYSCLK" LOC = P180;
-NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33;
 NET "SNES_SYSCLK" TNM_NET = "SNES_SYSCLK";
 TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %;
 

diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise
@@ -284,7 +284,7 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -366,8 +366,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="5" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>