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fixed bugs in properly address (next word) instructions in VM

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commit b2927c53f771da993100ba7e381daa61503afaf4 1 parent 949bec9
@aaronbrenzel aaronbrenzel authored
Showing with 32 additions and 15 deletions.
  1. +21 −9 src/c/dcpuvm.c
  2. +1 −1  src/c/disassemble.c
  3. +10 −5 src/haskell/Assembler.hs
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30 src/c/dcpuvm.c
@@ -51,10 +51,12 @@ uint16_t *get_dcpu_value(machine *m, uint16_t opcode) {
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
//the mask at the end ensures the returned address is 16-bit
+ m->PC++;
return m->RAM +
- ((m->RAM[m->PC++] + m->registers[opcode & 7]) & 0xffff);
+ ((m->RAM[m->PC] + m->registers[opcode & 7]) & 0xffff);
case 0x18:
- return m->RAM + m->SP++;
+ m->SP++;
+ return m->RAM + m->SP;
case 0x19:
return m->RAM + m->SP;
case 0x1a:
@@ -66,9 +68,11 @@ uint16_t *get_dcpu_value(machine *m, uint16_t opcode) {
case 0x1d:
return &m->O;
case 0x1e:
- return m->RAM + m->RAM[m->PC++];
+ m->PC++;
+ return m->RAM + m->RAM[m->PC];
case 0x1f:
- return m->RAM + m->PC++;
+ m->PC++;
+ return m->RAM + m->PC;
default:
return literals + (opcode & 0x1F);
};
@@ -76,7 +80,7 @@ uint16_t *get_dcpu_value(machine *m, uint16_t opcode) {
inline void do_set_op(machine *m, uint16_t a, uint16_t b) {
uint16_t *mem_loc = get_dcpu_value(m, a);
- uint16_t *b_val = get_dcpu_value(m, b);
+ uint16_t *b_val = get_dcpu_value(m, b);
*mem_loc = *b_val;
};
@@ -271,8 +275,8 @@ uint16_t execute(machine *m) {
void dumpheader(void) {
fprintf(stdout,
- "PC SP OV A B C X Y Z I J Instruction\n"
- "---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- -----------\n");
+ "PC SP OV A B C X Y Z I J Next Instruction\n"
+ "---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----------------\n");
}
void dumpstate(machine *m) {
@@ -313,8 +317,16 @@ int main(int argc, char** argv) {
machine m;
init_machine(&m);
- load_into_memory(&m, argc > 1 ? argv[1] : "out.hex");
-
+ //load_into_memory(&m, argc > 1 ? argv[1] : "out.hex");
+ m.RAM[0] = 0x7c01;
+ m.RAM[1] = 0x0030;
+ m.RAM[2] = 0x7de1;
+ m.RAM[3] = 0x1000;
+ m.RAM[4] = 0x0020;
+ m.RAM[5] = 0x7803;
+ m.RAM[6] = 0x1000;
+ m.RAM[7] = 0xa861;
+
dumpheader();
uint16_t result = 1;
while (result != 0) {
View
2  src/c/disassemble.c
@@ -39,7 +39,7 @@
typedef uint16_t u16;
static const char *opcode[] = {
- "XXX", "MOV", "ADD", "SUB", "MUL", "DIV", "MOD", "SHL",
+ "XXX", "SET", "ADD", "SUB", "MUL", "DIV", "MOD", "SHL",
"SHR", "AND", "BOR", "XOR", "IFE", "IFN", "IFG", "IFB",
};
View
15 src/haskell/Assembler.hs
@@ -41,6 +41,8 @@ genIdentHex ident = case ident of
Literal _ -> genLiteralHex ident
Address _ -> genAddressHex ident
+genRawHex (Literal i) = read i :: Word16
+
genCmdHex :: Binop -> Word16
genCmdHex SET = 0x1 :: Word16
genCmdHex ADD = 0x2 :: Word16
@@ -58,16 +60,19 @@ genCmdHex IFN = 0xd :: Word16
genCmdHex IFG = 0xe :: Word16
genCmdHex IFB = 0xf :: Word16
-assemble :: Expr -> Word16
+assemble :: Expr -> [Word16]
+assemble (Bin cmd (BinArg a (Literal b))) =
+ [(genCmdHex cmd) .|. ((genIdentHex a) `shiftL` 4) .|.
+ (0x1F `shiftL` 10), genIdentHex (Literal b)]
assemble (Bin cmd (BinArg a b)) =
- (genCmdHex cmd) .|. ((genIdentHex a) `shiftL` 4) .|.
- ((genIdentHex b) `shiftL` 10)
-
+ [(genCmdHex cmd) .|. ((genIdentHex a) `shiftL` 4) .|.
+ ((genIdentHex b) `shiftL` 10)]
+
assembleFromFile path = do
instructions <- parseAssemblerFile path
case (head instructions) of
Error err -> return []
- otherwise -> return (map assemble instructions)
+ otherwise -> return (concat $ map assemble instructions)
writeInstruction instr = do
return $ putWord16host instr
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