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Commits on Feb 14, 2015
  1. NFM cubieboard: mux NAND pins

    authored
    Change-Id: I0b8cb997982fe795203632504f9b250655dc7fbe
  2. cpu/allwinner/a10: Use SD card for bootblock media

    authored
    This is a brute-force approach of copying the entire CBFS to RAM in
    the bootblock. While this may be sub-optimal with large CBFS sizes,
    it simplifies the logic of buffer management. We still do not have
    a proper CBFS infrastructure for handling this.
    
    With this patch, it is now possible to load a uboot payload, and boot
    linux from SD cards.
    
    Change-Id: Ie0b123023c53e485c41650c1fc7b0fb69a286a30
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  3. cpu/allwinner/a10: Import sunxi MMC driver from uboot

    authored
    This import is a stripped-down version which only includes read
    functionality. Erase and write can be added later, if needed.
    
    Change-Id: I8417875737a5f8e1dc21325ad5d6d245423f68cb
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  4. drivers: Import generic MMC handler from uboot

    authored
    Aye and behold, the wonderful world of MMC and SD cards.
    This is the MMC handler imported from uboot and adjusted for coreboot
    use. There are over 100 micro-commits to refactor and clean up the
    ubootian style, so there is no sense in saying what uboot revision
    this came from (yeah, Paul, I'm looking at you).
    
    I've also looked at how Deptcharge deals with MMC, but decided to not
    use code from there for two reasons. First, I would have had to
    refactor a lot of camelcase. Second, I already had most of the uboot
    version up and ready for a while.
    
    Any issues that I consider unresolved or sub-optimal have been noted
    in in-source comments for future reference.
    
    Change-Id: Ied5ac5701d2fe8338fd92477110d6f74a4295371
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  5. drivers/xpowers/axp209: Adapt to new I²C API

    authored
    Originally, axp209_(read|write) accessors relied on i2c_(read|write)
    to return the number of bytes transferred. When this was changed in
    
    * cdb61a6 i2c: Replace the i2c API.
    
    To return an error code or 0 on success. This caused the AXP209 check
    to fail. Fix the accessors to account for this new behavior.
    
    Change-Id: Ib0f492bd52260d224d87f8e8f2d3c1244d1507df
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  6. cpu/allwinner/a10/twi.c: Refactor I²C handler to use i2c_seg API

    authored
    The coreboot I²C API was completely reworked in commit
    * cdb61a6 i2c: Replace the i2c API.
    
    For the allwinner I²C driver, wrappers to the old API were provided
    on a "best guess" basis. Replace these wrappers with proper
    transaction handling based on the i2c_seg API.
    
    Change-Id: Ibdda3b022ce4876deb2906e17a5a0ca9e939aada
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  7. cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM

    authored
    The default linking behavior of ramstage was changed in commit
    * 8f99378 ARMv7/Exynos: Fix memory location assumptions
    
    However, that commit failed to address the issue of maintaining
    linking behavior on non-Exynos chips. As a result we ended up
    linking ramstage at address 0, which is outside of SDRAM.
    
    Explicitly link ramstage at SDRAM base for A10. This patch does not
    address the issue on other chips that were broken by commit 8f99378.
    
    Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/8443
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
  8. @kmalkki

    AMD cimx/sb800: Initially enable all GPP ports

    kmalkki authored
    PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
    appear visible in hardware. The real configuration will be done by
    vendorcode once we call sb_Before_Pci_Init().
    
    Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8387
    Tested-by: build bot (Jenkins)
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  9. @kmalkki

    AMD cimx/sb800: Move cimx init for ramstage

    kmalkki authored
    This has nothing to do with SATA controller. We only need to
    fill the table with defaults before we parse devicetree for
    changes to device configuration.
    
    Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8386
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  10. @kmalkki

    AMD cimx/sb800: Disable unused GPP ports

    kmalkki authored
    If devicetree.cb has GPP port off, really disable it before even
    trying to do link training.
    
    Change-Id: I810945da28d86768e88249dc4d29a50ad9f9959b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8385
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  11. @kmalkki

    AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration

    kmalkki authored
    A set of pins can be configured for GPIO or (parallel) PCI bridge use.
    
    When requested configuration is 0:14.4 enabled, register programming
    must be done before attempting to enumerate devices behind the bridge.
    
    When requested configuration is 0:14.4 disabled, we must not even
    temporarily enable pins for PCI use to avoid spurious GPIO state changes.
    
    As our PCI subsystem currently does not configure visible PCI bridges
    that are marked disabled, we cannot mark 0:14.4 disabled just yet but
    need to handle pcengines/apu1 as a special case.
    
    Drop related dead code.
    
    Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  12. @kmalkki

    AMD cimx/sb800: Fix console output

    kmalkki authored
    These sb800_enable() messages without newline mess up the log.
    
    Change-Id: I1689b68702e08e2a287083835f310f52f495c451
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8384
    Tested-by: build bot (Jenkins)
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  13. @kmalkki

    AGESA fam15tn fam15rl fam16kb: Drop HT3_SUPPORT

    kmalkki authored
    Kconfig variable is not implemented.
    
    Change-Id: I546a1001847e7b1002f96baf49ed3301852a6894
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
  14. @kmalkki

    AGESA fam10 fam12 fam15: Always have HT3_SUPPORT

    kmalkki authored
    Keep the slower HyperTransport configuration for a possible reference
    in fam15 boards.
    
    Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/8344
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
  15. @paulepanter

    arch/x86/boot/tables.c: Remove unused variable assignment to `rom_tab…

    paulepanter authored committed
    …le_end`
    
    Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5106
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
  16. drivers/xpowers/axp209: Print a message when probing fails

    authored
    Probing is done by reading the ID register and comparing it to a known
    value. When there is a mismatch, print an error.
    
    Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/8433
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commits on Feb 13, 2015
  1. superio/fintek/f81216h: Add the correct unlock key values

    Dave Frodin authored
    The actual key values were not added in commit 17ace82.
    TEST: amd/lamar shows the correct result.
    
    Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/8375
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: Marc Jones <marc.jones@se-eng.com>
  2. arm64: Cleanup arch io header files

    Furquan Shaikh authored Marc Jones committed
    BUG=None
    BRANCH=None
    TEST=Compiles successfully for rush
    
    Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55
    Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/203142
    Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2)
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    
    Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48
    Reviewed-on: http://review.coreboot.org/8410
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: Marc Jones <marc.jones@se-eng.com>
  3. southbridge/amd/pi: Combine and correct the IRQ text strings

    Dave Frodin authored
    This combines the Avalon and Bolton tables of text descriptions
    of the IRQ assignments. It also corrects the text string for
    the SD controller on Bolton.
    
    Test: This was verified on amd/lamar.
    
    Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/8374
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
  4. tegra132: Fix build for verstage

    Marc Jones authored
    Verstage isn't included yet, but we need to have
    the Kconfig option for toolchain.inc to pass.
    
    Change-Id: I7fae73cd3b77fd347398221489caf745274701eb
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/8409
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
  5. @pgeorgi

    documentation: begin documenting our use of git submodules

    pgeorgi authored pgeorgi committed
    git submodules have some surprising behaviour, and we make full use
    of it.  Start building a canonical resource for that so developers
    can spend their time on better things than on fighting git.
    
    Change-Id: I5aa721e9b0acb2912a057858fd23a1d59d845ed1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/8371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  6. @pgeorgi

    northbridge/amd/amdfam10: Move K10 specific menu to proper Kconfig file

    Timothy Pearson authored pgeorgi committed
    Change-Id: Ib83ec5c397fdef5aa9e3376f1c0072cfa2f74fa6
    Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/8425
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
  7. @pgeorgi

    fsp_baytrail: Add macros to define 20K pull-up and down

    Werner Zeh authored pgeorgi committed
    Add two macros to gpio.h which allow to setup 20K
    pull-up or pull-down resistor for a given GPIO.
    
    Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483
    Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
    Reviewed-on: http://review.coreboot.org/8402
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
  8. @stefanreinauer

    Fix source code permissions

    stefanreinauer authored
    Two source files were accidently marked executable. Switch them back to
    mode 644 (rw-r---r--)
    
    Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9
    Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/8426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Reviewed-by: Martin Roth <gaumless@gmail.com>
Commits on Feb 12, 2015
  1. @pgeorgi

    Use ALIGN_UP instead of manual alignment

    pgeorgi authored
    BUG=none
    BRANCH=none
    TEST=none
    
    Change-Id: I56f357db6d37120772a03a1f7f84ce2a5b5620e9
    Signed-off-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/241855
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Patrick Georgi <pgeorgi@chromium.org>
    Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
    Reviewed-on: http://review.coreboot.org/8396
    Tested-by: build bot (Jenkins)
  2. @pgeorgi

    lint: exclude *.hex files from whitespace checking

    Werner Zeh authored pgeorgi committed
    If one needs raw binary files, .bin extension cannot
    be used due to settings in .gitignore. This patch
    allows to use .hex files. To avoid lint checks on these
    files, exclude the .hex extension from the test.
    
    Change-Id: I4b503229d63694c48cce12ca8cd33ea58172af01
    Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
    Reviewed-on: http://review.coreboot.org/8403
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
  3. @pgeorgi

    lint: exclude nvidia submodule from file list

    pgeorgi authored pgeorgi committed
    From git's point of view submodules are a weird third thing between file
    and directory. Avoid trying to apply file handling on a directory.
    
    Change-Id: Ibbc9c28e1657d96413c5fb08705d30e25171254d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/8372
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
  4. drivers/xgi: Fix user-visible typo in printk

    Timothy Pearson authored committed
    Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e
    Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/8361
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  5. payloads/seabios: Enable SeaVGABIOS option if native text init supported

    Timothy Pearson authored committed
    SeaVGABIOS supports both the coreboot linear framebuffer and native EGA
    text mode.  To use SeaBIOS interactively on standard VGA hardware a VBIOS
    is needed; SeaVGABIOS is one such option.
    
    TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS.  Was able to
    interact with SeaBIOS and comboot menu, then booted Linux successfully.
    VGA display was continuously usable from power on to Linux login.
    
    Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47
    Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/8368
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  6. @paulepanter

    AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly

    paulepanter authored committed
    Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5101
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
Commits on Feb 11, 2015
  1. cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id

    Nicolas Reinecke authored committed
    Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/8355
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
  2. amd/amdfam10: Fix incorrect core count identification

    Timothy Pearson authored committed
    The core count identification code in the PowerNow! _PSS
    ACPI object generation code was incorrectly copied from the
    model_fxx code.  This code has been rewritten to properly
    return the number of cores installed in the system.
    
    Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99
    Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/8421
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
  3. asus/m4a785/Kconfig: Add vgabios PCI id

    Nicolas Reinecke authored committed
    The PCI id defaults to 1106,3230 -> via chrome 9 ...
    Tested on the board.
    
    Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/8177
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  4. cpu/amd/model_10xxx: update microcode

    Nicolas Reinecke authored committed
    microcode updates are extracted from: www.amd64.org/microcode.html
    Mircocode versions of 1020h and 1022h are more recent in coreboot
    than inside the AMD archive.
    
    Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/8354
    Tested-by: build bot (Jenkins)
    Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
  5. @stefanreinauer

    Add Linux kernel's checkpatch.pl script

    stefanreinauer authored
    Carefully staging to enable checkpatch for coreboot contributions.
    
    The biggest offender of the rules enforced by checkpatch I have found so
    far is ... Oh, you guessed it? It's checkpatch itself.
    
    Change-Id: Iaacbcd52c3bc22b083a24127a3ea17a7cc706245
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/8417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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