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remove the debug print

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1 parent ce24008 commit 2b28d1c534c3a6addb07c94ef82338038ba54a67 @yajin yajin committed with Jan 15, 2009
Showing with 0 additions and 27 deletions.
  1. +0 −10 cpu-exec.c
  2. +0 −17 hw/mips_int.c
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@@ -447,16 +447,6 @@ int cpu_exec(CPUState *env1)
next_tb = 0;
}
#elif defined(TARGET_MIPS)
-if (interrupt_request & CPU_INTERRUPT_HARD)
-{
-if (env->CP0_Cause&0x400)
-{
- printf("HARD INT \n");
- printf("env->CP0_Status %x env->CP0_Cause %x CP0Ca_IP_mask %x \n",env->CP0_Status,env->CP0_Cause,CP0Ca_IP_mask);
- printf("CP0St_IE %x CP0St_EXL %x CP0St_ERL %x \n",CP0St_IE,CP0St_EXL,CP0St_ERL);
- printf("env->hflags %x MIPS_HFLAG_DM %x \n",env->hflags ,MIPS_HFLAG_DM);
-}
-}
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
(env->CP0_Status & (1 << CP0St_IE)) &&
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@@ -28,23 +28,12 @@
IRQ may change */
void cpu_mips_update_irq(CPUState *env)
{
-// if (interrupt_request & CPU_INTERRUPT_HARD)
-//{
-//if (env->CP0_Cause&0x400)
-//{
-// printf("cpu_mips_update_irq \n");
-// printf("env->CP0_Status %x env->CP0_Cause %x CP0Ca_IP_mask %x \n",env->CP0_Status,env->CP0_Cause,CP0Ca_IP_mask);
-// printf("CP0St_IE %x CP0St_EXL %x CP0St_ERL %x \n",CP0St_IE,CP0St_EXL,CP0St_ERL);
-// printf("env->hflags %x MIPS_HFLAG_DM %x \n",env->hflags ,MIPS_HFLAG_DM);
-//}
-//}
if ((env->CP0_Status & (1 << CP0St_IE)) &&
!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) {
if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
!(env->interrupt_request & CPU_INTERRUPT_HARD)) {
- printf("cpu_mips_update_irq \n");
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
} else
@@ -60,14 +49,8 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
- if (env->CP0_Status & 0x1)
- {
- printf("irq %d env->CP0_Cause %x \n",irq,env->CP0_Cause);
- printf("status %x\n",env->CP0_Status);
- }
} else {
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
- //printf("clear irq %d env->CP0_Cause %x \n",irq,env->CP0_Cause);
}
cpu_mips_update_irq(env);
}

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