Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP
Browse files

MIPS JZ Pavo: Fixed compilation with today's QEMU master branch.

  • Loading branch information...
commit 5ddca8586421d484b83986e409396f05eabc8274 1 parent 419c31f
@mthuurne authored
View
243 hw/mips_jz.c
@@ -31,6 +31,7 @@
#include "hw.h"
#include "mips.h"
+#include "mips_cpudevs.h"
#include "sysemu.h"
#include "qemu-timer.h"
#include "qemu-char.h"
@@ -323,7 +324,7 @@ static void jz4740_cpm_write(void *opaque, target_phys_addr_t addr,
{
struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) opaque;
- debug_out(DEBUG_CPM, "write to cpm addr "JZ_FMT_plx" value 0x%x\n", addr, value);
+ debug_out(DEBUG_CPM, "write to cpm addr " TARGET_FMT_plx " value 0x%x\n", addr, value);
switch (addr)
{
@@ -362,7 +363,7 @@ static void jz4740_cpm_write(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_cpm_write undefined addr " JZ_FMT_plx
+ "jz4740_cpm_write undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
@@ -399,7 +400,7 @@ static uint32_t jz474_cpm_read(void *opaque, target_phys_addr_t addr)
return s->ssicdr;
default:
cpu_abort(s->soc->env,
- "jz474_cpm_read undefined addr " JZ_FMT_plx " \n", addr);
+ "jz474_cpm_read undefined addr " TARGET_FMT_plx " \n", addr);
}
}
@@ -407,14 +408,14 @@ static uint32_t jz474_cpm_read(void *opaque, target_phys_addr_t addr)
static CPUReadMemoryFunc *jz4740_cpm_readfn[] = {
- jz4740_badwidth_read32,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz474_cpm_read,
};
static CPUWriteMemoryFunc *jz4740_cpm_writefn[] = {
- jz4740_badwidth_write32,
- jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_cpm_write,
};
@@ -444,7 +445,7 @@ static struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *soc)
jz4740_cpm_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_cpm_readfn, jz4740_cpm_writefn, s);
+ cpu_register_io_memory(jz4740_cpm_readfn, jz4740_cpm_writefn, s);
cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
return s;
}
@@ -485,7 +486,7 @@ static uint32_t jz4740_intc_read(void *opaque, target_phys_addr_t addr)
return s->icpr;
default:
cpu_abort(s->soc->env,
- "jz4740_intc_read undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_intc_read undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
@@ -516,21 +517,21 @@ static void jz4740_intc_write(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_intc_write undefined addr " JZ_FMT_plx
+ "jz4740_intc_write undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
}
static CPUReadMemoryFunc *jz4740_intc_readfn[] = {
- jz4740_badwidth_read32,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz4740_intc_read,
};
static CPUWriteMemoryFunc *jz4740_intc_writefn[] = {
- jz4740_badwidth_write32,
- jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_intc_write,
};
@@ -571,7 +572,7 @@ static qemu_irq *jz4740_intc_init(struct jz_state_s *soc, qemu_irq parent_irq)
jz4740_intc_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_intc_readfn, jz4740_intc_writefn, s);
+ cpu_register_io_memory(jz4740_intc_readfn, jz4740_intc_writefn, s);
cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
return qemu_allocate_irqs(jz4740_set_irq, s, 32);
}
@@ -677,7 +678,7 @@ static uint32_t jz4740_emc_read8(void *opaque, target_phys_addr_t addr)
return (s->sdmr >> ((addr - 0xa000) * 8)) & 0xff;
default:
cpu_abort(s->soc->env,
- "jz4740_emc_read8 undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_emc_read8 undefined addr " TARGET_FMT_plx " \n", addr);
}
@@ -713,7 +714,7 @@ static uint32_t jz4740_emc_read16(void *opaque, target_phys_addr_t addr)
return (s->nferr3 >> ((addr - 0x128) * 8)) & 0xffff;
default:
cpu_abort(s->soc->env,
- "jz4740_emc_read16 undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_emc_read16 undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -772,7 +773,7 @@ static uint32_t jz4740_emc_read32(void *opaque, target_phys_addr_t addr)
return s->dmar;
default:
cpu_abort(s->soc->env,
- "jz4740_emc_read32 undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_emc_read32 undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -782,7 +783,7 @@ static void jz4740_emc_write8(void *opaque, target_phys_addr_t addr,
{
struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
- debug_out(DEBUG_EMC, "jz4740_emc_write8 addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_EMC, "jz4740_emc_write8 addr "TARGET_FMT_plx" value %x\n", addr, value);
switch (addr)
{
@@ -808,7 +809,7 @@ static void jz4740_emc_write8(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_emc_write8 undefined addr " JZ_FMT_plx
+ "jz4740_emc_write8 undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
}
@@ -817,7 +818,7 @@ static void jz4740_emc_write16(void *opaque, target_phys_addr_t addr,
{
struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
- debug_out(DEBUG_EMC, "jz4740_emc_write16 addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_EMC, "jz4740_emc_write16 addr "TARGET_FMT_plx" value %x\n", addr, value);
switch (addr)
{
case 0x108:
@@ -845,7 +846,7 @@ static void jz4740_emc_write16(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_emc_write16 undefined addr " JZ_FMT_plx
+ "jz4740_emc_write16 undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
}
@@ -860,7 +861,7 @@ static void jz4740_emc_write32(void *opaque, target_phys_addr_t addr,
{
struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
- debug_out(DEBUG_EMC, "jz4740_emc_write32 addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_EMC, "jz4740_emc_write32 addr " TARGET_FMT_plx " value %x\n", addr, value);
switch (addr)
{
case 0x104:
@@ -967,7 +968,7 @@ static void jz4740_emc_write32(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_emc_write32 undefined addr " JZ_FMT_plx
+ "jz4740_emc_write32 undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
@@ -975,14 +976,14 @@ static void jz4740_emc_write32(void *opaque, target_phys_addr_t addr,
}
static CPUReadMemoryFunc *jz4740_emc_readfn[] = {
- jz4740_emc_read8,
- jz4740_emc_read16,
+ jz4740_emc_read8,
+ jz4740_emc_read16,
jz4740_emc_read32,
};
static CPUWriteMemoryFunc *jz4740_emc_writefn[] = {
- jz4740_emc_write8,
- jz4740_emc_write16,
+ jz4740_emc_write8,
+ jz4740_emc_write16,
jz4740_emc_write32,
};
@@ -999,7 +1000,7 @@ static struct jz4740_emc_s *jz4740_emc_init(struct jz_state_s *soc,
jz4740_emc_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_emc_readfn, jz4740_emc_writefn, s);
+ cpu_register_io_memory(jz4740_emc_readfn, jz4740_emc_writefn, s);
cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
return s;
@@ -1172,7 +1173,7 @@ static uint32_t jz4740_gpio_read(void *opaque, target_phys_addr_t addr)
return s->paflg[group];
default:
cpu_abort(s->soc->env,
- "jz4740_gpio_read undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_gpio_read undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -1183,7 +1184,7 @@ static void jz4740_gpio_write(void *opaque, target_phys_addr_t addr,
struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) opaque;
uint32_t group;
- debug_out(DEBUG_GPIO, "jz4740_gpio_write addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_GPIO, "jz4740_gpio_write addr " TARGET_FMT_plx " value %x\n", addr, value);
switch (addr)
{
@@ -1332,7 +1333,7 @@ static void jz4740_gpio_write(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_gpio_write undefined addr " JZ_FMT_plx
+ "jz4740_gpio_write undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
@@ -1342,14 +1343,14 @@ static void jz4740_gpio_write(void *opaque, target_phys_addr_t addr,
static CPUReadMemoryFunc *jz4740_gpio_readfn[] = {
- jz4740_badwidth_read32,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz4740_gpio_read,
};
static CPUWriteMemoryFunc *jz4740_gpio_writefn[] = {
- jz4740_badwidth_write32,
- jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_gpio_write,
};
@@ -1365,7 +1366,7 @@ static struct jz4740_gpio_s *jz4740_gpio_init(struct jz_state_s *soc,
jz4740_gpio_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_gpio_readfn, jz4740_gpio_writefn, s);
+ cpu_register_io_memory(jz4740_gpio_readfn, jz4740_gpio_writefn, s);
cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
return s;
@@ -1401,14 +1402,14 @@ static void jz4740_rtc_update_interrupt(struct jz4740_rtc_s *s)
{
if (!s->rtcsr&0x1)
return;
-
+
if (((s->rtccr & 0x40) && (s->rtccr & 0x20))
|| ((s->rtccr & 0x10) && (s->rtccr & 0x8)))
{
debug_out(DEBUG_RTC,"s->rtccr %x \n",s->rtcsr);
qemu_set_irq(s->irq, 1);
}
-
+
}
@@ -1447,7 +1448,7 @@ static void jz4740_rtc_hz(void *opaque)
static void jz4740_rtc_reset(struct jz4740_rtc_s *s)
{
-
+
s->rtccr = 0x81;
s->next = 1000;
@@ -1486,7 +1487,7 @@ static uint32_t jz4740_rtc_read(void *opaque, target_phys_addr_t addr)
return s->hspr;
default:
cpu_abort(s->soc->env,
- "jz4740_rtc_read undefined addr " JZ_FMT_plx "\n", addr);
+ "jz4740_rtc_read undefined addr " TARGET_FMT_plx "\n", addr);
}
return (0);
@@ -1497,15 +1498,15 @@ static void jz4740_rtc_write(void *opaque, target_phys_addr_t addr,
{
struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
- debug_out(DEBUG_RTC, "jz4740_rtc_write addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_RTC, "jz4740_rtc_write addr " TARGET_FMT_plx " value %x\n", addr, value);
switch (addr)
{
case 0x0:
s->rtccr = value & 0x7d;
- if (!value & 0x40)
+ if (~value & 0x40)
s->rtccr &= ~0x40;
- if (!value & 0x10)
+ if (~value & 0x10)
s->rtccr &= ~0x10;
if (s->rtccr & 0x1)
{
@@ -1543,21 +1544,21 @@ static void jz4740_rtc_write(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_rtc_write undefined addr " JZ_FMT_plx
+ "jz4740_rtc_write undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
}
static CPUReadMemoryFunc *jz4740_rtc_readfn[] = {
- jz4740_badwidth_read32,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz4740_rtc_read,
};
static CPUWriteMemoryFunc *jz4740_rtc_writefn[] = {
- jz4740_badwidth_write32,
- jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_rtc_write,
};
@@ -1575,7 +1576,7 @@ static struct jz4740_rtc_s *jz4740_rtc_init(struct jz_state_s *soc,
jz4740_rtc_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_rtc_readfn, jz4740_rtc_writefn, s);
+ cpu_register_io_memory(jz4740_rtc_readfn, jz4740_rtc_writefn, s);
cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
return s;
}
@@ -1714,7 +1715,7 @@ static void jz4740_tcu_if_write8(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_tcu_if_write8 undefined addr " JZ_FMT_plx
+ "jz4740_tcu_if_write8 undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
@@ -1754,7 +1755,7 @@ static void jz4740_tcu_if_write32(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_tcu_if_write32 undefined addr " JZ_FMT_plx
+ "jz4740_tcu_if_write32 undefined addr " TARGET_FMT_plx
" value %x \n", addr, value);
}
@@ -1772,7 +1773,7 @@ static uint32_t jz4740_tcu_if_read8(void *opaque, target_phys_addr_t addr)
return s->ter;
default:
cpu_abort(s->soc->env,
- "jz4740_tcu_if_read8 undefined addr " JZ_FMT_plx "\n", addr);
+ "jz4740_tcu_if_read8 undefined addr " TARGET_FMT_plx "\n", addr);
}
return (0);
}
@@ -1793,7 +1794,7 @@ static uint32_t jz4740_tcu_if_read32(void *opaque, target_phys_addr_t addr)
return s->tmr;
default:
cpu_abort(s->soc->env,
- "jz4740_tcu_if_read32 undefined addr " JZ_FMT_plx "\n", addr);
+ "jz4740_tcu_if_read32 undefined addr " TARGET_FMT_plx "\n", addr);
}
return (0);
@@ -1802,13 +1803,13 @@ static uint32_t jz4740_tcu_if_read32(void *opaque, target_phys_addr_t addr)
static CPUReadMemoryFunc *jz4740_tcu_if_readfn[] = {
jz4740_tcu_if_read8,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz4740_tcu_if_read32,
};
static CPUWriteMemoryFunc *jz4740_tcu_if_writefn[] = {
- jz4740_tcu_if_write8,
- jz4740_badwidth_write32,
+ jz4740_tcu_if_write8,
+ jz4740_badwidth_write32,
jz4740_tcu_if_write32,
};
@@ -1830,8 +1831,7 @@ static struct jz4740_tcu_s *jz4740_tcu_if_init(struct jz_state_s *soc,
jz4740_tcu_if_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_tcu_if_readfn, jz4740_tcu_if_writefn,
- s);
+ cpu_register_io_memory(jz4740_tcu_if_readfn, jz4740_tcu_if_writefn, s);
cpu_register_physical_memory(s->base, 0x00000040, iomemtype);
return s;
@@ -1988,7 +1988,7 @@ static uint32_t jz4740_lcdc_read(void *opaque, target_phys_addr_t addr)
return s->lcdcmd1;
default:
cpu_abort(s->soc->env,
- "jz4740_lcdc_read undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_lcdc_read undefined addr " TARGET_FMT_plx " \n", addr);
}
@@ -1999,7 +1999,7 @@ static void jz4740_lcdc_write(void *opaque, target_phys_addr_t addr,
{
struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
- debug_out(DEBUG_LCDC, "jz4740_lcdc_write addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_LCDC, "jz4740_lcdc_write addr "TARGET_FMT_plx" value %x\n", addr, value);
switch (addr)
{
@@ -2066,21 +2066,21 @@ static void jz4740_lcdc_write(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_lcdc_write undefined addr " JZ_FMT_plx " value %x \n",
+ "jz4740_lcdc_write undefined addr " TARGET_FMT_plx " value %x \n",
addr, value);
}
}
static CPUReadMemoryFunc *jz4740_lcdc_readfn[] = {
- jz4740_badwidth_read32,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz4740_lcdc_read,
};
static CPUWriteMemoryFunc *jz4740_lcdc_writefn[] = {
jz4740_badwidth_write32,
- jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_lcdc_write,
};
@@ -2109,8 +2109,8 @@ static void *jz4740_lcd_get_buffer(struct jz4740_lcdc_s *s,
cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n",
__FUNCTION__);
else
- return phys_ram_base +
- (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
+ return qemu_get_ram_ptr(
+ (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK));
}
static void jz4740_lcd_update_display(void *opaque)
@@ -2151,7 +2151,7 @@ static void jz4740_lcd_update_display(void *opaque)
if (s->width != ds_get_width(s->state) ||
s->height != ds_get_height(s->state))
{
- qemu_console_resize(s->console, s->width, s->height);
+ qemu_console_resize(s->state, s->width, s->height);
s->invalidate = 1;
}
@@ -2183,7 +2183,7 @@ static inline void jz4740_lcd_invalidate_display(void *opaque)
}
static struct jz4740_lcdc_s *jz4740_lcdc_init(struct jz_state_s *soc,
- qemu_irq irq, DisplayState * ds)
+ qemu_irq irq)
{
int iomemtype;
@@ -2191,18 +2191,16 @@ static struct jz4740_lcdc_s *jz4740_lcdc_init(struct jz_state_s *soc,
s->base = JZ4740_PHYS_BASE(JZ4740_LCD_BASE);
s->soc = soc;
s->irq = irq;
- s->state = ds;
-
jz4740_lcdc_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_lcdc_readfn, jz4740_lcdc_writefn, s);
+ cpu_register_io_memory(jz4740_lcdc_readfn, jz4740_lcdc_writefn, s);
cpu_register_physical_memory(s->base, 0x10000, iomemtype);
- s->console = graphic_console_init(s->state, jz4740_lcd_update_display,
- jz4740_lcd_invalidate_display,
- NULL, NULL, s);
+ s->state = graphic_console_init(jz4740_lcd_update_display,
+ jz4740_lcd_invalidate_display,
+ NULL, NULL, s);
switch (ds_get_bits_per_pixel(s->state))
{
case 0x0:
@@ -2229,7 +2227,6 @@ static struct jz4740_lcdc_s *jz4740_lcdc_init(struct jz_state_s *soc,
}
return s;
-
}
#define JZ4740_DMA_NUM 6
@@ -2273,21 +2270,21 @@ static inline void jz4740_dma_transfer(struct jz4740_dma_s *s,
pd_src = cpu_get_physical_page_desc(src);
if ((pd_src & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
/* TODO */
- cpu_abort(cpu_single_env, "%s: DMA source address "JZ_FMT_plx" outside RAM!\n",
+ cpu_abort(cpu_single_env, "%s: DMA source address " TARGET_FMT_plx " outside RAM!\n",
__FUNCTION__, src);
else
- sr = phys_ram_base +
- (pd_src & TARGET_PAGE_MASK) + (src & ~TARGET_PAGE_MASK);
+ sr = qemu_get_ram_ptr(
+ (pd_src & TARGET_PAGE_MASK) + (src & ~TARGET_PAGE_MASK));
pd_dest = cpu_get_physical_page_desc(dest);
if ((pd_dest & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
/* TODO */
cpu_abort(cpu_single_env,
- "%s: DMA destination address "JZ_FMT_plx" outside RAM!\n",
+ "%s: DMA destination address " TARGET_FMT_plx " outside RAM!\n",
__FUNCTION__, dest);
else
- de = phys_ram_base +
- (pd_dest & TARGET_PAGE_MASK) + (dest & ~TARGET_PAGE_MASK);
+ de = qemu_get_ram_ptr(
+ (pd_dest & TARGET_PAGE_MASK) + (dest & ~TARGET_PAGE_MASK));
memcpy(de, sr, len);
}
@@ -2345,23 +2342,22 @@ static inline void jz4740_dma_drun(struct jz4740_dma_s *s, int channel)
desc_phy = s->dda[channel];
if (desc_phy & 0xf)
cpu_abort(s->soc->env,
- "jz4740_dma_drun descriptor address " JZ_FMT_plx
+ "jz4740_dma_drun descriptor address " TARGET_FMT_plx
" must be 4 bytes aligned \n", desc_phy);
pd = cpu_get_physical_page_desc(desc_phy);
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
cpu_abort(cpu_single_env,
- "%s: DMA descriptor address " JZ_FMT_plx " outside RAM!\n",
+ "%s: DMA descriptor address " TARGET_FMT_plx " outside RAM!\n",
__FUNCTION__, desc_phy);
else
- desc = (struct jz4740_desc_s *) (phys_ram_base +
+ desc = (struct jz4740_desc_s *) qemu_get_ram_ptr(
(pd & TARGET_PAGE_MASK) +
(desc_phy & ~TARGET_PAGE_MASK));
if (!desc)
cpu_abort(cpu_single_env,
- "%s: DMA descriptor %x is NULL!\n", __FUNCTION__,
- (uint32_t)desc);
+ "%s: DMA descriptor is NULL!\n", __FUNCTION__);
while (1)
{
@@ -2396,18 +2392,17 @@ static inline void jz4740_dma_drun(struct jz4740_dma_s *s, int channel)
pd = cpu_get_physical_page_desc(desc_phy);
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
cpu_abort(cpu_single_env,
- "%s: DMA descriptor address "JZ_FMT_plx" outside RAM!\n",
+ "%s: DMA descriptor address " TARGET_FMT_plx " outside RAM!\n",
__FUNCTION__, desc_phy);
else
- desc = (struct jz4740_desc_s *) (phys_ram_base +
+ desc = (struct jz4740_desc_s *) qemu_get_ram_ptr(
(pd & TARGET_PAGE_MASK)
+
(desc_phy &
~TARGET_PAGE_MASK));
if (!desc)
cpu_abort(cpu_single_env,
- "%s: DMA descriptor %x is NULL!\n",
- __FUNCTION__, (uint32_t) desc);
+ "%s: DMA descriptor is NULL!\n", __FUNCTION__);
}
else
break;
@@ -2520,7 +2515,7 @@ static uint32_t jz4740_dma_read(void *opaque, target_phys_addr_t addr)
return s->dda[channel];
default:
cpu_abort(s->soc->env,
- "jz4740_dma_read undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_dma_read undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -2531,7 +2526,7 @@ static void jz4740_dma_write(void *opaque, target_phys_addr_t addr,
struct jz4740_dma_s *s = (struct jz4740_dma_s *) opaque;
int channel;
- debug_out(DEBUG_DMA, "jz4740_dma_write addr "JZ_FMT_plx" value %x \n", addr, value);
+ debug_out(DEBUG_DMA, "jz4740_dma_write addr " TARGET_FMT_plx " value %x \n", addr, value);
switch (addr)
{
case 0x304:
@@ -2625,20 +2620,20 @@ static void jz4740_dma_write(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_dma_read undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_dma_read undefined addr " TARGET_FMT_plx " \n", addr);
}
}
static CPUReadMemoryFunc *jz4740_dma_readfn[] = {
- jz4740_badwidth_read32,
- jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz4740_dma_read,
};
static CPUWriteMemoryFunc *jz4740_dma_writefn[] = {
- jz4740_badwidth_write32,
- jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_dma_write,
};
@@ -2655,7 +2650,7 @@ static struct jz4740_dma_s *jz4740_dma_init(struct jz_state_s *soc,
jz4740_dma_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_dma_readfn, jz4740_dma_writefn, s);
+ cpu_register_io_memory(jz4740_dma_readfn, jz4740_dma_writefn, s);
cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
return s;
@@ -2691,8 +2686,8 @@ struct jz4740_sadc_s
uint16_t pen_state;
uint8_t read_index;
-
-
+
+
};
static void jz4740_touchscreen_interrupt(struct jz4740_sadc_s *s)
@@ -2705,7 +2700,7 @@ static void jz4740_touchscreen_interrupt(struct jz4740_sadc_s *s)
debug_out(DEBUG_SADC,"irq s->adctrl %x s->adstate %x \n",s->adctrl,s->adstate);
qemu_set_irq(s->irq,1);
}
-
+
}
static void jz4740_touchscreen_event(void *opaque,
@@ -2730,7 +2725,7 @@ static void jz4740_touchscreen_event(void *opaque,
jz4740_touchscreen_interrupt(s);
}
s->pen_state = buttons_state;
-
+
}
static uint32_t jz4740_sadc_read8(void *opaque, target_phys_addr_t addr)
@@ -2747,7 +2742,7 @@ static uint32_t jz4740_sadc_read8(void *opaque, target_phys_addr_t addr)
return s->adstate;
default:
cpu_abort(s->soc->env,
- "jz4740_sadc_read8 undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_sadc_read8 undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -2755,7 +2750,7 @@ static uint32_t jz4740_sadc_read8(void *opaque, target_phys_addr_t addr)
static uint32_t jz4740_sdac_read16(void *opaque, target_phys_addr_t addr)
{
struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
-
+
switch (addr)
{
case 0x10:
@@ -2768,7 +2763,7 @@ static uint32_t jz4740_sdac_read16(void *opaque, target_phys_addr_t addr)
return s->adsdat;
default:
cpu_abort(s->soc->env,
- "jz4740_sdac_read16 undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_sdac_read16 undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -2794,7 +2789,7 @@ static uint32_t jz4740_sdac_read32(void *opaque, target_phys_addr_t addr)
}
default:
cpu_abort(s->soc->env,
- "jz4740_sdac_read32 undefined addr " JZ_FMT_plx " \n", addr);
+ "jz4740_sdac_read32 undefined addr " TARGET_FMT_plx " \n", addr);
}
return (0);
}
@@ -2804,7 +2799,7 @@ static void jz4740_sadc_write8(void *opaque, target_phys_addr_t addr,
{
struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
- debug_out(DEBUG_SADC, "jz4740_sadc_write8 addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_SADC, "jz4740_sadc_write8 addr " TARGET_FMT_plx " value %x\n", addr, value);
switch (addr)
{
@@ -2820,7 +2815,7 @@ static void jz4740_sadc_write8(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_sadc_write8 undefined addr " JZ_FMT_plx " value %x \n", addr,value);
+ "jz4740_sadc_write8 undefined addr " TARGET_FMT_plx " value %x \n", addr,value);
}
}
@@ -2829,7 +2824,7 @@ static void jz4740_sadc_write16(void *opaque, target_phys_addr_t addr,
{
struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
- debug_out(DEBUG_SADC, "jz4740_sadc_write16 addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_SADC, "jz4740_sadc_write16 addr " TARGET_FMT_plx " value %x\n", addr, value);
switch (addr)
{
@@ -2845,7 +2840,7 @@ static void jz4740_sadc_write16(void *opaque, target_phys_addr_t addr,
s->adsdat = 0x0;
default:
cpu_abort(s->soc->env,
- "jz4740_sadc_write16 undefined addr " JZ_FMT_plx " value %x \n", addr,value);
+ "jz4740_sadc_write16 undefined addr " TARGET_FMT_plx " value %x \n", addr,value);
}
}
@@ -2855,7 +2850,7 @@ static void jz4740_sadc_write32(void *opaque, target_phys_addr_t addr,
struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
- debug_out(DEBUG_SADC, "jz4740_sadc_write32 addr "JZ_FMT_plx" value %x\n", addr, value);
+ debug_out(DEBUG_SADC, "jz4740_sadc_write32 addr " TARGET_FMT_plx " value %x\n", addr, value);
switch (addr)
{
@@ -2870,7 +2865,7 @@ static void jz4740_sadc_write32(void *opaque, target_phys_addr_t addr,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_sadc_write32 undefined addr " JZ_FMT_plx " value %x \n", addr,value);
+ "jz4740_sadc_write32 undefined addr " TARGET_FMT_plx " value %x \n", addr,value);
}
}
@@ -2884,20 +2879,20 @@ static void jz4740_sadc_reset(struct jz4740_sadc_s *s)
}
static CPUReadMemoryFunc *jz4740_sadc_readfn[] = {
- jz4740_sadc_read8,
- jz4740_sdac_read16,
+ jz4740_sadc_read8,
+ jz4740_sdac_read16,
jz4740_sdac_read32,
};
static CPUWriteMemoryFunc *jz4740_sadc_writefn[] = {
- jz4740_sadc_write8,
- jz4740_sadc_write16,
+ jz4740_sadc_write8,
+ jz4740_sadc_write16,
jz4740_sadc_write32,
};
static struct jz4740_sadc_s *jz4740_sadc_init(struct jz_state_s *soc,
qemu_irq irq)
-{
+{
int iomemtype;
struct jz4740_sadc_s *s;
@@ -2913,7 +2908,7 @@ static struct jz4740_sadc_s *jz4740_sadc_init(struct jz_state_s *soc,
jz4740_sadc_reset(s);
iomemtype =
- cpu_register_io_memory(0, jz4740_sadc_readfn, jz4740_sadc_writefn, s);
+ cpu_register_io_memory(jz4740_sadc_readfn, jz4740_sadc_writefn, s);
cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
return s;
}
@@ -2924,7 +2919,7 @@ static void jz4740_cpu_reset(void *opaque)
}
struct jz_state_s *jz4740_init(unsigned long sdram_size,
- uint32_t osc_extal_freq, DisplayState * ds)
+ uint32_t osc_extal_freq)
{
struct jz_state_s *s = (struct jz_state_s *)
qemu_mallocz(sizeof(struct jz_state_s));
@@ -2950,9 +2945,9 @@ struct jz_state_s *jz4740_init(unsigned long sdram_size,
jz_clk_init(s, osc_extal_freq);
/*map sram to 0x80000000 and sdram to 0x80004000 */
- sram_base = qemu_ram_alloc(s->sram_size);
+ sram_base = qemu_ram_alloc(NULL, "jz4740.sram", s->sram_size);
cpu_register_physical_memory(0x0, s->sram_size, (sram_base | IO_MEM_RAM));
- sdram_base = qemu_ram_alloc(s->sdram_size);
+ sdram_base = qemu_ram_alloc(NULL, "jz4740.sdram", s->sdram_size);
cpu_register_physical_memory(JZ4740_SRAM_SIZE, s->sdram_size,
(sdram_base | IO_MEM_RAM));
@@ -2971,12 +2966,12 @@ struct jz_state_s *jz4740_init(unsigned long sdram_size,
s->rtc = jz4740_rtc_init(s, intc[15]);
s->tcu = jz4740_tcu_if_init(s, intc[23], intc[22], intc[21]);
jz4740_tcu_init(s, s->tcu, 0);
- s->lcdc = jz4740_lcdc_init(s, intc[30], ds);
+ s->lcdc = jz4740_lcdc_init(s, intc[30]);
s->dma = jz4740_dma_init(s, intc[20]);
s->sadc = jz4740_sadc_init(s,intc[12]);
if (serial_hds[0])
- serial_mm_init(0x10030000, 2, intc[9], 57600, serial_hds[0], 1);
+ serial_mm_init(0x10030000, 2, intc[9], 57600, serial_hds[0], 1, 0);
return s;
}
View
15 hw/mips_jz.h
@@ -22,6 +22,7 @@
#define _MIPS_JZ_H_
#include "qemu-common.h"
+#include "targphys.h"
@@ -102,8 +103,6 @@
-#define JZ_FMT_plx "%llx"
-
uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr);
uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr);
uint32_t jz4740_badwidth_read32(void *opaque, target_phys_addr_t addr);
@@ -118,19 +117,19 @@ void jz4740_badwidth_write32(void *opaque, target_phys_addr_t addr,
#ifdef IO_ACCESS_VERBOSE
#define JZ4740_8B_REG(paddr) \
- fprintf(stderr, "%s: 8-bit register " JZ_FMT_plx "\n", \
+ fprintf(stderr, "%s: 8-bit register " TARGET_FMT_plx "\n", \
__FUNCTION__, paddr)
#define JZ4740_16B_REG(paddr) \
- fprintf(stderr, "%s: 16-bit register " JZ_FMT_plx "\n", \
+ fprintf(stderr, "%s: 16-bit register " TARGET_FMT_plx "\n", \
__FUNCTION__, paddr)
#define JZ4740_32B_REG(paddr) \
- fprintf(stderr, "%s: 32-bit register " JZ_FMT_plx "\n", \
+ fprintf(stderr, "%s: 32-bit register " TARGET_FMT_plx "\n", \
__FUNCTION__, paddr)
#define JZ4740_RO_REG(paddr) \
- fprintf(stderr, "%s: write to read only 32-bit register " JZ_FMT_plx "\n", \
+ fprintf(stderr, "%s: write to read only 32-bit register " TARGET_FMT_plx "\n", \
__FUNCTION__, paddr)
#define JZ4740_WO_REG(paddr) \
- fprintf(stderr, "%s: read from write only 32-bit register " JZ_FMT_plx "\n", \
+ fprintf(stderr, "%s: read from write only 32-bit register " TARGET_FMT_plx "\n", \
__FUNCTION__, paddr)
#else
#define JZ4740_8B_REG(paddr)
@@ -177,7 +176,7 @@ void jz_clk_reparent(jz_clk clk, jz_clk parent);
/*mips_jz.c*/
struct jz_state_s *jz4740_init(unsigned long sdram_size,
- uint32_t osc_extal_freq,DisplayState * ds);
+ uint32_t osc_extal_freq);
enum jz_cpu_model {
jz4740,
View
34 hw/mips_jz_glue.h
@@ -23,7 +23,7 @@
*/
-
+
#ifdef TCU_INDEX
static inline void glue(jz4740_tcu_time_sync,
TCU_INDEX) (struct jz4740_tcu_s * s)
@@ -48,8 +48,8 @@ static inline void glue(jz4740_tcu_time_sync,
// s->freq[TCU_INDEX], s->prescale[TCU_INDEX]);
// debug_out(DEBUG_TCU, "distance %lld s->time[TCU_INDEX] %lld \n",
// distance, s->time[TCU_INDEX]);
- //temp = muldiv64(distance,(s->freq[TCU_INDEX]/s->prescale[TCU_INDEX]),ticks_per_sec);
- temp = muldiv64(distance, 46875, ticks_per_sec);
+ //temp = muldiv64(distance,(s->freq[TCU_INDEX]/s->prescale[TCU_INDEX]),get_ticks_per_sec());
+ temp = muldiv64(distance, 46875, get_ticks_per_sec());
if (temp != 0)
{
/*distance is too short */
@@ -63,7 +63,7 @@ static inline void glue(jz4740_tcu_time_sync,
*/
}
- //printf("%lld distance %lld \n",muldiv64(distance,(s->freq[TCU_INDEX]/s->prescale[TCU_INDEX]),ticks_per_sec),distance);
+ //printf("%lld distance %lld \n",muldiv64(distance,(s->freq[TCU_INDEX]/s->prescale[TCU_INDEX]),get_ticks_per_sec()),distance);
if (s->tcnt[TCU_INDEX] >= 0x10000)
s->tcnt[TCU_INDEX] = 0x0;
@@ -81,7 +81,7 @@ static inline void glue(jz4740_tcu_start_half,
/*The timer has not beed initialized */
if (!s->half_timer[TCU_INDEX])
return;
-
+
if ((!(s->tsr & (1 << (TCU_INDEX+16)))) && (s->ter & (1 << (TCU_INDEX+16)))
&& (s->freq[TCU_INDEX] != 0))
{
@@ -89,7 +89,7 @@ static inline void glue(jz4740_tcu_start_half,
/*calculate next fire time */
count =
(s->tdhr[TCU_INDEX] - s->tcnt[TCU_INDEX]) * s->prescale[TCU_INDEX];
- next += muldiv64(count, ticks_per_sec, s->freq[TCU_INDEX]);
+ next += muldiv64(count, get_ticks_per_sec(), s->freq[TCU_INDEX]);
qemu_mod_timer(s->half_timer[TCU_INDEX], next);
}
@@ -107,7 +107,7 @@ static inline void glue(jz4740_tcu_start_full,
/*The timer has not beed initialized */
if (!s->full_timer[TCU_INDEX])
return;
-
+
debug_out(DEBUG_TCU, "s->tsr %d s->ter %d s->freq[TCU_INDEX] %d \n",
s->tsr , s->ter ,s->freq[TCU_INDEX]);
if ((!(s->tsr & (1 << TCU_INDEX))) && (s->ter & (1 << TCU_INDEX))
@@ -117,7 +117,7 @@ static inline void glue(jz4740_tcu_start_full,
/*calculate next fire time */
count =
(s->tdfr[TCU_INDEX] - s->tcnt[TCU_INDEX]) * s->prescale[TCU_INDEX];
- next += muldiv64(count, ticks_per_sec, s->freq[TCU_INDEX]);
+ next += muldiv64(count, get_ticks_per_sec(), s->freq[TCU_INDEX]);
qemu_mod_timer(s->full_timer[TCU_INDEX], next);
debug_out(DEBUG_TCU, "s->tdfr[TCU_INDEX] %d s->tcnt[TCU_INDEX] %d next %lld \n",
s->tdfr[TCU_INDEX] , s->tcnt[TCU_INDEX] ,next);
@@ -127,10 +127,10 @@ static inline void glue(jz4740_tcu_start_full,
}
-/*
+/*
* TCNT will reset to 0 if it reach to TDFR.
* So for the half compare, the next fire count is (TDFR-TDHR) + TDHR
- *
+ *
*/
static void glue(jz4740_tcu_half_cb, TCU_INDEX) (void *opaque)
{
@@ -142,7 +142,7 @@ static void glue(jz4740_tcu_half_cb, TCU_INDEX) (void *opaque)
&& (s->freq[TCU_INDEX] != 0))
{
count = s->tdfr[TCU_INDEX] * s->prescale[TCU_INDEX];
- next += muldiv64(count, ticks_per_sec, s->freq[TCU_INDEX]);
+ next += muldiv64(count, get_ticks_per_sec(), s->freq[TCU_INDEX]);
qemu_mod_timer(s->half_timer[TCU_INDEX], next);
s->tfr |= 1 << (16 + TCU_INDEX);
jz4740_tcu_update_interrupt(s);
@@ -164,7 +164,7 @@ static void glue(jz4740_tcu_full_cb, TCU_INDEX) (void *opaque)
&& (s->freq[TCU_INDEX] != 0))
{
count = s->tdfr[TCU_INDEX] * s->prescale[TCU_INDEX];
- next += muldiv64(count, ticks_per_sec, s->freq[TCU_INDEX]);
+ next += muldiv64(count, get_ticks_per_sec(), s->freq[TCU_INDEX]);
qemu_mod_timer(s->full_timer[TCU_INDEX], next);
s->tfr |= 1 << TCU_INDEX;
jz4740_tcu_update_interrupt(s);
@@ -196,7 +196,7 @@ static uint32_t glue(jz4740_tcu_read, TCU_INDEX) (void *opaque,
return s->tcsr[TCU_INDEX];
default:
cpu_abort(s->soc->env,
- "jz4740_tcu_read undefined addr "JZ_FMT_plx" timer %x \n", addr,
+ "jz4740_tcu_read undefined addr " TARGET_FMT_plx " timer %x \n", addr,
TCU_INDEX);
}
return (0);
@@ -208,14 +208,14 @@ static void glue(jz4740_tcu_write, TCU_INDEX) (void *opaque,
{
struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
- debug_out(DEBUG_TCU, "jz4740_tcu_write%x addr "JZ_FMT_plx" value %x \n", TCU_INDEX,
+ debug_out(DEBUG_TCU, "jz4740_tcu_write%x addr " TARGET_FMT_plx " value %x \n", TCU_INDEX,
addr, value);
addr -= 0x40 + TCU_INDEX * 0x10;
switch (addr)
{
case 0x0:
- /*TDFR*/
+ /*TDFR*/
s->tdfr[TCU_INDEX] = value & 0xffff;
glue(jz4740_tcu_start_full, TCU_INDEX) (s);
break;
@@ -253,7 +253,7 @@ static void glue(jz4740_tcu_write, TCU_INDEX) (void *opaque,
break;
default:
cpu_abort(s->soc->env,
- "jz4740_tcu_write undefined addr "JZ_FMT_plx" timer %x \n", addr,
+ "jz4740_tcu_write undefined addr " TARGET_FMT_plx " timer %x \n", addr,
TCU_INDEX);
}
@@ -281,7 +281,7 @@ static void glue(jz4740_tcu_init, TCU_INDEX) (struct jz_state_s * soc,
qemu_new_timer(vm_clock, glue(jz4740_tcu_full_cb, TCU_INDEX), s);
iomemtype =
- cpu_register_io_memory(0, glue(jz4740_tcu_readfn, TCU_INDEX),
+ cpu_register_io_memory(glue(jz4740_tcu_readfn, TCU_INDEX),
glue(jz4740_tcu_writefn, TCU_INDEX), s);
cpu_register_physical_memory(s->base + 0x00000040 + TCU_INDEX * 0x10,
0x00000010, iomemtype);
View
34 hw/mips_pavo.c
@@ -114,17 +114,16 @@ CPUWriteMemoryFunc *pavo_nand_writefn[] = {
jz4740_badwidth_write16,
jz4740_badwidth_write32,
};
-
+
static void pavo_nand_setup(struct mips_pavo_s *s)
{
int iomemtype;
-
+
/*K9K8G08U0*/
s->nand = nandb_init(NAND_MFR_SAMSUNG,0xd3);
- iomemtype = cpu_register_io_memory(0, pavo_nand_readfn,
- pavo_nand_writefn, s);
- cpu_register_physical_memory(0x18000000, 0x20000, iomemtype);
+ iomemtype = cpu_register_io_memory(pavo_nand_readfn, pavo_nand_writefn, s);
+ cpu_register_physical_memory(0x18000000, 0x20000, iomemtype);
}
static int pavo_nand_read_page(struct mips_pavo_s *s,uint8_t *buf, uint16_t page_addr)
@@ -160,13 +159,13 @@ static int pavo_boot_from_nand(struct mips_pavo_s *s)
uint32_t nand_pages,i;
//int fd;
-
+
len = 0x2000; /*8K*/
-
+
/*put the first page into internal ram*/
- load_dest = phys_ram_base;
-
+ load_dest = qemu_get_ram_ptr(0);
+
nand_pages = len/0x800;
//fd = open("u-boot.bin", O_RDWR | O_CREAT);
for (i=0;i<nand_pages;i++)
@@ -187,15 +186,16 @@ static int pavo_boot_from_nand(struct mips_pavo_s *s)
static int pavo_rom_emu(struct mips_pavo_s *s)
{
if (pavo_boot_from_nand(s)<0)
- return (-1);
+ return (-1);
return (0);
}
-static void mips_pavo_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState * ds,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+static void mips_pavo_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
{
struct mips_pavo_s *s = (struct mips_pavo_s *) qemu_mallocz(sizeof(*s));
@@ -205,7 +205,7 @@ static void mips_pavo_init(ram_addr_t ram_size, int vga_ram_size,
PAVO_RAM_SIZE + JZ4740_SRAM_SIZE);
exit(1);
}
- s->soc = jz4740_init(PAVO_RAM_SIZE, PAVO_OSC_EXTAL,ds);
+ s->soc = jz4740_init(PAVO_RAM_SIZE, PAVO_OSC_EXTAL);
pavo_nand_setup(s);
if (pavo_rom_emu(s)<0)
{
@@ -222,8 +222,6 @@ QEMUMachine mips_pavo_machine = {
.name = "pavo",
.desc = "JZ Pavo demo board",
.init = mips_pavo_init,
- .ram_require = (JZ4740_SRAM_SIZE + PAVO_RAM_SIZE) | RAMSIZE_FIXED,
- .nodisk_ok = 1,
};
static void mips_pavo_machine_init(void)
View
38 hw/nand_bpage.c
@@ -22,7 +22,7 @@
#include "hw.h"
#include "flash.h"
#include "block.h"
-#include "sysemu.h"
+#include "blockdev.h"
#define MAX_PAGE 0x800
@@ -72,7 +72,7 @@ struct nand_bflash_s
uint32 addr_cycle;
uint32 cmd, status;
- #ifdef DEBUG
+ #ifdef DEBUG
FILE *fp;
#endif
};
@@ -87,7 +87,7 @@ static void debug_init(struct nand_bflash_s *s)
fprintf(stderr,"can not open nandflash_debug.txt \n");
exit(-1);
}
-
+
}
static void debug_out(struct nand_bflash_s *s,const char* format, ...)
{
@@ -104,11 +104,11 @@ static void debug_out(struct nand_bflash_s *s,const char* format, ...)
#else
static void debug_init(struct nand_bflash_s *s)
{
-
+
}
static void debug_out(struct nand_bflash_s *s,const char* format, ...)
{
-
+
}
#endif
@@ -171,7 +171,7 @@ static void nandb_blk_load(struct nand_bflash_s *s)
debug_out(s,"nandb_blk_load page number %x s->addr_low %x s->addr_high %x\n",page_number,s->addr_low,s->addr_high);
if (page_number >= s->pages)
return;
-
+
if (bdrv_read(s->bdrv, (page_number * s->page_oob_size + offset) >> 9,
s->io, (s->page_sectors + 2)) == -1)
printf("%s: read error in sector %i\n",
@@ -195,7 +195,7 @@ static void nandb_blk_erase(struct nand_bflash_s *s)
return;
addr = page_number * s->page_oob_size;
-
+
sector = addr >> 9;
if (bdrv_read(s->bdrv, sector, iobuf, 1) == -1)
printf("%s: read error in sector %i\n", __FUNCTION__, sector);
@@ -353,7 +353,7 @@ void nandb_write_address(struct nand_bflash_s *s, uint16_t value)
s->addr_low += colum_addr;
}
s->addr_cycle++;
-
+
}
uint8_t nandb_read_data8(struct nand_bflash_s *s)
@@ -370,11 +370,11 @@ uint8_t nandb_read_data8(struct nand_bflash_s *s)
fprintf(stderr,"iolen <0 \n");
exit(-1);
}
- if (s->cmd!=0x70)
+ if (s->cmd!=0x70)
s->iolen -=1 ;
ret = *((uint8_t *)s->ioaddr);
- if (s->cmd!=0x70)
- s->ioaddr += 1;
+ if (s->cmd!=0x70)
+ s->ioaddr += 1;
//debug_out(s," %x ",ret);
return ret;
@@ -405,11 +405,11 @@ uint16_t nandb_read_data16(struct nand_bflash_s *s)
fprintf(stderr,"iolen <0 \n");
exit(-1);
}
- if (s->cmd!=0x70)
+ if (s->cmd!=0x70)
s->iolen -=2 ;
ret = *((uint16_t *)s->ioaddr);
- if (s->cmd!=0x70)
- s->ioaddr += 2;
+ if (s->cmd!=0x70)
+ s->ioaddr += 2;
return ret;
}
@@ -429,7 +429,7 @@ struct nand_bflash_s *nandb_init(int manf_id, int chip_id)
{
//int pagesize;
struct nand_bflash_s *s;
- int index;
+ DriveInfo *dinfo;
int i;
s = (struct nand_bflash_s *) qemu_mallocz(sizeof(struct nand_bflash_s));
@@ -464,10 +464,10 @@ struct nand_bflash_s *nandb_init(int manf_id, int chip_id)
exit(-1);
}
-
- index = drive_get_index(IF_MTD, 0, 0);
- if (index != -1)
- s->bdrv = drives_table[index].bdrv;
+
+ dinfo = drive_get(IF_MTD, 0, 0);
+ if (dinfo)
+ s->bdrv = dinfo->bdrv;
else
{
fprintf(stderr, "%s: Please use -mtdblock to specify flash image.\n",
Please sign in to comment.
Something went wrong with that request. Please try again.