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1.fix the new line issue(dos2unix)

2.add int controller emulation
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1 parent 04e63c5 commit 897df225e82944e7d63f7f4f8359137f004fd60f @yajin yajin committed with
Showing with 248 additions and 80 deletions.
  1. +197 −41 hw/mips_jz.c
  2. +23 −32 hw/mips_jz.h
  3. +18 −1 hw/mips_jz_clk.c
  4. +10 −6 hw/mips_pavo.c
View
238 hw/mips_jz.c
@@ -43,22 +43,10 @@
#define DEBUG_FLAG (DEBUG_CPM)
-
-struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *cpu);
-void jz4740_bandwidth_write8(void *opaque, target_phys_addr_t addr,
- uint32_t value);
-void jz4740_bandwidth_write16(void *opaque, target_phys_addr_t addr,
- uint32_t value);
-void jz4740_bandwidth_write32(void *opaque, target_phys_addr_t addr,
- uint32_t value);
-uint32_t jz4740_bandwidth_read8(void *opaque, target_phys_addr_t addr);
-uint32_t jz4740_bandwidth_read16(void *opaque, target_phys_addr_t addr);
-uint32_t jz4740_bandwidth_read32(void *opaque, target_phys_addr_t addr);
-
#ifdef DEBUG
FILE *fp;
-static void debug_init(void)
+static void debug_init()
{
fp = fopen("jz4740.txt", "w+");
if (fp == NULL)
@@ -82,7 +70,7 @@ static void debug_out(uint32_t flag, const char *format, ...)
}
}
#else
-static void debug_init(void)
+static void debug_init()
{
}
static void debug_out(uint32_t flag, const char *format, ...)
@@ -90,7 +78,7 @@ static void debug_out(uint32_t flag, const char *format, ...)
}
#endif
-uint32_t jz4740_bandwidth_read8(void *opaque, target_phys_addr_t addr)
+uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr)
{
uint8_t ret;
@@ -99,7 +87,7 @@ uint32_t jz4740_bandwidth_read8(void *opaque, target_phys_addr_t addr)
return ret;
}
-void jz4740_bandwidth_write8(void *opaque, target_phys_addr_t addr,
+void jz4740_badwidth_write8(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
uint8_t val8 = value;
@@ -108,7 +96,7 @@ void jz4740_bandwidth_write8(void *opaque, target_phys_addr_t addr,
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
-uint32_t jz4740_bandwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr)
{
uint16_t ret;
JZ4740_16B_REG(addr);
@@ -116,7 +104,7 @@ uint32_t jz4740_bandwidth_read16(void *opaque, target_phys_addr_t addr)
return ret;
}
-void jz4740_bandwidth_write16(void *opaque, target_phys_addr_t addr,
+void jz4740_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
uint16_t val16 = value;
@@ -125,7 +113,7 @@ void jz4740_bandwidth_write16(void *opaque, target_phys_addr_t addr,
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
-uint32_t jz4740_bandwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t jz4740_badwidth_read32(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -134,7 +122,7 @@ uint32_t jz4740_bandwidth_read32(void *opaque, target_phys_addr_t addr)
return ret;
}
-void jz4740_bandwidth_write32(void *opaque, target_phys_addr_t addr,
+void jz4740_badwidth_write32(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
JZ4740_32B_REG(addr);
@@ -146,7 +134,7 @@ void jz4740_bandwidth_write32(void *opaque, target_phys_addr_t addr,
struct jz4740_cpm_s
{
target_phys_addr_t base;
- struct jz_state_s *cpu;
+ struct jz_state_s *soc;
uint32_t cpccr;
uint32_t cppcr;
@@ -158,12 +146,12 @@ struct jz4740_cpm_s
uint32_t ssicdr;
};
-static void jz4740_dump_clocks(struct clk *parent)
+static inline void jz4740_dump_clocks(struct clk *parent)
{
struct clk *i = parent;
debug_out(DEBUG_CPM, "clock %x rate 0x%x \n", i->name, i->rate);
- for (i = i->child1; i; i = i->sibling)
+ for (i = clk->child1; i; i = i->sibling)
jz4740_dump_clocks(i);
}
@@ -222,7 +210,7 @@ static inline void jz4740_cpccr_update(struct jz4740_cpm_s *s,
static inline void jz4740_cppcr_update(struct jz4740_cpm_s *s,
uint32_t new_value)
{
- uint32_t pllm, plln, pllod, pllbp, pllen, pllst;
+ uint32_t pllm, plln, pllod, pllbp, pllen, pllst, pllen, pllbp;
uint32_t pll0[4] = { 1, 2, 2, 4 };
@@ -383,14 +371,14 @@ static uint32_t jz474_cpm_read(void *opaque, target_phys_addr_t addr)
static CPUReadMemoryFunc *jz4740_cpm_readfn[] = {
- jz4740_bandwidth_read32,
- jz4740_bandwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
jz474_cpm_read,
};
static CPUWriteMemoryFunc *jz4740_cpm_writefn[] = {
- jz4740_bandwidth_write32,
- jz4740_bandwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
jz4740_cpm_write,
};
@@ -406,51 +394,205 @@ static void jz4740_cpm_reset(struct jz4740_cpm_s *s)
s->ssicdr = 0x00000004;
}
-struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *cpu)
+static struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *soc)
{
int iomemtype;
struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) qemu_mallocz(sizeof(*s));
s->base = JZ4740_PHYS_BASE(JZ4740_CPM_BASE);
+ s->soc = soc;
jz4740_cpm_reset(s);
iomemtype =
cpu_register_io_memory(0, jz4740_cpm_readfn, jz4740_cpm_writefn, s);
cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
-
- return s;
}
-static void jz4740_cpu_reset(void *opaque)
+/* JZ4740 interrupt controller
+ * It issues INT2 to MIPS
+ */
+struct jz4740_intc_s
+{
+ qemu_irq parent_irq;
+
+ target_phys_addr_t base;
+ struct jz_state_s *soc;
+
+ uint32_t icsr;
+ uint32_t icmr;
+ uint32_t icmsr;
+ uint32_t icmcr;
+ uint32_t icpr;
+};
+
+static uint32_t jz4740_intc_read(void *opaque, target_phys_addr_t addr)
+{
+ struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
+ int offset = addr - s->base;
+ switch (offset)
+ {
+ case 0x8:
+ case 0xc:
+ JZ4740_WO_REG(addr);
+ break;
+ case 0x0:
+ return s->icsr;
+ case 0x4:
+ return s->icmr;
+ case 0x10:
+ return s->icpr;
+ default:
+ cpu_abort(s->cpu->env,
+ "jz4740_intc_read undefined addr " JZ_FMT_plx " \n", addr);
+
+ }
+}
+
+static void jz4740_intc_write(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
+ int offset = addr - s->base;
+
+ switch (offset)
+ {
+ case 0x0:
+ case 0x10:
+ JZ4740_RO_REG(addr);
+ break;
+ case 0x4:
+ s->icmr = value ;
+ break;
+ case 0x8:
+ s->icmr |= value;
+ break;
+ case 0xc:
+ s->icmr &= ~value;
+ break;
+ default:
+ cpu_abort(s->cpu->env,
+ "jz4740_intc_write undefined addr value %x" JZ_FMT_plx " \n",
+ addr, value);
+ }
+}
+
+
+static CPUReadMemoryFunc *jz4740_intc_readfn[] = {
+ jz4740_badwidth_read32,
+ jz4740_badwidth_read32,
+ jz4740_intc_read,
+};
+
+static CPUWriteMemoryFunc *jz4740_intc_writefn[] = {
+ jz4740_badwidth_write32,
+ jz4740_badwidth_write32,
+ jz4740_intc_write,
+};
+
+static void jz4740_intc_reset(struct jz4740_intc_s *s)
+{
+ s->icsr = 0x0;
+ s->icmr = 0xffffffff;
+ s->icpr = 0x0;
+}
+
+static void jz4740_set_irq(void *opaque, int irq, int level)
+{
+ struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
+ uint32_t irq_mask = 1<<irq;
+
+ s->icsr |= irq_mask;
+ s->icpr |= irq_mask;
+ s->icpr &= ~s->icmr;
+
+ if ((~s->icmr)&irq_mask)
+ qemu_set_irq(s->parent_irq,1);
+ else
+ qemu_set_irq(s->parent_irq,0);
+}
+
+static qemu_irq *jz4740_intc_init(struct jz_state_s *soc,qemu_irq parent_irq)
+{
+ int iomemtype;
+ struct jz4740_intc_s *s = (struct jz4740_intc_s *) qemu_mallocz(sizeof(*s));
+ s->base = JZ4740_PHYS_BASE(JZ4740_INTC_BASE);
+ s->parent_irq = parent_irq;
+ s->soc = soc;
+
+ jz4740_intc_reset(s);
+
+ iomemtype =
+ cpu_register_io_memory(0, jz4740_intc_readfn, jz4740_intc_writefn, s);
+ cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
+ return qemu_allocate_irqs(jz4740_set_irq, s, 32);
+}
+
+/*external memory controller*/
+struct jz4740_emc_s
+{
+ qemu_irq irq;
+ target_phys_addr_t base;
+ struct jz_state_s *soc;
+
+ uint32_t smcr1; /*0x13010014*/
+ uint32_t smcr2; /*0x13010018*/
+ uint32_t smcr3; /*0x1301001c*/
+ uint32_t smcr4; /*0x13010020*/
+ uint32_t sacr1; /*0x13010034*/
+ uint32_t sacr2; /*0x13010038*/
+ uint32_t sacr3; /*0x1301003c*/
+ uint32_t sacr4; /*0x13010040*/
+
+ uint32_t nfcsr; /*0x13010050*/
+ uint32_t nfeccr; /*0x13010100*/
+ uint32_t nfecc; /*0x13010104*/
+ uint32_t nfpar0; /*0x13010108*/
+ uint32_t nfpar1; /*0x1301010c*/
+ uint32_t nfpar2; /*0x13010110*/
+ uint32_t nfints; /*0x13010114*/
+ uint32_t nfinte; /*0x13010118*/
+ uint32_t nferr0; /*0x1301011c*/
+ uint32_t nferr1; /*0x13010120*/
+ uint32_t nferr2; /*0x13010124*/
+ uint32_t nferr3; /*0x13010128*/
+
+ uint32_t dmcr; /*0x13010080*/
+ uint32_t rtcsr; /*0x13010084*/
+ uint32_t rtcnt; /*0x13010088*/
+ uint32_t rtcor; /*0x1301008c*/
+ uint32_t dmar; /*0x13010090*/
+ uint32_t sdmr; /*0x1301a000*/
+
+};
+
+static void jz4740_emc_init(struct jz_state_s *soc,qemu_irq irq)
{
- fprintf(stderr, "%s: UNIMPLEMENTED!", __FUNCTION__);
+
}
struct jz_state_s *jz4740_init(unsigned long sdram_size,
- DisplayState * ds, const char *core,
- uint32_t osc_extal_freq)
+ uint32_t osc_extal_freq)
{
struct jz_state_s *s = (struct jz_state_s *)
qemu_mallocz(sizeof(struct jz_state_s));
ram_addr_t sram_base, sdram_base;
+ qemu_irq * intc;
s->mpu_model = jz4740;
s->env = cpu_init("jz4740");
+
if (!s->env)
{
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- qemu_register_reset(jz4740_cpu_reset, s->env);
+ qemu_register_reset(main_cpu_reset, env);
s->sdram_size = sdram_size;
s->sram_size = JZ4740_SRAM_SIZE;
- /* Clocks */
- jz_clk_init(s, osc_extal_freq);
-
- /* map sram to 0x80000000 and sdram to 0x80004000 */
+ /*map sram to 0x80000000 and sdram to 0x80004000 */
sram_base = qemu_ram_alloc(s->sram_size);
cpu_register_physical_memory(JZ4740_SRAM_BASE, s->sram_size,
(sram_base | IO_MEM_RAM));
@@ -458,5 +600,19 @@ struct jz_state_s *jz4740_init(unsigned long sdram_size,
cpu_register_physical_memory(JZ4740_SDRAM_BASE, s->sdram_size,
(sdram_base | IO_MEM_RAM));
- return s;
+ /* Init internal devices */
+ cpu_mips_irq_init_cpu(env);
+ cpu_mips_clock_init(env);
+
+
+ /* Clocks */
+ jz_clk_init(s, osc_extal_freq);
+
+ intc = jz4740_intc_init(s,s->env->irq[2]);
+ jz4740_cpm_init(s);
+
+
+
+
+
}
View
55 hw/mips_jz.h
@@ -18,18 +18,17 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
#ifndef _MIPS_JZ_H_
#define _MIPS_JZ_H_
-#include "qemu-common.h"
-#define JZ4740_SRAM_SIZE 0x4000
-#define JZ4740_SRAM_BASE 0x80000000
-#define JZ4740_SDRAM_BASE 0x80004000
-#define JZ4740_ROM_BASE 0xBFC00000
-#define JZ4740_ROM_SIZE 0x1000
+
+
+
+#define JZ4740_SRAM_SIZE 0x4000
+#define JZ4740_SRAM_BASE 0x80000000
+#define JZ4740_SDRAM_BASE 0x80004000
#define JZ4740_PHYS_BASE(a) ((a)-0xa0000000)
@@ -113,9 +112,9 @@
#endif
-#define TCMI_VERBOSE 1
+#define IO_ACCESS_VERBOSE 1
-#ifdef TCMI_VERBOSE
+#ifdef IO_ACCESS_VERBOSE
#define JZ4740_8B_REG(paddr) \
fprintf(stderr, "%s: 8-bit register " JZ_FMT_plx "\n", \
__FUNCTION__, paddr)
@@ -125,10 +124,18 @@
#define JZ4740_32B_REG(paddr) \
fprintf(stderr, "%s: 32-bit register " JZ_FMT_plx "\n", \
__FUNCTION__, paddr)
+#define JZ4740_RO_REG(paddr) \
+ fprintf(stderr, "%s: write to read only 32-bit register " JZ_FMT_plx "\n", \
+ __FUNCTION__, paddr)
+#define JZ4740_WO_REG(paddr) \
+ fprintf(stderr, "%s: read from write only 32-bit register " JZ_FMT_plx "\n", \
+ __FUNCTION__, paddr)
# else
#define JZ4740_8B_REG(paddr)
#define JZ4740_16B_REG(paddr)
#define JZ4740_32B_REG(paddr)
+#define JZ4740_RO_REG(paddr)
+#define JZ4740_WO_REG(paddr)
#endif
@@ -149,6 +156,12 @@ void jz_clk_setrate(jz_clk clk, int divide, int multiply);
int64_t jz_clk_getrate(jz_clk clk);
void jz_clk_reparent(jz_clk clk, jz_clk parent);
+/*mips_jz.c*/
+struct jz_state_s *jz4740_init(unsigned long sdram_size,
+ uint32_t osc_extal_freq);
+struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *soc);
+qemu_irq *jz4740_intc_init(struct jz_state_s *soc,qemu_irq parent_irq);
+
@@ -168,30 +181,8 @@ struct jz_state_s {
unsigned long sdram_size;
unsigned long sram_size;
-
- jz_clk clks;
-};
-struct clk {
- const char *name;
- const char *alias;
- struct clk *parent;
- struct clk *child1;
- struct clk *sibling;
-
- uint32_t flags;
- int id;
- int usecount;
-
- int running; /* Is currently ticking */
- int enabled; /* Is enabled, regardless of its input clk */
- unsigned long rate; /* Current rate (if .running) */
- unsigned int divisor; /* Rate relative to input (if .enabled) */
- unsigned int multiplier; /* Rate relative to input (if .enabled) */
+ jz_clk clks;
};
-struct jz_state_s *jz4740_init(unsigned long sdram_size,
- DisplayState * ds, const char *core,
- uint32_t osc_extal_freq);
-
#endif
View
19 hw/mips_jz_clk.c
@@ -31,6 +31,23 @@
#define CLOCK_IN_JZ4750 (1 << 12)
+struct clk {
+ const char *name;
+ const char *alias;
+ struct clk *parent;
+ struct clk *child1;
+ struct clk *sibling;
+
+ uint32_t flags;
+ int id;
+
+ int running; /* Is currently ticking */
+ int enabled; /* Is enabled, regardless of its input clk */
+ unsigned long rate; /* Current rate (if .running) */
+ unsigned int divisor; /* Rate relative to input (if .enabled) */
+ unsigned int multiplier; /* Rate relative to input (if .enabled) */
+};
+
static struct clk osc_extal = {
.name = "osc_extal_12M",
.rate = 12000000,
@@ -252,7 +269,7 @@ void jz_clk_setrate(struct clk *clk, int divide, int multiply)
jz_clk_rate_update(clk);
}
-int64_t jz_clk_getrate(struct clk *clk)
+int64_t jz_clk_getrate(omap_clk clk)
{
return clk->rate;
}
View
16 hw/mips_pavo.c
@@ -44,20 +44,24 @@
#define PAVO_RAM_SIZE (0x4000000) /*64M */
-
+#define PAVO_OSC_EXTAL (12000000) /*12MHZ*/
/* pavo board support */
struct mips_pavo_s
{
- struct jz_state_s *cpu;
+ struct jz_state_s *soc;
};
+
+
+
+
static
- void mips_pavo_init(ram_addr_t ram_size, int vga_ram_size,
+ void mips_pvao_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -70,7 +74,7 @@ static
PAVO_RAM_SIZE + JZ4740_SRAM_SIZE);
exit(1);
}
- s->cpu = (struct jz_state_s *)jz4740_init(PAVO_RAM_SIZE, NULL, NULL, 12000000);
+ s->soc = jz4740_init(PAVO_RAM_SIZE, PAVO_OSC_EXTAL);
}
@@ -78,9 +82,9 @@ static
QEMUMachine mips_pavo_machine = {
- .name = "pavo",
+ .name = "pvao",
.desc = "JZ Pavo demo board",
- .init = mips_pavo_init,
+ .init = mips_pvao_init,
.ram_require = (JZ4740_SRAM_SIZE + PAVO_RAM_SIZE) | RAMSIZE_FIXED,
.nodisk_ok = 1,
};

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