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Removed "nand_bpage.c": "nand.c" has support for large pages as well.

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1 parent 4722d6a commit 9e6c256e7214404cfc9955adc9b168f5b7b8bfa0 @mthuurne committed Jul 22, 2010
Showing with 33 additions and 506 deletions.
  1. +1 −1 Makefile.target
  2. +0 −12 hw/flash.h
  3. +13 −10 hw/mips_dingoo.c
  4. +13 −10 hw/mips_pavo.c
  5. +6 −0 hw/nand.c
  6. +0 −473 hw/nand_bpage.c
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@@ -215,7 +215,7 @@ obj-ppc-y += ppce500_mpc8544ds.o
obj-ppc-$(CONFIG_KVM) += kvm_ppc.o
obj-ppc-$(CONFIG_FDT) += device_tree.o
-obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o mips_pavo.o mips_dingoo.o nand_bpage.o sd.o
+obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o mips_pavo.o mips_dingoo.o nand.o sd.o
obj-mips-y += mips_jz.o mips_jz_clk.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
obj-mips-y += vga.o i8259.o
View
@@ -27,18 +27,6 @@ void nand_getpins(NANDFlashState *s, int *rb);
void nand_setio(NANDFlashState *s, uint8_t value);
uint8_t nand_getio(NANDFlashState *s);
-/* nand_bpage.c */
-struct nand_bflash_s;
-struct nand_bflash_s *nandb_init(int manf_id, int chip_id);
-void nandb_write_data16(struct nand_bflash_s *s, uint16_t value);
-uint16_t nandb_read_data16(struct nand_bflash_s *s);
-void nandb_write_data8(struct nand_bflash_s *s, uint8_t value);
-uint8_t nandb_read_data8(struct nand_bflash_s *s);
-void nandb_write_address(struct nand_bflash_s *s, uint16_t value);
-void nandb_write_command(struct nand_bflash_s *s, uint16_t value);
-
-
-
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xec
#define NAND_MFR_FUJITSU 0x04
View
@@ -49,7 +49,7 @@
struct mips_dingoo_s {
struct jz_state_s *soc;
- struct nand_bflash_s *nand;
+ NANDFlashState *nand;
};
static uint32_t dingoo_nand_read8(void *opaque, target_phys_addr_t addr)
@@ -59,13 +59,13 @@ static uint32_t dingoo_nand_read8(void *opaque, target_phys_addr_t addr)
switch (addr) {
case 0x8000: /*NAND_COMMAND*/
case 0x10000: /*NAND_ADDRESS*/
- jz4740_badwidth_read8(s,addr);
+ jz4740_badwidth_read8(s, addr);
break;
case 0x0: /*NAND_DATA*/
- return nandb_read_data8(s->nand);
- break;
+ nand_setpins(s->nand, 0, 0, 0, 1, 0);
+ return nand_getio(s->nand);
default:
- jz4740_badwidth_read8(s,addr);
+ jz4740_badwidth_read8(s, addr);
break;
}
return 0;
@@ -80,16 +80,19 @@ static void dingoo_nand_write8(void *opaque, target_phys_addr_t addr,
switch (addr) {
case 0x8000: /*NAND_COMMAND*/
- nandb_write_command(s->nand,value);
+ nand_setpins(s->nand, 1, 0, 0, 1, 0);
+ nand_setio(s->nand, value);
break;
case 0x10000: /*NAND_ADDRESS*/
- nandb_write_address(s->nand,value);
+ nand_setpins(s->nand, 0, 1, 0, 1, 0);
+ nand_setio(s->nand, value);
break;
case 0x0: /*NAND_DATA*/
- nandb_write_data8(s->nand,value);
+ nand_setpins(s->nand, 0, 0, 0, 1, 0);
+ nand_setio(s->nand, value);
break;
default:
- jz4740_badwidth_write8(s,addr,value);
+ jz4740_badwidth_write8(s, addr, value);
break;
}
}
@@ -111,7 +114,7 @@ static void dingoo_nand_setup(struct mips_dingoo_s *s)
int iomemtype;
/* K9LBG08U0M */
- s->nand = nandb_init(NAND_MFR_SAMSUNG, 0xd7);
+ s->nand = nand_init(NAND_MFR_SAMSUNG, 0xd7);
iomemtype = cpu_register_io_memory(dingoo_nand_readfn,
dingoo_nand_writefn, s);
View
@@ -55,7 +55,7 @@
struct mips_pavo_s {
struct jz_state_s *soc;
- struct nand_bflash_s *nand;
+ NANDFlashState *nand;
};
static uint32_t pavo_nand_read8(void *opaque, target_phys_addr_t addr)
@@ -65,13 +65,13 @@ static uint32_t pavo_nand_read8(void *opaque, target_phys_addr_t addr)
switch (addr) {
case 0x8000: /*NAND_COMMAND*/
case 0x10000: /*NAND_ADDRESS*/
- jz4740_badwidth_read8(s,addr);
+ jz4740_badwidth_read8(s, addr);
break;
case 0x0: /*NAND_DATA*/
- return nandb_read_data8(s->nand);
- break;
+ nand_setpins(s->nand, 0, 0, 0, 1, 0);
+ return nand_getio(s->nand);
default:
- jz4740_badwidth_read8(s,addr);
+ jz4740_badwidth_read8(s, addr);
break;
}
return 0;
@@ -86,16 +86,19 @@ static void pavo_nand_write8(void *opaque, target_phys_addr_t addr,
switch (addr) {
case 0x8000: /*NAND_COMMAND*/
- nandb_write_command(s->nand,value);
+ nand_setpins(s->nand, 1, 0, 0, 1, 0);
+ nand_setio(s->nand, value);
break;
case 0x10000: /*NAND_ADDRESS*/
- nandb_write_address(s->nand,value);
+ nand_setpins(s->nand, 0, 1, 0, 1, 0);
+ nand_setio(s->nand, value);
break;
case 0x0: /*NAND_DATA*/
- nandb_write_data8(s->nand,value);
+ nand_setpins(s->nand, 0, 0, 0, 1, 0);
+ nand_setio(s->nand, value);
break;
default:
- jz4740_badwidth_write8(s,addr,value);
+ jz4740_badwidth_write8(s, addr, value);
break;
}
}
@@ -117,7 +120,7 @@ static void pavo_nand_setup(struct mips_pavo_s *s)
int iomemtype;
/*K9K8G08U0*/
- s->nand = nandb_init(NAND_MFR_SAMSUNG,0xd3);
+ s->nand = nand_init(NAND_MFR_SAMSUNG, 0xd3);
iomemtype = cpu_register_io_memory(pavo_nand_readfn, pavo_nand_writefn, s);
cpu_register_physical_memory(0x18000000, 0x20000, iomemtype);
View
@@ -197,6 +197,12 @@ static const struct {
[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
+
+ /* 32 Gigabit */
+ [0xa7] = { 4096, 8, 0, 0, LP_OPTIONS },
+ [0xd7] = { 4096, 8, 0, 0, LP_OPTIONS },
+ [0xb7] = { 4096, 16, 0, 0, LP_OPTIONS16 },
+ [0xc7] = { 4096, 16, 0, 0, LP_OPTIONS16 },
};
static void nand_reset(NANDFlashState *s)
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