HACK: mediatek: snfi: adjust pin drive strength for Fidelix SPI-NAND

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
mtk-openwrt · Mar 10, 2024 · 783c1b2 · 783c1b2
1 parent fb2a2b6
commit 783c1b2
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diff --git a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
@@ -86,13 +86,20 @@ struct snand_mem_org {
 
 typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
 
+enum snand_drv {
+	SNAND_DRV_NO_CHANGE = 0,
+	SNAND_DRV_4mA = 4,
+	SNAND_DRV_8mA = 8,
+};
+
 struct snand_flash_info {
 	const char *model;
 	struct snand_id id;
 	const struct snand_mem_org memorg;
 	const struct snand_io_cap *cap_rd;
 	const struct snand_io_cap *cap_pl;
 	snand_select_die_t select_die;
+	enum snand_drv drv;
 };
 
 #define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \

diff --git a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
@@ -424,7 +424,9 @@ static const struct snand_flash_info snand_flash_ids[] = {
 	SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
 		   SNAND_MEMORG_1G_2K_64,
 		   &snand_cap_read_from_cache_x4_only,
-		   &snand_cap_program_load_x4),
+		   &snand_cap_program_load_x4,
+		   NULL,
+		   SNAND_DRV_8mA),
 
 	SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
 		   SNAND_MEMORG_1G_2K_128,

diff --git a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
@@ -1845,6 +1845,33 @@ static int mtk_snand_id_probe(struct mtk_snand *snf,
 	return -EINVAL;
 }
 
+#define GPIO_BASE    (void *)0x10211000
+#define GPIO_DRIV(x) (GPIO_BASE + 0x900 + 0x10 * x)
+
+void mtk_snand_adjust_drive(void *dev, enum snand_drv drv)
+{
+	uint32_t e4, e8;
+
+	e4 = readl(GPIO_DRIV(6)) & ~(0x3f00);
+	e8 = readl(GPIO_DRIV(7)) & ~(0x3f00);
+
+	switch (drv) {
+	case SNAND_DRV_4mA:
+		e4 |= 0x3f00;
+		break;
+	case SNAND_DRV_8mA:
+		e8 |= 0x3f00;
+		break;
+	default:
+		return;
+	}
+
+	snand_log_chip(dev, "adjusting SPI-NAND pin drive strength to %umA\n", drv);
+
+	writel(e4, GPIO_DRIV(6));
+	writel(e8, GPIO_DRIV(7));
+}
+
 int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
 		   struct mtk_snand **psnf)
 {
@@ -1888,6 +1915,9 @@ int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
 	if (ret)
 		return ret;
 
+	if (snand_info->drv)
+		mtk_snand_adjust_drive(dev, snand_info->drv);
+
 	rawpage_size = snand_info->memorg.pagesize +
 		       snand_info->memorg.sparesize;