{"payload":{"header_redesign_enabled":false,"results":[{"id":"675607476","archived":false,"color":"#b2b7f8","followers":1,"has_funding_file":false,"hl_name":"muhammadtalhasami/verilog_practice","hl_trunc_description":"Verilog is a hardware description language. This repo is basically a learning journey of verilog ","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":675607476,"name":"verilog_practice","owner_id":141629485,"owner_login":"muhammadtalhasami","updated_at":"2023-08-21T07:16:33.717Z","has_issues":true}},"sponsorable":false,"topics":["design","vhdl","hardware-designs","gtkwave","testbench","verilog-"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":112,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amuhammadtalhasami%252Fverilog_practice%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/muhammadtalhasami/verilog_practice/star":{"post":"pQvT2Yaey-IlGRxDrmj6IasBqWEgGGeX8NhvY_JuKimya7eF8cPKxXPSCw_Qq1T2WobYWIc4iThJ0RbcI7EIJw"},"/muhammadtalhasami/verilog_practice/unstar":{"post":"aesP-hyVpp9xPMvyXlghVDwbaUPxYAFSn11yEXvQKGw7sQ9pIS0_x1dCnopfk-9xYixLtQJyiAWuAf1BsdWXsQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"moxuur23KmC58J6JJZ-i5u8K2mdXV6nPQWC9kpGrQuF-HKtu0dhmRXoUwS7_kg4KFJaj4tjUb_6RgHDWdCmNHQ"}}},"title":"Repository search results"}