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mmu wip #9

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1 parent f7ca524 commit 99e6157e87848b1329d3c831066017415eed8d38 @mwalle committed Feb 14, 2013
Showing with 67 additions and 38 deletions.
  1. +6 −7 target-lm32/cpu.h
  2. +39 −9 target-lm32/helper.c
  3. +4 −4 tests/tcg/lm32/crt.S
  4. +18 −18 tests/tcg/lm32/test_mmu.S
View
@@ -54,8 +54,8 @@ enum {
EXCP_DIVIDE_BY_ZERO,
EXCP_IRQ,
EXCP_SYSTEMCALL,
- EXCP_DTLB_MISS,
EXCP_ITLB_MISS,
+ EXCP_DTLB_MISS,
EXCP_DTLB_FAULT,
EXCP_PRIVILEGE,
};
@@ -131,7 +131,7 @@ enum {
PSW_BUSR = (1<<11),
};
-/* TLB commands */
+/* TLB commands in TLBVADDR register */
enum {
ITLB_NOP = 0x00,
DTLB_NOP = 0x01,
@@ -165,8 +165,9 @@ enum {
CSR_WP2 = 0x1a,
CSR_WP3 = 0x1b,
CSR_PSW = 0x1d,
- CSR_TLBVADDR = 0x1e,
- CSR_TLBPADDR = 0x1f,
+ CSR_TLBVADDR = 0x1e,
+ CSR_TLBPADDR = 0x1f, /* write only */
+ CSR_TLBBADVADDR = 0x1f, /* read only */
};
enum {
@@ -189,9 +190,7 @@ struct tlb_t {
target_ulong vaddr;
target_ulong paddr;
uint_fast8_t valid:1;
- uint_fast8_t x:1;
- uint_fast8_t w:1;
- uint_fast8_t r:1;
+ uint_fast8_t ro:1; /* only valid for DTLB entries */
};
#define LM32_TLB_ENTRIES 1024
View
@@ -24,12 +24,11 @@ static int get_physical_address(CPULM32State *env,
target_phys_addr_t *physical, int *prot, target_ulong address, int rw)
{
int idx;
- int ret = 1;
bool dtlb = (rw != 2);
bool tlb_enabled = (dtlb) ? env->psw & PSW_DTLB : env->psw & PSW_ITLB;
tlb_t *tlb;
- *prot = PAGE_BITS;
+ *prot = 0;
if (env->features & LM32_FEATURE_MMU && tlb_enabled) {
idx = mmu_tlb_index(env, address);
@@ -40,20 +39,43 @@ static int get_physical_address(CPULM32State *env,
tlb = &env->mmu.itlb[idx];
}
- if (tlb->valid && ((tlb->vaddr ^ address) & 0xffc00000) == 0) {
- /* XXX: add offset within page */
- *physical = tlb->paddr;
- ret = 0;
+ if (!tlb->valid) {
+ /* TLB entry not valid */
+ goto tlb_miss;
+ }
+
+ if (((tlb->vaddr ^ address) & 0xffc00000) != 0) {
+ /* TLB frame number mismatch */
+ goto tlb_miss;
+ }
+
+ /* for all ITLB entries ro == 0 */
+ if (tlb->ro && rw == 1) {
+ goto tlb_fault;
+ }
+
+ *physical = tlb->paddr;
+ if (dtlb) {
+ if (tlb->ro) {
+ *prot = PAGE_READ;
+ } else {
+ *prot = PAGE_READ | PAGE_WRITE;
+ }
} else {
- ret = 1;
+ *prot = PAGE_EXEC /* | PAGE_READ */;
}
} else {
/* mmu not available or disabled */
*physical = address;
- ret = 0;
+ *prot = PAGE_BITS;
}
- return ret;
+ return 0;
+
+tlb_miss:
+ return 1;
+tlb_fault:
+ return 2;
}
void mmu_fill_tbl(CPULM32State *env, tlb_t *tlb)
@@ -62,6 +84,7 @@ void mmu_fill_tbl(CPULM32State *env, tlb_t *tlb)
tlb[idx].vaddr = env->tlbvaddr & TARGET_PAGE_MASK;
tlb[idx].paddr = env->tlbpaddr & TARGET_PAGE_MASK;
tlb[idx].valid = 1;
+ tlb[idx].ro = !!(env->tlbpaddr & 2);
tlb_flush_page(env, env->tlbvaddr);
}
@@ -84,6 +107,13 @@ void mmu_invalidate_tlb(CPULM32State *env, tlb_t *tlb)
static void raise_mmu_exception(CPULM32State *env, target_ulong address, int rw)
{
env->tlbvaddr = address;
+ if (rw == 0) {
+ env->tlbvaddr |= 1;
+ env->exception_index = EXCP_DTLB_MISS;
+ } else if (rw == 1) {
+ env->tlbvaddr |= 1;
+ env->exception_index = EXCP_DTLB_MISS;
+ }
if (rw != 2) {
/* dtlb */
env->tlbvaddr |= 1;
View
@@ -82,25 +82,25 @@ _system_call_handler:
nop
nop
-_dtlb_miss_handler:
+_itlb_miss_handler:
ori r25, r25, 128
rcsr r24, TLBVADDR
- addi ra, ea, 4
ret
nop
nop
nop
nop
+ nop
-_itlb_miss_handler:
+_dtlb_miss_handler:
ori r25, r25, 256
rcsr r24, TLBVADDR
+ addi ra, ea, 4
ret
nop
nop
nop
nop
- nop
_dtlb_fault_handler:
ori r25, r25, 512
View
@@ -28,30 +28,30 @@ test_name MMU_DTLB_ON
test_name MMU_DTLB_MISS_1
calli enable_dtlb
1:
- lw r3, (r1+0x1004)
+ lb r3, (r1+0x1fff)
calli disable_dtlb
- check_excp 128
+ check_excp 256
test_name MMU_DTLB_MISS_2
check_reg ea 1b
test_name MMU_DTLB_MISS_3
- check_reg r24 data2+0x1004+1
+ check_reg r24 data2+0x1000+1 # page mask already applied
test_name MMU_DTLB_MISS_4
calli enable_dtlb
lw r3, (r1+0x1004)
lw r3, (r1+0x1004)
calli disable_dtlb
- check_excp 128
+ check_excp 256
test_name MMU_DTLB_MISS_5
calli enable_dtlb
mvi r3, 0x1234
sw (r1+4), r3
lw r3, (r1+0x1004)
calli disable_dtlb
- check_excp 128
+ check_excp 256
test_name MMU_DTLB_MISS_6
lw r3, (r2+4)
@@ -77,7 +77,7 @@ test_name MMU_DTLB_UPDATE_2
lw r3, (r1+0) # A load
wcsr TLBPADDR, r11 # .. directly followed an TLB update
calli disable_dtlb
- check_excp 128
+ check_excp 256
test_name MMU_DTLB_FAULT_1
calli flush_dtlb
@@ -103,7 +103,7 @@ test_name MMU_DTLB_FAULT_3
check_reg ea 1b
test_name MMU_DTLB_FAULT_4
- check_reg r24 data2
+ check_reg r24 data2+1 # page mask already applied
test_name MMU_DTLB_CACHE_INHIBIT_1
mvhi r3, 0xaa55 # this is a test for the test below :)
@@ -160,7 +160,7 @@ test_name MMU_DTLB_FLUSH
calli flush_dtlb
lw r3, (r1+0)
calli disable_dtlb
- check_excp 128
+ check_excp 256
test_name MMU_DTLB_INV
mvhi r1, hi(data2)
@@ -173,7 +173,7 @@ test_name MMU_DTLB_INV
calli invalidate_dtlb
lw r3, (r1+0)
calli disable_dtlb
- check_excp 128
+ check_excp 256
# make sure we have a mapping for the current code
mvhi r1, hi(initial_page)
@@ -207,27 +207,27 @@ test_name MMU_ITLB_CACHE_ALIAS
test_name MMU_ITLB_MISS_1
calli enable_itlb
- calli code2+0x1004
- check_excp 256
+ calli code2+0x1ffc
+ check_excp 128
test_name MMU_ITLB_MISS_2
- check_reg ea code2+0x1004
+ check_reg ea code2+0x1ffc
test_name MMU_ITLB_MISS_3
- check_reg r24 code2+0x1004
+ check_reg r24 code2+0x1000 # page mask already applied
test_name MMU_ITLB_MISS_4
calli flush_dcache
calli enable_itlb
lw r1, (r0+0) # provoke data cache restart request
calli code2+0x1004
- check_excp 256
+ check_excp 128
test_name MMU_ITLB_MISS_5
calli flush_icache
calli enable_itlb
calli code2+0x1004 # provoke instruction cache restart request
- check_excp 256
+ check_excp 128
test_name MMU_ITLB_INV
mvhi r1, hi(code2)
@@ -239,7 +239,7 @@ test_name MMU_ITLB_INV
ori ra, ra, lo(1f)
bi code2
1:
- check_excp 256
+ check_excp 128
test_name MMU_ITLB_FLUSH
calli flush_itlb
@@ -248,13 +248,13 @@ test_name MMU_ITLB_FLUSH
ori r1, r1, lo(initial_page)
mv r2, r1
calli update_itlb
-
+
calli enable_itlb
mvhi ra, hi(1f)
ori ra, ra, lo(1f)
bi code1
1:
- check_excp 256
+ check_excp 128
test_name MMU_ITLB_EXCEPTION_1
calli enable_itlb

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