From 154d0ec9837f541ff8ae2eb517e406100edb3ee3 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:11:48 -0500 Subject: [PATCH 01/31] fix isinstance long, int checks for python3 --- myhdl/_Signal.py | 8 +++++--- myhdl/_compat.py | 9 +++++++++ myhdl/_concat.py | 5 ++++- myhdl/_delay.py | 4 +++- myhdl/_intbv.py | 8 +++++--- myhdl/_util.py | 3 ++- myhdl/conversion/_toVHDL.py | 8 +++++--- myhdl/conversion/_toVerilog.py | 8 +++++--- myhdl/test/core/test_intbv.py | 4 +++- 9 files changed, 41 insertions(+), 16 deletions(-) create mode 100644 myhdl/_compat.py diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py index b419f0ed2..ce112a989 100644 --- a/myhdl/_Signal.py +++ b/myhdl/_Signal.py @@ -33,10 +33,12 @@ from copy import copy, deepcopy import operator +from myhdl._compat import integer_types from myhdl import _simulator as sim from myhdl._simulator import _signals, _siglist, _futureEvents, now from myhdl._intbv import intbv from myhdl._bin import bin + # from myhdl._enum import EnumItemType _schedule = _futureEvents.append @@ -136,8 +138,8 @@ def __init__(self, val=None): self._setNextVal = self._setNextBool self._printVcd = self._printVcdBit self._nrbits = 1 - elif isinstance(val, (int, long)): - self._type = (int, long) + elif isinstance(val, integer_types): + self._type = integer_types self._setNextVal = self._setNextInt elif isinstance(val, intbv): self._type = intbv @@ -280,7 +282,7 @@ def _setNextInt(self, val): def _setNextIntbv(self, val): if isinstance(val, intbv): val = val._val - elif not isinstance(val, (int, long)): + elif not isinstance(val, integer_types): raise TypeError("Expected int or intbv, got %s" % type(val)) self._next._val = val self._next._handleBounds() diff --git a/myhdl/_compat.py b/myhdl/_compat.py new file mode 100644 index 000000000..2a936c0b0 --- /dev/null +++ b/myhdl/_compat.py @@ -0,0 +1,9 @@ +import sys + +PY2 = sys.version_info[0] == 2 + + +if not PY2: + integer_types = (int,) +else: + integer_types = (int, long) diff --git a/myhdl/_concat.py b/myhdl/_concat.py index 0c758dbd5..36d1aef79 100644 --- a/myhdl/_concat.py +++ b/myhdl/_concat.py @@ -22,15 +22,18 @@ """ from __future__ import absolute_import +from myhdl._compat import integer_types from myhdl._intbv import intbv from myhdl._Signal import _Signal + + def concat(base, *args): if isinstance(base, intbv): basewidth = base._nrbits val = base._val - elif isinstance(base, (int, long)): + elif isinstance(base, integer_types): if isinstance(base, bool): basewidth = 1 else: diff --git a/myhdl/_delay.py b/myhdl/_delay.py index 40a3f9476..35589adcc 100644 --- a/myhdl/_delay.py +++ b/myhdl/_delay.py @@ -18,7 +18,9 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the delay class.""" +from __future__ import absolute_import +from myhdl._compat import integer_types _errmsg = "arg of delay constructor should be a natural integeer" @@ -33,6 +35,6 @@ def __init__(self, val): val -- a natural integer representing the desired delay """ - if not isinstance(val, (int, long)) or val < 0: + if not isinstance(val, integer_types) or val < 0: raise TypeError(_errmsg) self._time = val diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 4cf6f0873..89ed70079 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -19,6 +19,7 @@ """ Module with the intbv class """ from __future__ import absolute_import +from __builtin__ import max as maxfunc @@ -27,9 +28,10 @@ from types import StringType import operator +from myhdl._compat import integer_types from myhdl._bin import bin -from __builtin__ import max as maxfunc + class intbv(object): #__slots__ = ('_val', '_min', '_max', '_nrbits', '_handleBounds') @@ -49,7 +51,7 @@ def __init__(self, val=0, min=None, max=None, _nrbits=0): else: # make sure there is a leading zero bit in positive numbers _nrbits = maxfunc(len(bin(max-1))+1, len(bin(min))) - if isinstance(val, (int, long)): + if isinstance(val, integer_types): self._val = val elif isinstance(val, StringType): mval = val.replace('_', '') @@ -356,7 +358,7 @@ def __ipow__(self, other, modulo=None): self._val **= other._val else: self._val **= other - if not isinstance(self._val, (int, long)): + if not isinstance(self._val, integer_types): raise ValueError("intbv value should be integer") self._handleBounds() return self diff --git a/myhdl/_util.py b/myhdl/_util.py index 8149aa9a5..35a9e635c 100644 --- a/myhdl/_util.py +++ b/myhdl/_util.py @@ -31,6 +31,7 @@ from tokenize import generate_tokens, untokenize, INDENT from cStringIO import StringIO +from myhdl._compat import integer_types def _printExcInfo(): kind, value = sys.exc_info()[:2] @@ -58,7 +59,7 @@ def _isTupleOfInts(obj): if not isinstance(obj, tuple): return False for e in obj: - if not isinstance(e, (int, long)): + if not isinstance(e, integer_types): return False return True diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 3fddfe457..02ee3c95d 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -41,6 +41,7 @@ import myhdl from myhdl import * +from myhdl._compat import integer_types from myhdl import ToVHDLError, ToVHDLWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVhdlCode, _userCodeMap) @@ -53,6 +54,7 @@ from myhdl._Signal import _Signal,_WaiterList from myhdl.conversion._toVHDLPackage import _package + _version = myhdl.__version__.replace('.','') _shortversion = _version.replace('dev','') _converting = 0 @@ -950,7 +952,7 @@ def visit_Call(self, node): self.raiseError(node, _error.UnsupportedType, "Strings with length > 1" ) else: node.args[0].s = ord(node.args[0].s) - elif f in (int, long): + elif f in integer_types: opening, closing = '', '' # convert number argument to integer if isinstance(node.args[0], ast.Num): @@ -1288,7 +1290,7 @@ def getName(self, node): if n in _constDict and obj == _constDict[n]: if isinstance(node.vhd, vhd_boolean): s = "bool(%s)" % n - elif isinstance(obj, (int, long)): + elif isinstance(obj, integer_types): # print the symbol for an integer in the global constant dict if n in _constDict and obj == _constDict[n]: assert abs(obj) < 2**31 @@ -1987,7 +1989,7 @@ def inferVhdlObj(obj): else: tipe = obj._type vhd = vhd_enum(tipe) - elif isinstance(obj, (int, long)): + elif isinstance(obj, integer_types): if obj >= 0: vhd = vhd_nat() else: diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 9a65d357b..1ff43ca7e 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -39,6 +39,7 @@ import myhdl from myhdl import * +from myhdl._compat import integer_types from myhdl import ToVerilogError, ToVerilogWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVerilogCode, _userCodeMap) @@ -50,6 +51,7 @@ _Ram, _Rom) from myhdl._Signal import _Signal + _converting = 0 _profileFunc = None @@ -730,7 +732,7 @@ def visit_Call(self, node): self.raiseError(node, _error.UnsupportedType, "Strings with length > 1") else: node.args[0].s = str(ord(node.args[0].s)) - elif f in (int, long): + elif f in integer_types: opening, closing = '', '' # convert number argument to integer if isinstance(node.args[0], ast.Num): @@ -1004,7 +1006,7 @@ def getName(self, node): obj = self.tree.symdict[n] if isinstance(obj, bool): s = "%s" % int(obj) - elif isinstance(obj, (int, long)): + elif isinstance(obj, integer_types): s = self.IntRepr(obj) elif isinstance(obj, _Signal): addSignBit = isMixedExpr @@ -1427,7 +1429,7 @@ def visit_FunctionDef(self, node): def _maybeNegative(obj): if hasattr(obj, '_min') and (obj._min is not None) and (obj._min < 0): return True - if isinstance(obj, (int, long)) and obj < 0: + if isinstance(obj, integer_types) and obj < 0: return True return False diff --git a/myhdl/test/core/test_intbv.py b/myhdl/test/core/test_intbv.py index 091e2d958..4eba47d56 100644 --- a/myhdl/test/core/test_intbv.py +++ b/myhdl/test/core/test_intbv.py @@ -33,6 +33,8 @@ from myhdl._intbv import intbv +from myhdl._compat import integer_types + class TestIntbvInit(TestCase): def testDefaultValue(self): self.assertEqual(intbv(), 0) @@ -493,7 +495,7 @@ def checkBounds(self, i, j, op): exec("a %s long(j)" % op) except (ZeroDivisionError, ValueError): return # prune - if not isinstance(a._val, (int, long)): + if not isinstance(a._val, integer_types): return # prune if abs(a) > maxint * maxint: return # keep it reasonable From 43b0653c8f7d4b4c63113d4a5e7603d93ce0dcb9 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:23:42 -0500 Subject: [PATCH 02/31] Add compatibility layer for dealing with long --- myhdl/_compat.py | 2 ++ myhdl/_concat.py | 2 +- myhdl/_intbv.py | 16 ++++++++-------- myhdl/_modbv.py | 2 +- myhdl/test/core/test_intbv.py | 2 +- 5 files changed, 13 insertions(+), 11 deletions(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index 2a936c0b0..3b06fdd94 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -5,5 +5,7 @@ if not PY2: integer_types = (int,) + long = int else: integer_types = (int, long) + long = long diff --git a/myhdl/_concat.py b/myhdl/_concat.py index 36d1aef79..6be595a58 100644 --- a/myhdl/_concat.py +++ b/myhdl/_concat.py @@ -75,7 +75,7 @@ def concat(base, *args): if not w: raise TypeError("concat: arg on pos %d should have length" % (i+1)) width += w - val = val << w | v & (1L << w)-1 + val = val << w | v & (long(1) << w)-1 if basewidth: return intbv(val, _nrbits=basewidth + width) diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 89ed70079..7aa2c10bc 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -28,7 +28,7 @@ from types import StringType import operator -from myhdl._compat import integer_types +from myhdl._compat import long, integer_types from myhdl._bin import bin @@ -147,7 +147,7 @@ def __getitem__(self, key): if i <= j: raise ValueError("intbv[i:j] requires i > j\n" \ " i, j == %s, %s" % (i, j)) - res = intbv((self._val & (1L << i)-1) >> j, _nrbits=i-j) + res = intbv((self._val & (long(1) << i)-1) >> j, _nrbits=i-j) return res else: i = int(key) @@ -168,15 +168,15 @@ def __setitem__(self, key, val): raise ValueError("intbv[i:j] = v requires j >= 0\n" \ " j == %s" % j) if i is None: # default - q = self._val % (1L << j) - self._val = val * (1L << j) + q + q = self._val % (long(1) << j) + self._val = val * (long(1) << j) + q self._handleBounds() return i = int(i) if i <= j: raise ValueError("intbv[i:j] = v requires i > j\n" \ " i, j, v == %s, %s, %s" % (i, j, val)) - lim = (1L << (i-j)) + lim = (long(1) << (i-j)) if val >= lim or val < -lim: raise ValueError("intbv[i:j] = v abs(v) too large\n" \ " i, j, v == %s, %s, %s" % (i, j, val)) @@ -187,9 +187,9 @@ def __setitem__(self, key, val): else: i = int(key) if val == 1: - self._val |= (1L << i) + self._val |= (long(1) << i) elif val == 0: - self._val &= ~(1L << i) + self._val &= ~(long(1) << i) else: raise ValueError("intbv[i] = v requires v in (0, 1)\n" \ " i == %s " % i) @@ -415,7 +415,7 @@ def __abs__(self): def __invert__(self): if self._nrbits and self._min >= 0: - return type(self)(~self._val & (1L << self._nrbits)-1) + return type(self)(~self._val & (long(1) << self._nrbits)-1) else: return type(self)(~self._val) diff --git a/myhdl/_modbv.py b/myhdl/_modbv.py index 0959405d4..685d710f5 100644 --- a/myhdl/_modbv.py +++ b/myhdl/_modbv.py @@ -53,7 +53,7 @@ def __getitem__(self, key): if i <= j: raise ValueError("modbv[i:j] requires i > j\n" \ " i, j == %s, %s" % (i, j)) - res = modbv((self._val & (1L << i)-1) >> j, _nrbits=i-j) + res = modbv((self._val & (long(1) << i)-1) >> j, _nrbits=i-j) return res else: i = int(key) diff --git a/myhdl/test/core/test_intbv.py b/myhdl/test/core/test_intbv.py index 4eba47d56..c2d9b9ba3 100644 --- a/myhdl/test/core/test_intbv.py +++ b/myhdl/test/core/test_intbv.py @@ -33,7 +33,7 @@ from myhdl._intbv import intbv -from myhdl._compat import integer_types +from myhdl._compat import long, integer_types class TestIntbvInit(TestCase): def testDefaultValue(self): From 9e756bfbf9d2b4b51f9de85bf2dca4e494bd325b Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:39:42 -0500 Subject: [PATCH 03/31] add builtins to _compat --- myhdl/_compat.py | 2 ++ myhdl/_intbv.py | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index 3b06fdd94..a5c4b1643 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -6,6 +6,8 @@ if not PY2: integer_types = (int,) long = int + import builtins else: integer_types = (int, long) long = long + import __builtin__ as builtins diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 7aa2c10bc..c0dad1810 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -19,9 +19,6 @@ """ Module with the intbv class """ from __future__ import absolute_import -from __builtin__ import max as maxfunc - - import sys maxint = sys.maxint @@ -29,6 +26,7 @@ import operator from myhdl._compat import long, integer_types +from myhdl._compat.builtins import max as maxfunc from myhdl._bin import bin From 9887ad342768fc217469e77e82cad414a8c7705c Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:44:22 -0500 Subject: [PATCH 04/31] add string_types to _compat --- myhdl/_compat.py | 2 ++ myhdl/_enum.py | 5 ++--- myhdl/_intbv.py | 5 ++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index a5c4b1643..13a4d71cd 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -4,10 +4,12 @@ if not PY2: + string_types = (str, unicode) integer_types = (int,) long = int import builtins else: + str_types = (str,) integer_types = (int, long) long = long import __builtin__ as builtins diff --git a/myhdl/_enum.py b/myhdl/_enum.py index 02bc7a3d7..b4ed2a724 100644 --- a/myhdl/_enum.py +++ b/myhdl/_enum.py @@ -23,10 +23,9 @@ from __future__ import absolute_import -from types import StringType - from myhdl._bin import bin from myhdl._Signal import _Signal +from myhdl._compat import string_types class EnumType(object): def __init__(self): @@ -53,7 +52,7 @@ def enum(*names, **kwargs): codedict = {} i = 0 for name in names: - if not isinstance(name, StringType): + if not isinstance(name, string_types): raise TypeError() if codedict.has_key(name): raise ValueError("enum literals should be unique") diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index c0dad1810..b2f65e91c 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -22,10 +22,9 @@ import sys maxint = sys.maxint -from types import StringType import operator -from myhdl._compat import long, integer_types +from myhdl._compat import long, integer_types, string_types from myhdl._compat.builtins import max as maxfunc from myhdl._bin import bin @@ -51,7 +50,7 @@ def __init__(self, val=0, min=None, max=None, _nrbits=0): _nrbits = maxfunc(len(bin(max-1))+1, len(bin(min))) if isinstance(val, integer_types): self._val = val - elif isinstance(val, StringType): + elif isinstance(val, string_types): mval = val.replace('_', '') self._val = long(mval, 2) _nrbits = len(mval) From 1c3a05d070eba71e7c4e48b777c356c773dbbf75 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:46:25 -0500 Subject: [PATCH 05/31] fix builtins import --- myhdl/_intbv.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index b2f65e91c..728f091e8 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -24,8 +24,7 @@ maxint = sys.maxint import operator -from myhdl._compat import long, integer_types, string_types -from myhdl._compat.builtins import max as maxfunc +from myhdl._compat import long, integer_types, string_types, builtins from myhdl._bin import bin @@ -47,7 +46,7 @@ def __init__(self, val=0, min=None, max=None, _nrbits=0): _nrbits = len(bin(min)) else: # make sure there is a leading zero bit in positive numbers - _nrbits = maxfunc(len(bin(max-1))+1, len(bin(min))) + _nrbits = builtins.max(len(bin(max-1))+1, len(bin(min))) if isinstance(val, integer_types): self._val = val elif isinstance(val, string_types): From a8def5451a1e8d655c3c3969a70a6ba6e8e98407 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:48:42 -0500 Subject: [PATCH 06/31] fix typo in _compat --- myhdl/_compat.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index 13a4d71cd..029d6ea25 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -9,7 +9,7 @@ long = int import builtins else: - str_types = (str,) + string_types = (str,) integer_types = (int, long) long = long import __builtin__ as builtins From d9e7105550a3d8dd54a1217045a3708c1345531e Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:51:18 -0500 Subject: [PATCH 07/31] fix string_types in _compat --- myhdl/_compat.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index 029d6ea25..382e3f00c 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -4,12 +4,12 @@ if not PY2: - string_types = (str, unicode) + string_types = (str,) integer_types = (int,) long = int import builtins else: - string_types = (str,) + string_types = (str, unicode) integer_types = (int, long) long = long import __builtin__ as builtins From 475b3e7e48d95074f18c0475fedd8c5192a677af Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:52:36 -0500 Subject: [PATCH 08/31] remove unused import, var --- myhdl/_intbv.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 728f091e8..bc80b6972 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -20,8 +20,6 @@ """ Module with the intbv class """ from __future__ import absolute_import -import sys -maxint = sys.maxint import operator from myhdl._compat import long, integer_types, string_types, builtins From ebeb57ea22459ab986ddc9c92750b0c024427f4a Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 18:55:13 -0500 Subject: [PATCH 09/31] move StringIO to compat --- myhdl/_compat.py | 4 ++++ myhdl/_unparse.py | 2 +- myhdl/_util.py | 3 +-- myhdl/conversion/_toVHDL.py | 3 +-- myhdl/conversion/_toVerilog.py | 2 +- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index 382e3f00c..2f6a3a8e1 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -7,9 +7,13 @@ string_types = (str,) integer_types = (int,) long = int + + from io import StringIO import builtins else: string_types = (str, unicode) integer_types = (int, long) long = long + + from cStringIO import StringIO import __builtin__ as builtins diff --git a/myhdl/_unparse.py b/myhdl/_unparse.py index a1eef8daf..f4e3eb649 100644 --- a/myhdl/_unparse.py +++ b/myhdl/_unparse.py @@ -24,7 +24,7 @@ import compiler -from cStringIO import StringIO +from myhdl._compat import StringIO def _unparse(ast): v = _UnparseVisitor() diff --git a/myhdl/_util.py b/myhdl/_util.py index 35a9e635c..01b0b7928 100644 --- a/myhdl/_util.py +++ b/myhdl/_util.py @@ -29,9 +29,8 @@ import inspect from tokenize import generate_tokens, untokenize, INDENT -from cStringIO import StringIO -from myhdl._compat import integer_types +from myhdl._compat import integer_types, StringIO def _printExcInfo(): kind, value = sys.exc_info()[:2] diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 02ee3c95d..b0cf7a184 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -34,14 +34,13 @@ #from compiler import ast as astNode import ast from types import GeneratorType, ClassType -from cStringIO import StringIO import warnings from copy import copy import string import myhdl from myhdl import * -from myhdl._compat import integer_types +from myhdl._compat import integer_types, StringIO from myhdl import ToVHDLError, ToVHDLWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVhdlCode, _userCodeMap) diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 1ff43ca7e..b88df033c 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -34,7 +34,7 @@ import string from types import GeneratorType, ClassType, TypeType -from cStringIO import StringIO +from myhdl._compat import StringIO import warnings import myhdl From cb4785ada71bda81cf0f665fc3791e6da539e536 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 19:34:23 -0500 Subject: [PATCH 10/31] move classtype to compat --- myhdl/_compat.py | 3 +++ myhdl/conversion/_toVHDL.py | 8 ++++---- myhdl/conversion/_toVerilog.py | 8 ++++---- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/myhdl/_compat.py b/myhdl/_compat.py index 2f6a3a8e1..2761b3bad 100644 --- a/myhdl/_compat.py +++ b/myhdl/_compat.py @@ -1,4 +1,5 @@ import sys +import types PY2 = sys.version_info[0] == 2 @@ -7,6 +8,7 @@ string_types = (str,) integer_types = (int,) long = int + class_types = (type,) from io import StringIO import builtins @@ -14,6 +16,7 @@ string_types = (str, unicode) integer_types = (int, long) long = long + class_types = (type, types.ClassType) from cStringIO import StringIO import __builtin__ as builtins diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index b0cf7a184..078f7cb04 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -33,14 +33,14 @@ #import compiler #from compiler import ast as astNode import ast -from types import GeneratorType, ClassType +from types import GeneratorType import warnings from copy import copy import string import myhdl from myhdl import * -from myhdl._compat import integer_types, StringIO +from myhdl._compat import integer_types, class_types, StringIO from myhdl import ToVHDLError, ToVHDLWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVhdlCode, _userCodeMap) @@ -980,7 +980,7 @@ def visit_Call(self, node): self.write(closing) self.write(suf) return - elif type(f) is ClassType and issubclass(f, Exception): + elif (type(f) in class_types) and issubclass(f, Exception): self.write(f.__name__) elif f in (posedge, negedge): opening, closing = ' ', '' @@ -1336,7 +1336,7 @@ def getName(self, node): s = m.name elif isinstance(obj, EnumItemType): s = obj._toVHDL() - elif type(obj) is ClassType and issubclass(obj, Exception): + elif (type(obj) in class_types) and issubclass(obj, Exception): s = n else: self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj))) diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index b88df033c..e13df4ecf 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -33,13 +33,13 @@ import ast import string -from types import GeneratorType, ClassType, TypeType +from types import GeneratorType from myhdl._compat import StringIO import warnings import myhdl from myhdl import * -from myhdl._compat import integer_types +from myhdl._compat import integer_types, class_types from myhdl import ToVerilogError, ToVerilogWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVerilogCode, _userCodeMap) @@ -748,7 +748,7 @@ def visit_Call(self, node): self.write(opening) self.visit(fn.value) self.write(closing) - elif type(f) in (ClassType, TypeType) and issubclass(f, Exception): + elif (type(f) in class_types) and issubclass(f, Exception): self.write(f.__name__) elif f in (posedge, negedge): opening, closing = ' ', '' @@ -1017,7 +1017,7 @@ def getName(self, node): s = m.name elif isinstance(obj, EnumItemType): s = obj._toVerilog() - elif type(obj) in (ClassType, TypeType) and issubclass(obj, Exception): + elif (type(obj) in class_types) and issubclass(obj, Exception): s = n else: self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj))) From 185d0ddebaed3fbfba65c47ccf457c2835ed856c Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 19:41:01 -0500 Subject: [PATCH 11/31] fix __builtin__ references in _analyze --- myhdl/conversion/_analyze.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index f9731ea78..7a54b9ca7 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -29,7 +29,6 @@ import re import ast from collections import defaultdict -import __builtin__ import myhdl from myhdl import * @@ -45,9 +44,10 @@ from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal from myhdl._util import _isTupleOfInts, _dedent, _makeAST from myhdl._resolverefs import _AttrRefTransformer +from myhdl._compat import builtins myhdlObjects = myhdl.__dict__.values() -builtinObjects = __builtin__.__dict__.values() +builtinObjects = builtins.__dict__.values() _enumTypeSet = set() _constDict = {} @@ -876,8 +876,8 @@ def getName(self, node): _constDict[ws] = self.tree.symdict[ws] if ext: _extConstDict[ws] = self.tree.symdict[ws] - elif n in __builtin__.__dict__: - node.obj = __builtin__.__dict__[n] + elif n in builtins.__dict__: + node.obj = builtins.__dict__[n] else: self.raiseError(node, _error.UnboundLocal, n) From 64be5700d8866b443aedc5136ef06c74349c9891 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 19:59:11 -0500 Subject: [PATCH 12/31] fix long compat in _bin.py --- myhdl/_bin.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/_bin.py b/myhdl/_bin.py index 1cbe5432c..4678c55b2 100644 --- a/myhdl/_bin.py +++ b/myhdl/_bin.py @@ -20,7 +20,7 @@ """ module with the bin function. """ - +from myhdl._compat import long def _int2bitstring(num): From 5c8a291c263bfdcd1610a124c1d6850e6189a3a9 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 19:59:21 -0500 Subject: [PATCH 13/31] Use sys.maxsize instead of maxint in core tests --- myhdl/test/core/test_Signal.py | 2 +- myhdl/test/core/test_bin.py | 16 ++++++++-------- myhdl/test/core/test_intbv.py | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index 4e3a6bbd0..a38bc4645 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -26,7 +26,7 @@ from random import randrange random.seed(1) # random, but deterministic import sys -maxint = sys.maxint +maxint = sys.maxsize import types import copy diff --git a/myhdl/test/core/test_bin.py b/myhdl/test/core/test_bin.py index 34df37a30..df2eadd02 100644 --- a/myhdl/test/core/test_bin.py +++ b/myhdl/test/core/test_bin.py @@ -70,30 +70,30 @@ def testSmallWidth(self): def testRandomInt(self): for j in range(SIZE): - i = randrange(-sys.maxint, sys.maxint) + i = randrange(-sys.maxsize, sys.maxsize) self.assertEqual(bin(i), binref(i)) def testRandomIntWidth(self): for j in range(SIZE): w = randrange(1, 1000) - i = randrange(-sys.maxint, sys.maxint) + i = randrange(-sys.maxsize, sys.maxsize) self.assertEqual(bin(i, w), binref(i, w)) def testRandomLong(self): for j in range(SIZE): - k = randrange(sys.maxint) - i = k + sys.maxint + k = randrange(sys.maxsize) + i = k + sys.maxsize self.assertEqual(bin(i), binref(i)) - i = -k - sys.maxint + i = -k - sys.maxsize self.assertEqual(bin(i), binref(i)) def testRandomLongWith(self): for j in range(SIZE): w = randrange(1, 1000) - k = randrange(sys.maxint) - i = k + sys.maxint + k = randrange(sys.maxsize) + i = k + sys.maxsize self.assertEqual(bin(i, w), binref(i, w)) - i = -k - sys.maxint + i = -k - sys.maxsize self.assertEqual(bin(i, w), binref(i, w)) diff --git a/myhdl/test/core/test_intbv.py b/myhdl/test/core/test_intbv.py index c2d9b9ba3..33ad46fd3 100644 --- a/myhdl/test/core/test_intbv.py +++ b/myhdl/test/core/test_intbv.py @@ -27,7 +27,7 @@ from random import randrange random.seed(2) # random, but deterministic import sys -maxint = sys.maxint +maxint = sys.maxsize import operator from copy import copy, deepcopy From 8ec439d3f49f30ec15b0169406c304a40d2fbc50 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 20:01:24 -0500 Subject: [PATCH 14/31] fix dict.has_key usage for python3 --- myhdl/_enum.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/_enum.py b/myhdl/_enum.py index b4ed2a724..aac32fc37 100644 --- a/myhdl/_enum.py +++ b/myhdl/_enum.py @@ -54,7 +54,7 @@ def enum(*names, **kwargs): for name in names: if not isinstance(name, string_types): raise TypeError() - if codedict.has_key(name): + if name in codedict: raise ValueError("enum literals should be unique") if encoding == "one_hot": code = bin(1< Date: Sun, 1 Feb 2015 20:07:14 -0500 Subject: [PATCH 15/31] Fix iterator next() methods for python3 --- myhdl/_Waiter.py | 12 ++++++------ myhdl/_traceSignals.py | 4 ++-- myhdl/conversion/_misc.py | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/myhdl/_Waiter.py b/myhdl/_Waiter.py index b03f6216b..03b1e8d9d 100644 --- a/myhdl/_Waiter.py +++ b/myhdl/_Waiter.py @@ -67,7 +67,7 @@ def next(self, waiters, actives, exc): clone = _Waiter(self.generator, self.caller) try: - clause = self.generator.next() + clause = next(self.generator) except StopIteration: if self.caller: waiters.append(self.caller) @@ -126,7 +126,7 @@ def __init__(self, generator): self.generator = generator def next(self, waiters, actives, exc): - clause = self.generator.next() + clause = next(self.generator) schedule((_simulator._time + clause._time, self)) @@ -139,7 +139,7 @@ def __init__(self, generator): self.hasRun = 0 def next(self, waiters, actives, exc): - clause = self.generator.next() + clause = next(self.generator) clause.append(self) @@ -154,7 +154,7 @@ def __init__(self, generator): def next(self, waiters, actives, exc): if self.hasRun: raise StopIteration - clauses = self.generator.next() + clauses = next(self.generator) self.hasRun = 1 clone = _EdgeTupleWaiter(self.generator) for clause in clauses: @@ -171,7 +171,7 @@ def __init__(self, generator): self.hasRun = 0 def next(self, waiters, actives, exc): - clause = self.generator.next() + clause = next(self.generator) clause._eventWaiters.append(self) @@ -186,7 +186,7 @@ def __init__(self, generator): def next(self, waiters, actives, exc): if self.hasRun: raise StopIteration - clauses = self.generator.next() + clauses = next(self.generator) self.hasRun = 1 clone = _SignalTupleWaiter(self.generator) for clause in clauses: diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index 321ea711b..cf44342dd 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -152,7 +152,7 @@ def _writeVcdSigs(f, hierarchy, tracelists): raise ValueError("%s of module %s has no initial value" % (n, name)) if not s._tracing: s._tracing = 1 - s._code = namegen.next() + s._code = next(namegen) siglist.append(s) w = s._nrbits # use real for enum strings @@ -174,7 +174,7 @@ def _writeVcdSigs(f, hierarchy, tracelists): raise ValueError("%s of module %s has no initial value" % (n, name)) if not s._tracing: s._tracing = 1 - s._code = namegen.next() + s._code = next(namegen) siglist.append(s) w = s._nrbits if w: diff --git a/myhdl/conversion/_misc.py b/myhdl/conversion/_misc.py index 3872d6a92..4e1def35c 100644 --- a/myhdl/conversion/_misc.py +++ b/myhdl/conversion/_misc.py @@ -172,7 +172,7 @@ def _LabelGenerator(): class _Label(object): def __init__(self, name): - self.name = _genLabel.next() + '_' + name + self.name = next(_genLabel) + '_' + name self.isActive = False def __str__(self): return str(self.name) From 0009d7b139880d0d7a08c5d51af94cebbb337bd3 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 20:36:08 -0500 Subject: [PATCH 16/31] Remove deprecated _unparse module delete module, disable test it is not used anywhere --- myhdl/_unparse.py | 172 ------------------------------------ myhdl/test/core/test_all.py | 4 +- 2 files changed, 2 insertions(+), 174 deletions(-) delete mode 100644 myhdl/_unparse.py diff --git a/myhdl/_unparse.py b/myhdl/_unparse.py deleted file mode 100644 index f4e3eb649..000000000 --- a/myhdl/_unparse.py +++ /dev/null @@ -1,172 +0,0 @@ -# This file is part of the myhdl library, a Python package for using -# Python as a Hardware Description Language. -# -# Copyright (C) 2003-2008 Jan Decaluwe -# -# The myhdl library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public License as -# published by the Free Software Foundation; either version 2.1 of the -# License, or (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -""" unparse module - -""" -from __future__ import absolute_import - - -import compiler -from myhdl._compat import StringIO - -def _unparse(ast): - v = _UnparseVisitor() - compiler.walk(ast, v) - return v.buf.getvalue() - -class _UnparseVisitor(object): - - def __init__(self): - self.buf = StringIO() - - def write(self, arg): - self.buf.write(arg) - - def unaryOp(self, node, op): - self.write("(") - self.write("%s" % op) - self.visit(node.expr) - self.write(")") - - def binaryOp(self, node, op): - self.write("(") - self.visit(node.left) - self.write(" %s " % op) - self.visit(node.right) - self.write(")") - - def multiOp(self, node, op): - self.write("(") - self.visit(node.nodes[0]) - for node in node.nodes[1:]: - self.write(" %s " % op) - self.visit(node) - self.write(")") - - def visitAdd(self, node): - self.binaryOp(node, '+') - - def visitAnd(self, node): - self.multiOp(node, ' and ') - - def visitBitand(self, node): - self.multiOp(node, '&') - - def visitBitor(self, node): - self.multiOp(node, '|') - - def visitBitxor(self, node): - self.multiOp(node, '^') - - def visitCallFunc(self, node): - self.visit(node.node) - self.write('(') - comma = '' - for arg in node.args: - self.write(comma); comma=',' - self.visit(arg) - if node.star_args: - self.write(comma); comma=',' - self.write('*') - self.visit(node.star_args) - if node.dstar_args: - self.write(comma); comma=',' - self.write('**') - self.visit(node.dstar_args) - self.write(')') - - def visitCompare(self, node): - self.write("(") - self.visit(node.expr) - for comp in node.ops: - op, expr = comp - self.write(" %s " % op) - self.visit(expr) - self.write(")") - - def visitConst(self, node): - self.write(str(node.value)) - - def visitGetattr(self, node): - self.visit(node.expr) - self.write('.') - self.write(node.attrname) - - def visitFloorDiv(self, node): - self.binaryOp(node, '//') - - def visitInvert(self, node): - self.unaryOp(node, '~') - - def visitKeyword(self, node): - self.write(node.name) - self.write('=') - self.visit(node.expr) - - def visitLeftShift(self, node): - self.binaryOp(node, '<<') - - def visitName(self, node): - self.write(node.name) - - def visitMod(self, node): - self.binaryOp(node, '%') - - def visitMul(self, node): - self.binaryOp(node, '*') - - def visitNot(self, node): - self.unaryOp(node, 'not ') - - def visitOr(self, node): - self.multiOp(node, ' or ') - - def visitPower(self, node): - self.binaryOp(node, '**') - - def visitRightShift(self, node): - self.binaryOp(node, '>>') - - def visitSlice(self, node): - self.visit(node.expr) - self.write('[') - if node.lower is not None: - self.visit(node.lower) - self.write(':') - if node.upper is not None: - self.visit(node.upper) - self.write(']') - - def visitSub(self, node): - self.binaryOp(node, '-') - - def visitSubscript(self, node): - self.visit(node.expr) - self.write("[") - if len(node.subs) > 1: - raise NotImplementedError - self.visit(node.subs[0]) - self.write("]") - - def visitUnaryAdd(self, node, *args): - self.unaryOp(node, '+') - - def visitUnarySub(self, node, *args): - self.unaryOp(node, '-') diff --git a/myhdl/test/core/test_all.py b/myhdl/test/core/test_all.py index 6eca864c9..56acc97c6 100644 --- a/myhdl/test/core/test_all.py +++ b/myhdl/test/core/test_all.py @@ -23,12 +23,12 @@ import test_Simulation, test_Signal, test_intbv, test_Cosimulation, test_misc, \ test_always_comb, test_bin, test_traceSignals, test_enum, test_concat, \ - test_unparse, test_inferWaiter, test_always, test_instance, test_signed, \ + test_inferWaiter, test_always, test_instance, test_signed, \ test_modbv modules = (test_Simulation, test_Signal, test_intbv, test_misc, test_always_comb, test_bin, test_traceSignals, test_enum, test_concat, - test_unparse, test_inferWaiter, test_always, test_instance, test_signed, + test_inferWaiter, test_always, test_instance, test_signed, test_modbv ) From 15305854ef59f098d25caade23b05ccebff58cc4 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 20:43:05 -0500 Subject: [PATCH 17/31] fix long references in _signal --- myhdl/_Signal.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py index ce112a989..a04a13640 100644 --- a/myhdl/_Signal.py +++ b/myhdl/_Signal.py @@ -33,7 +33,7 @@ from copy import copy, deepcopy import operator -from myhdl._compat import integer_types +from myhdl._compat import integer_types, long from myhdl import _simulator as sim from myhdl._simulator import _signals, _siglist, _futureEvents, now from myhdl._intbv import intbv @@ -193,7 +193,7 @@ def _update(self): self._val = None elif isinstance(val, intbv): self._val._val = next._val - elif isinstance(val, (int, long, EnumItemType)): + elif isinstance(val, (integer_types, EnumItemType)): self._val = next else: self._val = deepcopy(next) @@ -275,7 +275,7 @@ def _setNextBool(self, val): def _setNextInt(self, val): if isinstance(val, intbv): val = val._val - elif not isinstance(val, (int, long)): + elif not isinstance(val, (integer_types, intbv)): raise TypeError("Expected int or intbv, got %s" % type(val)) self._next = val From 64e477cb3832693714796dfe96235c700cf73378 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 22:21:27 -0500 Subject: [PATCH 18/31] make test_intbv use operator rather than exec --- myhdl/test/core/test_intbv.py | 50 +++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/myhdl/test/core/test_intbv.py b/myhdl/test/core/test_intbv.py index 33ad46fd3..8d3536895 100644 --- a/myhdl/test/core/test_intbv.py +++ b/myhdl/test/core/test_intbv.py @@ -286,13 +286,13 @@ def augmentedAssignCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): for i, j in zip(self.seqi, self.seqj): bj = intbv(j) ref = long(i) - exec("ref %s j" % op) + ref = op(ref, j) r1 = bi1 = intbv(long(i)) - exec("r1 %s j" % op) + r1 = op(r1, j) r2 = long(i) - exec("r2 %s bj" % op) + r2 = op(r2, bj) r3 = bi3 = intbv(long(i)) - exec("r3 %s bj" % op) + r3 = op(r3, bj) self.assertEqual(type(r1), intbv) self.assertEqual(type(r3), intbv) self.assertEqual(r1, ref) @@ -324,10 +324,10 @@ def comparisonCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): for i, j in zip(self.seqi, self.seqj): bi = intbv(i) bj = intbv(j) - exec("ref = i %s j" % op) - exec("r1 = bi %s j" % op) - exec("r2 = i %s bj" % op) - exec("r3 = bi %s bj" % op) + ref = op(i, j) + r1 = op(bi, j) + r2 = op(i, bj) + r3 = op(bi, bj) self.assertEqual(r1, ref) self.assertEqual(r2, ref) self.assertEqual(r3, ref) @@ -369,37 +369,37 @@ def testXor(self): self.binaryCheck(operator.xor) def testIAdd(self): - self.augmentedAssignCheck("+=") + self.augmentedAssignCheck(operator.iadd) def testISub(self): - self.augmentedAssignCheck("-=") + self.augmentedAssignCheck(operator.isub) def testIMul(self): - self.augmentedAssignCheck("*=", imax=maxint) #XXX doesn't work for long i??? + self.augmentedAssignCheck(operator.imul, imax=maxint) #XXX doesn't work for long i??? def testIFloorDiv(self): - self.augmentedAssignCheck("//=", jmin=1) + self.augmentedAssignCheck(operator.ifloordiv, jmin=1) def testIMod(self): - self.augmentedAssignCheck("%=", jmin=1) + self.augmentedAssignCheck(operator.imod, jmin=1) def testIPow(self): - self.augmentedAssignCheck("**=", jmax=64) + self.augmentedAssignCheck(operator.ipow, jmax=64) def testIAnd(self): - self.augmentedAssignCheck("&=") + self.augmentedAssignCheck(operator.iand) def testIOr(self): - self.augmentedAssignCheck("|=") + self.augmentedAssignCheck(operator.ior) def testIXor(self): - self.augmentedAssignCheck("^=") + self.augmentedAssignCheck(operator.ixor) def testILShift(self): - self.augmentedAssignCheck("<<=", jmax=256) + self.augmentedAssignCheck(operator.ilshift, jmax=256) def testIRShift(self): - self.augmentedAssignCheck(">>=", jmax=256) + self.augmentedAssignCheck(operator.irshift, jmax=256) def testNeg(self): self.unaryCheck(operator.neg) @@ -431,17 +431,17 @@ def testHex(self): self.conversionCheck(hex) def testLt(self): - self.comparisonCheck("<") + self.comparisonCheck(operator.lt) def testLe(self): - self.comparisonCheck("<=") + self.comparisonCheck(operator.le) def testGt(self): - self.comparisonCheck(">") + self.comparisonCheck(operator.gt) def testGe(self): - self.comparisonCheck(">=") + self.comparisonCheck(operator.ge) def testEq(self): - self.comparisonCheck("==") + self.comparisonCheck(operator.eq) def testNe(self): - self.comparisonCheck("!=") + self.comparisonCheck(operator.ne) class TestIntbvBounds(TestCase): From aec0ee62bb7e613b62d5aa35219ee494e466744a Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 22:24:22 -0500 Subject: [PATCH 19/31] import compat long to test_Signal --- myhdl/test/core/test_Signal.py | 1 + 1 file changed, 1 insertion(+) diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index a38bc4645..62e885031 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -35,6 +35,7 @@ from myhdl._simulator import _siglist from myhdl import intbv, Signal +from myhdl._compat import long class SigTest(TestCase): From 0671c4f14365cb30c4cffdbd458b71fd325ae5ac Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 23:31:23 -0500 Subject: [PATCH 20/31] make test_Signal use operator rather than exec --- myhdl/test/core/test_Signal.py | 70 +++++++++++++++++----------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index 62e885031..55197b440 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -176,6 +176,7 @@ def testUpdatePosedge(self): s1._posedgeWaiters = self.posedgeWaiters[:] s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() + print(waiters) expected = self.eventWaiters + self.posedgeWaiters waiters.sort() expected.sort() @@ -307,19 +308,19 @@ def augmentedAssignCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): for i, j in zip(self.seqi, self.seqj): bj = Signal(j) ref = long(i) - exec("ref %s j" % op) + ref = op(ref, j) r1 = bi1 = Signal(i) try: - exec("r1 %s j" % op) + r1 = op(r1, j) except TypeError: pass else: self.fail() r2 = long(i) - exec("r2 %s bj" % op) + r2 = op(r2, bj) r3 = bi3 = Signal(i) try: - exec("r3 %s bj" % op) + r3 = op(r3, bj) except TypeError: pass else: @@ -349,10 +350,10 @@ def comparisonCheck(self, op, imin=0, imax=None, jmin=0, jmax=None): for i, j in zip(self.seqi, self.seqj): bi = Signal(i) bj = Signal(j) - exec("ref = i %s j" % op) - exec("r1 = bi %s j" % op) - exec("r2 = i %s bj" % op) - exec("r3 = bi %s bj" % op) + ref = op(i, j) + r1 = op(bi, j) + r2 = op(i, bj) + r3 = op(bi, bj) self.assertEqual(r1, ref) self.assertEqual(r2, ref) self.assertEqual(r3, ref) @@ -377,7 +378,7 @@ def testPow(self): def testLShift(self): self.binaryCheck(operator.lshift, jmax=256) - + def testRShift(self): self.binaryCheck(operator.rshift, jmax=256) @@ -386,42 +387,42 @@ def testAnd(self): def testOr(self): self.binaryCheck(operator.or_) - + def testXor(self): self.binaryCheck(operator.xor) def testIAdd(self): - self.augmentedAssignCheck("+=") + self.augmentedAssignCheck(operator.iadd) def testISub(self): - self.augmentedAssignCheck("-=") - + self.augmentedAssignCheck(operator.isub) + def testIMul(self): - self.augmentedAssignCheck("*=", imax=maxint) #XXX doesn't work for long i??? - + self.augmentedAssignCheck(operator.imul, imax=maxint) #XXX doesn't work for long i??? + def testIDiv(self): - self.augmentedAssignCheck("/=", jmin=1) - + self.augmentedAssignCheck(operator.idiv, jmin=1) + def testIMod(self): - self.augmentedAssignCheck("%=", jmin=1) + self.augmentedAssignCheck(operator.imod, jmin=1) def testIPow(self): - self.augmentedAssignCheck("**=", jmax=64) + self.augmentedAssignCheck(operator.ipow, jmax=64) def testIAnd(self): - self.augmentedAssignCheck("&=") - + self.augmentedAssignCheck(operator.iand) + def testIOr(self): - self.augmentedAssignCheck("|=") - + self.augmentedAssignCheck(operator.ior) + def testIXor(self): - self.augmentedAssignCheck("^=") - + self.augmentedAssignCheck(operator.ixor) + def testILShift(self): - self.augmentedAssignCheck("<<=", jmax=256) - + self.augmentedAssignCheck(operator.ilshift, jmax=256) + def testIRShift(self): - self.augmentedAssignCheck(">>=", jmax=256) + self.augmentedAssignCheck(operator.irshift, jmax=256) def testNeg(self): self.unaryCheck(operator.neg) @@ -453,18 +454,17 @@ def testHex(self): self.conversionCheck(hex) def testLt(self): - self.comparisonCheck("<") + self.comparisonCheck(operator.lt) def testLe(self): - self.comparisonCheck("<=") + self.comparisonCheck(operator.le) def testGt(self): - self.comparisonCheck(">") + self.comparisonCheck(operator.gt) def testGe(self): - self.comparisonCheck(">=") + self.comparisonCheck(operator.ge) def testEq(self): - self.comparisonCheck("==") + self.comparisonCheck(operator.eq) def testNe(self): - self.comparisonCheck("!=") - + self.comparisonCheck(operator.ne) def getItem(s, i): From adcd90ee0d73db0bb7a9948f99a72f3deaf9a652 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Sun, 1 Feb 2015 23:54:28 -0500 Subject: [PATCH 21/31] correctly sort _futureevents --- myhdl/_Simulation.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py index 5527381f7..4bad69553 100644 --- a/myhdl/_Simulation.py +++ b/myhdl/_Simulation.py @@ -24,6 +24,7 @@ import sys import os +from operator import itemgetter from warnings import warn from types import GeneratorType @@ -157,7 +158,7 @@ def run(self, duration=None, quiet=0): if t == maxTime: raise _SuspendSimulation( "Simulated %s timesteps" % duration) - _futureEvents.sort() + _futureEvents.sort(key=itemgetter(0)) t = _simulator._time = _futureEvents[0][0] if tracing: print("#%s" % t, file=tracefile) From e6bf9e0e0cd46184cb968958fe8252daccc648b6 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Mon, 2 Feb 2015 00:01:04 -0500 Subject: [PATCH 22/31] make list range before assigning in test_sim --- myhdl/test/core/test_Simulation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/test/core/test_Simulation.py b/myhdl/test/core/test_Simulation.py index 545d184f2..7fce45c90 100644 --- a/myhdl/test/core/test_Simulation.py +++ b/myhdl/test/core/test_Simulation.py @@ -436,7 +436,7 @@ def bench(self, function): s = [a, b, c, d] vectors = [intbv(j) for i in range(8) for j in range(16)] random.shuffle(vectors) - index = range(4) + index = list(range(4)) def clkGen(): while 1: From a213fa479223cf68722e3c312ed1c21fa21bd8d9 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Mon, 2 Feb 2015 00:05:16 -0500 Subject: [PATCH 23/31] test_concat import reduce, long for python3 --- myhdl/test/core/test_concat.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/myhdl/test/core/test_concat.py b/myhdl/test/core/test_concat.py index 812eb7d0c..8f10a9c55 100644 --- a/myhdl/test/core/test_concat.py +++ b/myhdl/test/core/test_concat.py @@ -25,12 +25,14 @@ from unittest import TestCase import random from random import randrange +from functools import reduce random.seed(2) # random, but deterministic import operator from myhdl._intbv import intbv from myhdl._Signal import Signal from myhdl._concat import concat +from myhdl._compat import long From 79704daa158021972349b8e53b04eaff6c01477e Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Mon, 2 Feb 2015 00:09:08 -0500 Subject: [PATCH 24/31] more long->integer_types fixes --- myhdl/_concat.py | 1 + myhdl/conversion/_analyze.py | 8 ++++---- myhdl/conversion/_toVHDL.py | 2 +- myhdl/test/core/test_bin.py | 1 + 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/myhdl/_concat.py b/myhdl/_concat.py index 6be595a58..08fefa37e 100644 --- a/myhdl/_concat.py +++ b/myhdl/_concat.py @@ -25,6 +25,7 @@ from myhdl._compat import integer_types from myhdl._intbv import intbv from myhdl._Signal import _Signal +from myhdl._compat import long diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index 7a54b9ca7..81168f3ed 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -44,7 +44,7 @@ from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal from myhdl._util import _isTupleOfInts, _dedent, _makeAST from myhdl._resolverefs import _AttrRefTransformer -from myhdl._compat import builtins +from myhdl._compat import builtins, integer_types myhdlObjects = myhdl.__dict__.values() builtinObjects = builtins.__dict__.values() @@ -576,7 +576,7 @@ def visit_Call(self, node): node.obj = int(0) # XXX elif f is bool: node.obj = bool() - elif f in (int, long, ord): + elif f in (integer_types, ord): node.obj = int(-1) ## elif f in (posedge , negedge): ## node.obj = _EdgeDetector() @@ -604,7 +604,7 @@ def visit_Call(self, node): if f.__code__.co_freevars: for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = _cell_deref(c) - if not isinstance(obj, (int, long, _Signal)): + if not isinstance(obj, (integer_types, _Signal)): self.raiseError(node, _error.FreeVarTypeError, n) tree.symdict[n] = obj v = _FirstPassVisitor(tree) @@ -647,7 +647,7 @@ def visit_Compare(self, node): val = arg.obj if isinstance(val, bool): val = int(val) # cast bool to int first - if isinstance(val, (EnumItemType, int, long)): + if isinstance(val, (EnumItemType, integer_types)): node.case = (node.left, val) # check whether it can be part of an edge check n = node.left.id diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 078f7cb04..d1cb6d571 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -2053,7 +2053,7 @@ def visit_Call(self, node): node.vhd = vhd_unsigned(s) elif f is bool: node.vhd = vhd_boolean() - elif f in (int, long, ord): + elif f in (integer_types, ord): node.vhd = vhd_int() node.args[0].vhd = vhd_int() elif f in (intbv, modbv): diff --git a/myhdl/test/core/test_bin.py b/myhdl/test/core/test_bin.py index df2eadd02..ab0b69d02 100644 --- a/myhdl/test/core/test_bin.py +++ b/myhdl/test/core/test_bin.py @@ -30,6 +30,7 @@ import sys from myhdl import bin +from myhdl._compat import long SIZE = 100 From d0dc39dc21218cbc679e929367c2800d148f6df1 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Fri, 6 Feb 2015 07:46:59 -0500 Subject: [PATCH 25/31] fix usage of x in integer_types,.. --- myhdl/conversion/_analyze.py | 4 ++-- myhdl/conversion/_toVHDL.py | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index 81168f3ed..b10ab1e61 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -42,7 +42,7 @@ from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode from myhdl._Signal import _Signal, _WaiterList from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal -from myhdl._util import _isTupleOfInts, _dedent, _makeAST +from myhdl._util import _isTupleOfInts, _dedent, _flatten, _makeAST from myhdl._resolverefs import _AttrRefTransformer from myhdl._compat import builtins, integer_types @@ -576,7 +576,7 @@ def visit_Call(self, node): node.obj = int(0) # XXX elif f is bool: node.obj = bool() - elif f in (integer_types, ord): + elif f in _flatten(integer_types, ord): node.obj = int(-1) ## elif f in (posedge , negedge): ## node.obj = _EdgeDetector() diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index d1cb6d571..8caf8e9d4 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -40,7 +40,6 @@ import myhdl from myhdl import * -from myhdl._compat import integer_types, class_types, StringIO from myhdl import ToVHDLError, ToVHDLWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVhdlCode, _userCodeMap) @@ -52,6 +51,8 @@ _Ram, _Rom, _enumTypeSet, _constDict, _extConstDict) from myhdl._Signal import _Signal,_WaiterList from myhdl.conversion._toVHDLPackage import _package +from myhdl._util import _flatten +from myhdl._compat import integer_types, class_types, StringIO _version = myhdl.__version__.replace('.','') @@ -2053,7 +2054,7 @@ def visit_Call(self, node): node.vhd = vhd_unsigned(s) elif f is bool: node.vhd = vhd_boolean() - elif f in (integer_types, ord): + elif f in _flatten(integer_types, ord): node.vhd = vhd_int() node.args[0].vhd = vhd_int() elif f in (intbv, modbv): From 969c122c8c6e0a25bd9427a7a10cddbe010b72ab Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Fri, 6 Feb 2015 08:30:03 -0500 Subject: [PATCH 26/31] use py3 compatible method of merging dicts --- myhdl/conversion/_analyze.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index b10ab1e61..f8025cce7 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -28,6 +28,7 @@ from types import FunctionType, MethodType import re import ast +from itertools import chain from collections import defaultdict import myhdl @@ -93,7 +94,7 @@ def _analyzeSigs(hierarchy, hdl='Verilog'): name = inst.name sigdict = inst.sigdict memdict = inst.memdict - namedict = dict(sigdict.items() + memdict.items()) + namedict = dict(chain(sigdict.items(), memdict.items())) delta = curlevel - level curlevel = level assert(delta >= -1) From 8137e6ce6be06fcdebe3fad49807ce8fb48e7cdf Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 11 Mar 2015 18:06:34 -0400 Subject: [PATCH 27/31] replace backqote with repr everywhere excpt conversion test --- myhdl/conversion/_toVHDL.py | 2 +- myhdl/conversion/_toVerilog.py | 2 +- myhdl/test/core/test_Signal.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 8caf8e9d4..a1552d762 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -937,7 +937,7 @@ def visit_Call(self, node): elif f is len: val = self.getVal(node) self.require(node, val is not None, "cannot calculate len") - self.write(`val`) + self.write(repr(val)) return elif f is now: pre, suf = self.inferCast(node.vhd, node.vhdOri) diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index e13df4ecf..2e4e9159e 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -720,7 +720,7 @@ def visit_Call(self, node): elif f is len: val = self.getVal(node) self.require(node, val is not None, "cannot calculate len") - self.write(`val`) + self.write(repr(val)) return elif f is now: self.write("$time") diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index 55197b440..5afb62bcf 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -164,7 +164,7 @@ def testModify(self): s.next[3] = 5 else: s.next # plain read access - self.assertTrue(s.val is not s.next, `s.val`) + self.assertTrue(s.val is not s.next, repr(s.val)) def testUpdatePosedge(self): """ update on posedge should return event and posedge waiters """ From f2274bd7301df34039a3bfcd45d8414e443f839f Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Mon, 9 Mar 2015 13:39:18 -0400 Subject: [PATCH 28/31] replace __nonzero__ with __bool__ python3 deprecates __nonzero__ and introduces __bool__ This commit introduces __bool__ while maintaining python2 compatibility --- myhdl/_Signal.py | 9 ++++----- myhdl/_intbv.py | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py index a04a13640..4dfb4ec1c 100644 --- a/myhdl/_Signal.py +++ b/myhdl/_Signal.py @@ -323,11 +323,10 @@ def __hash__(self): raise TypeError("Signals are unhashable") - def __nonzero__(self): - if self._val: - return 1 - else: - return 0 + def __bool__(self): + return bool(self._val) + + __nonzero__ = __bool__ # length def __len__(self): diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index bc80b6972..173ad75c9 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -114,11 +114,10 @@ def __iter__(self): return iter([self[i] for i in range(self._nrbits-1, -1, -1)]) # logical testing - def __nonzero__(self): - if self._val: - return 1 - else: - return 0 + def __bool__(self): + return bool(self._val) + + __nonzero__ = __bool__ # length def __len__(self): From b2948f484316b096ff5535216d9192588a50ca1d Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Mon, 9 Mar 2015 17:36:35 -0400 Subject: [PATCH 29/31] use future division in signal, intbv Also, remove the __div__ and __rdiv__ magic methods --- myhdl/_Signal.py | 16 +++++----------- myhdl/_intbv.py | 14 +++----------- myhdl/test/core/test_Signal.py | 10 +++++----- myhdl/test/core/test_intbv.py | 4 ++-- 4 files changed, 15 insertions(+), 29 deletions(-) diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py index 4dfb4ec1c..4a1d21102 100644 --- a/myhdl/_Signal.py +++ b/myhdl/_Signal.py @@ -364,21 +364,13 @@ def __mul__(self, other): def __rmul__(self, other): return other * self._val - def __div__(self, other): + def __truediv__(self, other): if isinstance(other, _Signal): return self._val / other._val else: return self._val / other - def __rdiv__(self, other): - return other / self._val - - def __truediv__(self, other): - if isinstance(other, _Signal): - return operator.truediv(self._val, other._val) - else: - return operator.truediv(self._val, other) def __rtruediv__(self, other): - return operator.truediv(other, self._val) + return other / self._val def __floordiv__(self, other): if isinstance(other, _Signal): @@ -515,8 +507,10 @@ def _toVerilog(self): def _augm(self): raise TypeError("Signal object doesn't support augmented assignment") - __iadd__ = __isub__ = __idiv__ = __imul__ = __ipow__ = __imod__ = _augm + __iadd__ = __isub__ = __imul__ = __ipow__ = __imod__ = _augm __ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm + __itruediv__ = __ifloordiv__ = _augm + # index and slice assignment not supported def __setitem__(self, key, val): diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 173ad75c9..9131daa98 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -18,7 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the intbv class """ -from __future__ import absolute_import +from __future__ import absolute_import, division import operator @@ -217,21 +217,13 @@ def __mul__(self, other): def __rmul__(self, other): return other * self._val - def __div__(self, other): + def __truediv__(self, other): if isinstance(other, intbv): return self._val / other._val else: return self._val / other - def __rdiv__(self, other): - return other / self._val - - def __truediv__(self, other): - if isinstance(other, intbv): - return operator.truediv(self._val, other._val) - else: - return operator.truediv(self._val, other) def __rtruediv__(self, other): - return operator.truediv(other, self._val) + return other / self._val def __floordiv__(self, other): if isinstance(other, intbv): diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index 5afb62bcf..07efe7964 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -367,9 +367,9 @@ def testSub(self): def testMul(self): self.binaryCheck(operator.mul, imax=maxint) # XXX doesn't work for long i??? - def testDiv(self): - self.binaryCheck(operator.div, jmin=1) - + def testFloorDiv(self): + self.binaryCheck(operator.floordiv, jmin=1) + def testMod(self): self.binaryCheck(operator.mod, jmin=1) @@ -400,8 +400,8 @@ def testISub(self): def testIMul(self): self.augmentedAssignCheck(operator.imul, imax=maxint) #XXX doesn't work for long i??? - def testIDiv(self): - self.augmentedAssignCheck(operator.idiv, jmin=1) + def testIFloorDiv(self): + self.augmentedAssignCheck(operator.ifloordiv, jmin=1) def testIMod(self): self.augmentedAssignCheck(operator.imod, jmin=1) diff --git a/myhdl/test/core/test_intbv.py b/myhdl/test/core/test_intbv.py index 8d3536895..fb7ba8649 100644 --- a/myhdl/test/core/test_intbv.py +++ b/myhdl/test/core/test_intbv.py @@ -341,8 +341,8 @@ def testSub(self): def testMul(self): self.binaryCheck(operator.mul, imax=maxint) # XXX doesn't work for long i??? - def testDiv(self): - self.binaryCheck(operator.div, jmin=1) + def testTrueDiv(self): + self.binaryCheck(operator.truediv, jmin=1) def testFloorDiv(self): self.binaryCheck(operator.floordiv, jmin=1) From b3416d49c8c4f62d537094702c7ff237b8a974f5 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 11 Mar 2015 02:39:16 -0400 Subject: [PATCH 30/31] fix intbv.signed behavior when min is None In python 2, None >= 0 returns false. However, in py3, None cannot be compared with zero. This commit ensures identical behaviour in py2,3 when min is none. --- myhdl/_intbv.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 9131daa98..05bdc8c34 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -502,7 +502,7 @@ def signed(self): ''' # value is considered unsigned - if self.min >= 0 and self._nrbits > 0: + if self.min is not None and self.min >= 0 and self._nrbits > 0: # get 2's complement value of bits msb = self._nrbits-1 From a2fd9c94a8dc2977625d1a9c852c12a6345553b7 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Mon, 9 Mar 2015 02:07:43 -0400 Subject: [PATCH 31/31] test_Signal: use set to check equality of lists fixes jandecaluwe#23 --- myhdl/test/core/test_Signal.py | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index 07efe7964..a37d0be2e 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -176,11 +176,8 @@ def testUpdatePosedge(self): s1._posedgeWaiters = self.posedgeWaiters[:] s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() - print(waiters) expected = self.eventWaiters + self.posedgeWaiters - waiters.sort() - expected.sort() - self.assertEqual(waiters, expected) + self.assertEqual(set(waiters), set(expected)) self.assertEqual(s1._eventWaiters, []) self.assertEqual(s1._posedgeWaiters, []) self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters) @@ -196,9 +193,7 @@ def testUpdateNegedge(self): s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() expected = self.eventWaiters + self.negedgeWaiters - waiters.sort() - expected.sort() - self.assertEqual(waiters, expected) + self.assertEqual(set(waiters), set(expected)) self.assertEqual(s1._eventWaiters, []) self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters) self.assertEqual(s1._negedgeWaiters, []) @@ -214,9 +209,7 @@ def testUpdateEvent(self): s1._negedgeWaiters = self.negedgeWaiters[:] waiters = s1._update() expected = self.eventWaiters - waiters.sort() - expected.sort() - self.assertEqual(waiters, expected) + self.assertEqual(set(waiters), set(expected)) self.assertEqual(s1._eventWaiters, []) self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters) self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)