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Makefile
README.txt
__init__.py
test_ShadowSignal.py
test_adapter.py
test_bin2gray.py
test_case.py
test_class_defined_signals.py
test_constants.py
test_dec.py
test_errors.py
test_fsm.py
test_hec.py
test_inc.py
test_initial_values.py
test_intbv_signed.py
test_interfaces1.py
test_interfaces2.py
test_interfaces3.py
test_interfaces4.py
test_listofsigs.py
test_loops.py
test_method.py
test_nonlocal.py
test_numass.py
test_print.py
test_ram.py
test_randscrambler.py
test_rom.py
test_set_dir.py
test_ternary.py
test_toplevel_method.py

README.txt

Conversion tests that should work with both VHDL and Verilog
------------------------------------------------------------

Requirements:
  * cver, icarus, GHDL, or vcom/vlog (default)
  * py.test

See the Makefile - it contains targets per simulator.