This figure is misleading as it implies the MCLK being in perfect sampling phase with the data.
Actually MCLK phase depends on the sample rate i.e. it is not possible to compensate with constant phase shift.
Another interesting point is that ENABLE_IQ_SEL is actually in phase with the data, so it would be a better candidate for sampling clock. But, for example on LimeSDR-Mini, ENABLE_IQ_SEL is not routed to the PLL input pin...so sadly cannot be used :(