Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

RX sampling clock phase depends on the sample rate #2

gasparka opened this Issue Jul 25, 2018 · 0 comments


None yet
1 participant
Copy link

gasparka commented Jul 25, 2018

This figure is misleading as it implies the MCLK being in perfect sampling phase with the data.
Actually MCLK phase depends on the sample rate i.e. it is not possible to compensate with constant phase shift.

Another interesting point is that ENABLE_IQ_SEL is actually in phase with the data, so it would be a better candidate for sampling clock. But, for example on LimeSDR-Mini, ENABLE_IQ_SEL is not routed to the PLL input sadly cannot be used :(

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
You can’t perform that action at this time.