Altera Cyclone IV FPGA project for the PCIe LimeSDR board
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vbuitvydas Ver.2.6.
Fix for synchronization disable;
Fix for low frequency synchronization;
Fix for tx_pct_loss flg.
Latest commit 3a1cbdc Jan 10, 2018
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.qsys_edit Updates for 1v2 version: FPGA SPI pins changed; BOM, HW pins added; R… Dec 8, 2016
db Recompiled project, added Clock to output delay assigments Jun 1, 2017
doc Added LimeSDR-PCIe_user_guide_V01r00.pdf document May 25, 2017
ip Changed DDR2 memory frequency to 125MHz Jun 7, 2017
limesdr-pcie_xillybus_core @ 9dea143 Enabled DMA acceleration option for PCIe core Aug 22, 2017
lms_ctr/synthesis Initial commit Jun 3, 2016
output_files Ver.2.0 Update for new hardwate version HW_VER_v1.3 May 25, 2017
software NIOS CPU core rebuild Jun 2, 2017
src Ver.2.6. Jan 10, 2018
symbols Temp commit Feb 13, 2017
.gitignore Updated .gitignore file to ignore NIOS EDS workspace Jan 25, 2017
.gitmodules Updates for 1v2 version: FPGA SPI pins changed; BOM, HW pins added; R… Dec 8, 2016
Av_FIFO_Int_hw.tcl Initial commit Jun 3, 2016
COPYING Added licence notice Jun 7, 2016
Clock_groups.sdc Added Clock_group.sdc Jun 2, 2017
DDR2_2_pin_assigments.tcl Added DDR2 memory pin script Apr 4, 2017
LMS7002_timing.sdc Changed timing values Jun 7, 2017
LimeSDR-PCIE_lms7_trx.qpf Initial commit Jun 3, 2016
LimeSDR-PCIE_lms7_trx.qsf Assigned delay chain settings Jun 7, 2017
LimeSDR-PCIE_lms7_trx_assignment_defaults.qdf Initial commit Jun 3, 2016
README.md README update Nov 2, 2017
assignment_defaults.qdf Initial commit Jun 3, 2016
gen_prg_files.tcl Ver.2.0 Update for new hardwate version HW_VER_v1.3 May 25, 2017
gui.tcl Ver. 1.4 RX_path update Nov 7, 2016
lms7_trx_timing.sdc Added header to .sdc files Jun 2, 2017
lms7_trx_top.bdf Recompiled project Jun 7, 2017
lms_ctr.qsys Initial commit Jun 3, 2016
lms_ctr.sopcinfo Initial commit Jun 3, 2016
update_rev.tcl Ver. 1.4 RX_path update Nov 7, 2016

README.md

LimeSDR-PCIe FPGA gateware

This repository contains the FPGA gateware project for the PCIe LimeSDR board.

The gateware can be built with the free version of the Altera Quartus tools.

Branches

This repository contains the following hardware-specific branches:

  • master:

    • Gateware for Hardware Revision 1v3
  • HW_v1.0:

    • Gateware for Hardware Revision 1v0
  • HW_v1.2:

    • Gateware for Hardware Revision 1v2

Licensing

Please see the COPYING file(s). However, please note that the license terms stated do not extend to any files provided with the Altera design tools and see the relevant files for the associated terms and conditions.