{"payload":{"header_redesign_enabled":false,"results":[{"id":"191574673","archived":true,"color":"#DAE1C2","followers":34,"has_funding_file":false,"hl_name":"name1e5s/Sirius","hl_trunc_description":"Asymmetric dual issue in-order microprocessor.","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":191574673,"name":"Sirius","owner_id":15176913,"owner_login":"name1e5s","updated_at":"2019-08-27T14:19:57.003Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public archive","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":67,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aname1e5s%252FSirius%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/name1e5s/Sirius/star":{"post":"sWC35BjURv9UPtyBloJ1mulpgLUCD8rA8PvU-7JBouwTkMi0y0IGSQTr34IWvvQ-PrHmzskBr0LSsW-pIcJLYA"},"/name1e5s/Sirius/unstar":{"post":"FXRGSzcw4p9NVaM0SVv0Z4ZUCMRR6GyLAn3wxRrJ1MPJbT-dQ12VU9h5qd6GgeL7XMOYMezBz_5xjsMSUckrpQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"y6QzudXT7YIc6A8iUqLeq7lwrjcGEu7y-r8RzHZ4qWi2OCDefVr8D5Eol8rt7Pjr3hhNGHPNwUXA9BcXstr59A"}}},"title":"Repository search results"}