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a/lib/stlink/bin/Qt5SerialPort.dll b/lib/stlink/bin/Qt5SerialPort.dll index ce5b579d..b0a1107b 100644 Binary files a/lib/stlink/bin/Qt5SerialPort.dll and b/lib/stlink/bin/Qt5SerialPort.dll differ diff --git a/lib/stlink/bin/Qt5Xml.dll b/lib/stlink/bin/Qt5Xml.dll index b84a8208..8a99234e 100644 Binary files a/lib/stlink/bin/Qt5Xml.dll and b/lib/stlink/bin/Qt5Xml.dll differ diff --git a/lib/stlink/bin/STLinkUSBDriver.dll b/lib/stlink/bin/STLinkUSBDriver.dll index 551fe259..58e4f82b 100644 Binary files a/lib/stlink/bin/STLinkUSBDriver.dll and b/lib/stlink/bin/STLinkUSBDriver.dll differ diff --git a/lib/stlink/bin/STM32_Programmer_CLI.exe b/lib/stlink/bin/STM32_Programmer_CLI.exe index b867a361..57160b89 100644 Binary files a/lib/stlink/bin/STM32_Programmer_CLI.exe and b/lib/stlink/bin/STM32_Programmer_CLI.exe differ diff --git a/lib/stlink/bin/libeay32.dll b/lib/stlink/bin/libeay32.dll index 30367c3d..ed8fe170 100644 Binary files a/lib/stlink/bin/libeay32.dll and b/lib/stlink/bin/libeay32.dll differ diff --git a/lib/stlink/bin/libgcc_s_seh-1.dll b/lib/stlink/bin/libgcc_s_seh-1.dll deleted file mode 100644 index b9dc93e8..00000000 Binary files a/lib/stlink/bin/libgcc_s_seh-1.dll and /dev/null differ diff --git a/lib/stlink/bin/libstdc++-6.dll b/lib/stlink/bin/libstdc++-6.dll index 9ec805ec..26d06cba 100644 Binary files a/lib/stlink/bin/libstdc++-6.dll and b/lib/stlink/bin/libstdc++-6.dll differ diff --git a/lib/stlink/bin/libwinpthread-1.dll b/lib/stlink/bin/libwinpthread-1.dll index c4b4c8d1..73ef1ab1 100644 Binary files a/lib/stlink/bin/libwinpthread-1.dll and b/lib/stlink/bin/libwinpthread-1.dll differ diff --git a/lib/stlink/bin/mfc120.dll b/lib/stlink/bin/mfc120.dll index 7c0b92c4..15af73cd 100644 Binary files a/lib/stlink/bin/mfc120.dll and b/lib/stlink/bin/mfc120.dll differ diff --git a/lib/stlink/bin/msvcp120.dll b/lib/stlink/bin/msvcp120.dll index 4ea1efa7..a237d2d7 100644 Binary files a/lib/stlink/bin/msvcp120.dll and b/lib/stlink/bin/msvcp120.dll differ diff --git a/lib/stlink/bin/msvcr100.dll b/lib/stlink/bin/msvcr100.dll deleted file mode 100644 index 329b1114..00000000 Binary files a/lib/stlink/bin/msvcr100.dll and /dev/null differ diff --git a/lib/stlink/bin/msvcr120.dll b/lib/stlink/bin/msvcr120.dll index d711c922..8c36149a 100644 Binary files a/lib/stlink/bin/msvcr120.dll and b/lib/stlink/bin/msvcr120.dll differ diff --git a/lib/stlink/bin/stlibp11_SAM.conf b/lib/stlink/bin/stlibp11_SAM.conf index 704ae3af..722fc5ea 100644 --- a/lib/stlink/bin/stlibp11_SAM.conf +++ b/lib/stlink/bin/stlibp11_SAM.conf @@ -1,6 +1,6 @@ [Global] OutputFolder=C:\Users\JoséSimões/STMicroelectronics/STM32CubeProgrammer/ -InputFolder=C:\Users\JoséSimões/STMicroelectronics/STM32CubeProgrammer/HSM/data/ +InputFolder=HSM/data/ [Info] IC.Label=SAM diff --git a/lib/stlink/bin/stlibp11_SAM.dll b/lib/stlink/bin/stlibp11_SAM.dll index 54b46abd..b35bab3d 100644 Binary files a/lib/stlink/bin/stlibp11_SAM.dll and b/lib/stlink/bin/stlibp11_SAM.dll differ diff --git a/lib/stlink/bin/xerces-c_3_1.dll b/lib/stlink/bin/xerces-c_3_1.dll index 43648702..133e16ea 100644 Binary files a/lib/stlink/bin/xerces-c_3_1.dll and b/lib/stlink/bin/xerces-c_3_1.dll differ diff --git a/lib/stlink/bin/zlib1.dll b/lib/stlink/bin/zlib1.dll deleted file mode 100644 index 994ef6d4..00000000 Binary files a/lib/stlink/bin/zlib1.dll and /dev/null differ diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x415.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x415.xml index 6c667ba6..46999e7e 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x415.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x415.xml @@ -60,13 +60,13 @@ - + - + @@ -100,8 +100,10 @@ 0xFF RWE + + - + Dual diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x419.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x419.xml index c2ceb99b..92bc1ae4 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x419.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x419.xml @@ -101,6 +101,7 @@ 0xFF RWE + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x425.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x425.xml index 3ac1f747..5ec6a4f9 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x425.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x425.xml @@ -65,6 +65,7 @@ 0x00 RWE + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x427.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x427.xml index 94733176..8f8c1ee5 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x427.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x427.xml @@ -141,7 +141,7 @@ Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 - R + RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection @@ -161,7 +161,7 @@ Sector protection mode selection option byte. 0x8 0x1 - R + RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection @@ -180,7 +180,7 @@ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 - R + RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V @@ -210,7 +210,7 @@ 0x14 0x1 - R + RW Hardware independant watchdog Software independant watchdog @@ -221,7 +221,7 @@ 0x15 0x1 - R + RW Reset generated when entering Stop mode No reset generated @@ -232,7 +232,7 @@ 0x16 0x1 - R + RW Reset generated when entering Standby mode No reset generated @@ -251,7 +251,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -262,7 +262,7 @@ 0x0 0x20 - R + RW read/Write protection active read/Write protection not active @@ -278,7 +278,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -289,231 +289,7 @@ 0x0 0x20 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP32 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - WRP48 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP48 - - 0x0 - 0x10 - W + RW read/Write protection active read/Write protection not active diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x429.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x429.xml index 4a11fef4..c8bdc84c 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x429.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x429.xml @@ -141,7 +141,7 @@ Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 - R + RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection @@ -161,7 +161,7 @@ Sector protection mode selection option byte. 0x8 0x1 - R + RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection @@ -180,7 +180,7 @@ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 - R + RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V @@ -210,7 +210,7 @@ 0x14 0x1 - R + RW Hardware independant watchdog Software independant watchdog @@ -221,7 +221,7 @@ 0x15 0x1 - R + RW Reset generated when entering Stop mode No reset generated @@ -232,7 +232,7 @@ 0x16 0x1 - R + RW Reset generated when entering Standby mode No reset generated @@ -251,7 +251,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -262,7 +262,7 @@ 0x0 0x20 - R + RW read/Write protection active read/Write protection not active @@ -272,176 +272,6 @@ - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x436.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x436.xml index 0ce44164..8141b0d1 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x436.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x436.xml @@ -42,10 +42,10 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE - + - + Dual 0x4 diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x437.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x437.xml index 3cc4bc09..e8f00736 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x437.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x437.xml @@ -134,7 +134,7 @@ Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 - R + RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection @@ -154,7 +154,7 @@ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 - R + RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V @@ -184,7 +184,7 @@ 0x14 0x1 - R + RW Hardware independant watchdog Software independant watchdog @@ -195,7 +195,7 @@ 0x15 0x1 - R + RW Reset generated when entering Stop mode No reset generated @@ -206,7 +206,7 @@ 0x16 0x1 - R + RW Reset generated when entering Standby mode No reset generated @@ -217,7 +217,7 @@ 0x17 0x1 - R + RW If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 @@ -236,7 +236,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -252,7 +252,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -268,7 +268,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -284,7 +284,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -294,111 +294,6 @@ - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x7 - 0x1 - W - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x443.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x443.xml index 61c3f692..fa3f8274 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x443.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x443.xml @@ -44,6 +44,7 @@ 0xFF RWE + @@ -438,9 +439,9 @@ - + FLASH security @@ -844,9 +845,9 @@ - + FLASH security diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x453.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x453.xml index 11762df7..e24b4002 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x453.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x453.xml @@ -4,8 +4,9 @@ 0x453 STMicroelectronics MCU + Cortex-M0+ - STM32C0 BigSpider + STM32C03x STM32C0 ARM 32-bit Cortex-M0+ based device @@ -23,14 +24,14 @@ 0x00 RWE - + - + Single - + @@ -42,7 +43,8 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE - + + @@ -56,7 +58,7 @@ - + OTP Storage @@ -83,11 +85,11 @@ RW - + Read Out Protection - + RDP @@ -96,9 +98,9 @@ 0x8 RW - Level 0, read protection not active - or any value other than 0xAA and 0xCC: Level 1,read protection of memories active - Level 2, chip read protection active + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection @@ -110,12 +112,41 @@ - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + BOR_EN + 0x8 - 0x5 + 0x1 + RW + + Configurable brown out reset disabled, power-on reset defined by POR/PDR levels + Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account + + + + BORR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x9 + 0x2 RW - + + BOR falling level 1 with threshold around 2.1 V + BOR falling level 2 with threshold around 2.3 V + BOR falling level 3 with threshold around 2.6 V + BOR falling level 4 with threshold around 2.9 V + + + + BORF_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0xB + 0x2 + RW + + BOR rising level 1 with threshold around 2.0 V + BOR rising level 2 with threshold around 2.2 V + BOR rising level 3 with threshold around 2.5 V + BOR rising level 4 with threshold around 2.8 V + @@ -123,7 +154,7 @@ User Configuration - + nRST_STOP @@ -148,7 +179,7 @@ - nRST_HDW + nRST_SHDW 0xF 0x1 @@ -202,6 +233,17 @@ Software window watchdog + + HSE_NOT_REMAPPED + + 0x15 + 0x1 + RW + + HSE_NOT_REMAPPED enable + HSE_NOT_REMAPPED disable + + RAM_PARITY_CHECK @@ -209,8 +251,19 @@ 0x1 RW - SRAM2 parity check enable - SRAM2 parity check disable + RAM_PARITY_CHECK enable + RAM_PARITY_CHECK disable + + + + SECURE_MUXING_EN + + 0x17 + 0x1 + RW + + SECURE_MUXING_EN disable + SECURE_MUXING_EN enable @@ -220,8 +273,8 @@ 0x1 RW - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit + BOOT0 pin (legacy mode) + nBOOT0 option bit @@ -234,7 +287,7 @@ Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory - + nBOOT0 @@ -245,29 +298,21 @@ nBOOT0=0 nBOOT0=1 - - - NGPIO_MODE + + + NRST_MODE 0x1B - 0x1 + 0x2 RW - NGPIO_MODE=0 - NOT_GPIO_MODE_ONLY: NGPIO_MODE=1 + Reserved + Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin + GPIO: standard GPIO pad functionality, only internal RESET possible + Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) + - - NRST_MODE - - 0x1C - 0x1 - RW - - NRST_MODE=0 - Reset Input only: NRST_MODE=1 - - IRHEN Internal reset holder enable bit @@ -278,7 +323,7 @@ Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level - + @@ -293,7 +338,7 @@ 0x0 0x6 RW - + @@ -306,7 +351,7 @@ 0x0 0x6 RW - + PCROP_RDP @@ -330,7 +375,7 @@ 0x0 0x6 RW - + @@ -343,10 +388,10 @@ 0x0 0x6 RW - + - + Write Protection @@ -355,11 +400,11 @@ WRP1A_STRT - Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + TStart offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect 0x0 0x4 RW - + WRP1A_END @@ -367,7 +412,7 @@ 0x10 0x4 RW - + @@ -380,7 +425,7 @@ 0x0 0x4 RW - + WRP1B_END @@ -388,16 +433,28 @@ 0x10 0x4 RW - + + + FLASH security + + SEC_SIZE + Securable memory area size + 0x0 + 0x5 + RW + + BOOT_LOCK Used to force boot from user area @@ -409,24 +466,17 @@ Boot forced from Main Flash memory - - SEC_SIZE - Sticky area width( Number of FLASH pages) - 0x0 - 0x5 - RW - - + - - + + Read Out Protection - + RDP @@ -435,9 +485,9 @@ 0x8 RW - Level 0, read protection not active - or any value other than 0xAA and 0xCC: Level 1,read protection of memories active - Level 2, chip read protection active + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection @@ -446,15 +496,46 @@ BOR Level - + - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + BOR_EN + 0x8 - 0x5 + 0x1 + RW + + Configurable brown out reset disabled, power-on reset defined by POR/PDR levels + Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account + + + + + BORR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x9 + 0x2 RW - + + BOR falling level 1 with threshold around 2.1 V + BOR falling level 2 with threshold around 2.3 V + BOR falling level 3 with threshold around 2.6 V + BOR falling level 4 with threshold around 2.9 V + + + + + BORF_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0xB + 0x2 + RW + + BOR rising level 1 with threshold around 2.0 V + BOR rising level 2 with threshold around 2.2 V + BOR rising level 3 with threshold around 2.5 V + BOR rising level 4 with threshold around 2.8 V + @@ -462,7 +543,7 @@ User Configuration - + nRST_STOP @@ -487,7 +568,7 @@ - nRST_HDW + nRST_SHDW 0xF 0x1 @@ -541,6 +622,17 @@ Software window watchdog + + HSE_NOT_REMAPPED + + 0x15 + 0x1 + RW + + HSE_NOT_REMAPPED enable + HSE_NOT_REMAPPED disable + + RAM_PARITY_CHECK @@ -548,8 +640,20 @@ 0x1 RW - SRAM2 parity check enable - SRAM2 parity check disable + RAM_PARITY_CHECK enable + + RAM_PARITY_CHECK disable + + + + SECURE_MUXING_EN + + 0x17 + 0x1 + RW + + SECURE_MUXING_EN disable + SECURE_MUXING_EN enable @@ -559,8 +663,8 @@ 0x1 RW - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit + BOOT0 pin (legacy mode) + nBOOT0 option bit @@ -570,10 +674,13 @@ 0x1 RW + + Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory - + + nBOOT0 @@ -584,29 +691,31 @@ nBOOT0=0 nBOOT0=1 - - - NGPIO_MODE + + + NRST_MODE 0x1B - 0x1 + 0x2 RW - NGPIO_MODE=0 - NOT_GPIO_MODE_ONLY: NGPIO_MODE=1 + Reserved + Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin + GPIO: standard GPIO pad functionality, only internal RESET possible + Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) + - - NRST_MODE - - 0x1C - 0x1 - RW - - NRST_MODE=0 - Reset Input only: NRST_MODE=1 - - + + + + + + + + + + IRHEN Internal reset holder enable bit @@ -617,7 +726,8 @@ Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level - + + @@ -632,12 +742,12 @@ 0x0 0x6 RW - + - + PCROP1A_END @@ -645,7 +755,7 @@ 0x0 0x6 RW - + PCROP_RDP @@ -654,14 +764,14 @@ 0x1 RW - PCROP zone is kept when RDP is decreased; Partial Mass Erase done + PCROP zone is kept when RDP is decreased Partial Mass Erase done PCROP zone is erased when RDP is decreased Full Mass Erase done - - + + PCROP1B_STRT @@ -669,12 +779,12 @@ 0x0 0x6 RW - + - + PCROP1B_END @@ -682,7 +792,7 @@ 0x0 0x6 RW - + @@ -690,36 +800,39 @@ Write Protection - + WRP1A_STRT Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + 0x0 0x4 RW - + WRP1A_END End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. + 0x10 0x4 RW - + - + WRP1B_STRT Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect + 0x0 0x4 RW - + WRP1B_END @@ -727,14 +840,14 @@ 0x10 0x4 RW - + - + - + FLASH security @@ -753,7 +866,7 @@ SEC_SIZE - Sticky area width( Number of FLASH pages) + Securable memory area size 0x0 0x5 RW diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x458.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x458.xml index 0e24985f..f360eb2c 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x458.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x458.xml @@ -82,13 +82,13 @@ RW - + Single 0x4 - + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x460.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x460.xml index 4c5a7a9d..a70f6319 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x460.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x460.xml @@ -65,6 +65,10 @@ 0xFF RWE + + + + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x461.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x461.xml index d86041e9..052a4e90 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x461.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x461.xml @@ -43,6 +43,8 @@ 0xFF RWE + + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x464.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x464.xml index d7bdef5f..d947a3b0 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x464.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x464.xml @@ -43,6 +43,8 @@ 0xFF RWE + + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x466.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x466.xml index 4caeea63..5bee4648 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x466.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x466.xml @@ -347,12 +347,12 @@ - + PCROP Protection - + PCROP1A_STRT Flash Area A PCROP start address 0x0 @@ -389,7 +389,7 @@ - + PCROP1B_STRT Flash Area B PCROP start address 0x0 @@ -402,7 +402,7 @@ - + PCROP1B_END Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 @@ -458,7 +458,7 @@ - + FLASH security @@ -706,7 +706,7 @@ - + PCROP Protection @@ -794,7 +794,7 @@ - + FLASH security diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x468.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x468.xml index 52930f42..0a153c3b 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x468.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x468.xml @@ -103,7 +103,7 @@ RW - + Read Out Protection @@ -395,9 +395,6 @@ - - - Secure Protection @@ -426,7 +423,7 @@ - + Read Out Protection @@ -723,9 +720,6 @@ - - - Secure Protection diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x470.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x470.xml index dc74ca98..7c93abee 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x470.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x470.xml @@ -105,6 +105,8 @@ 0xFF RWE + + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x471.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x471.xml index ae94939f..92121d52 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x471.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x471.xml @@ -105,6 +105,8 @@ 0xFF RWE + + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x474.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x474.xml new file mode 100644 index 00000000..5daff1ea --- /dev/null +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x474.xml @@ -0,0 +1,3628 @@ + + + + 0x474 + STMicroelectronics + MCU + Cortex-M33 + STM32H50x + STM32H5 + ARM 32-bit Cortex-M33 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0xFF + RWE + + + + + Single + + + + + + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0xFF + RWE + + + + + Dual + 0x4 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in standby Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + + + User Configuration 2 + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + R + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + + + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + W + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + + + User Configuration 2 + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + R + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + + + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + W + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + W + + Disabled + Enabled + + + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + R + + Disabled + Enabled + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress + 0x0 + 0x20 + R + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress. + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + + + + Flash EPOCH + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + + + + + \ No newline at end of file diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x479.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x479.xml index 74d305ac..755c60e1 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x479.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x479.xml @@ -117,7 +117,7 @@ RW - + Read Out Protection @@ -472,7 +472,7 @@ SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 - 0x8 + 0x9 RW @@ -846,7 +846,7 @@ SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 - 0x8 + 0x9 RW diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x481.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x481.xml index c823ee48..bf1f6f08 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x481.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x481.xml @@ -42,17 +42,21 @@ + + + + @@ -95,7 +99,7 @@ 0xFF RWE - + @@ -160,7 +164,7 @@ The Data EEPROM memory block. It contains user data. 0xFF RWE - + Single @@ -171,7 +175,7 @@ - + Single @@ -281,6 +285,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -315,14 +330,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -490,17 +505,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -787,6 +791,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -821,14 +836,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -1007,17 +1022,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -1461,6 +1465,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneouslyDescription + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -1495,14 +1510,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -1681,17 +1696,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -2153,6 +2157,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -2187,14 +2202,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -2362,26 +2377,15 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - Boot Configuration - + - + NSBOOTADD0 Non-secure Boot base address 0 0x7 @@ -2390,11 +2394,11 @@ - + - + NSBOOTADD1 Non-secure Boot base address 1 0x7 @@ -2404,7 +2408,100 @@ + + + + + SECBOOTADD0 + Secure boot base address 0 + 0x7 + 0x19 + RW + + + + + + + + + BOOT_LOCK + The boot is always forced to base address value programmed in SECBOOTADD0 + 0x0 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from base address memory + + + + + + Secure Area 1 + + + + + SECWM1_PSTRT + Start page of first secure area + 0x0 + 0x8 + RW + + + + SECWM1_PSTRT + Start page of first secure area + 0x0 + 0x8 + RW + + + + SECWM1_PEND + End page of first secure area + 0x10 + 0x8 + RW + + + + SECWM1_PEND + End page of first secure area + 0x10 + 0x8 + RW + + + + + + + + + HDP1_PEND + End page of first hide protection area + 0x10 + 0x8 + RW + + + + HDP1EN + Hide protection first area enable + 0x1F + 0x1 + RW + + No HDP area 1 + HDP first area is enabled + + + + + Write Protection 1 @@ -2503,6 +2600,70 @@ + + + Secure Area 2 + + + + + SECWM2_PSTRT + Start page of second secure area + 0x0 + 0x8 + RW + + + + SECWM2_PSTRT + Start page of second secure area + 0x0 + 0x8 + RW + + + + SECWM2_PEND + End page of second secure area + 0x10 + 0x8 + RW + + + + SECWM2_PEND + End page of second secure area + 0x10 + 0x8 + RW + + + + + + + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x8 + RW + + + + HDP2EN + Hide protection second area enable + 0x1F + 0x1 + RW + + No HDP area 2 + HDP second area is enabled + + + + Write Protection 2 @@ -2602,7 +2763,7 @@ - + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x482.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x482.xml index c1ba5900..288c9d95 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x482.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x482.xml @@ -107,7 +107,7 @@ 0xFF RWE - + @@ -172,7 +172,7 @@ The Data EEPROM memory block. It contains user data. 0xFF RWE - + Single @@ -183,7 +183,7 @@ - + Single @@ -245,7 +245,7 @@ RW - + Read Out Protection @@ -293,6 +293,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -502,17 +513,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -799,6 +799,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -1019,17 +1030,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -1492,6 +1492,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -1712,17 +1723,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -2184,6 +2184,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -2349,17 +2360,6 @@ USB power delivery dead-battery disabled/ TDI pull-up activated - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x484.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x484.xml index 937102a4..99573d39 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x484.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x484.xml @@ -56,12 +56,12 @@ - + Single - + @@ -159,7 +159,7 @@ Configuration RW - + @@ -989,9 +989,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 R - + BOOT_LOCK_NS @@ -1010,9 +1010,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 W - + BOOT_LOCK_NS @@ -1075,7 +1075,52 @@ - + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + R + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + R + + + + + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + W + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + W + + + + + Write sector group protection 1 @@ -1107,7 +1152,52 @@ - + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + R + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + R + + + + + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + W + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + W + + + + + Write sector group protection 2 @@ -1433,7 +1523,7 @@ - + @@ -2263,9 +2353,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 R - + BOOT_LOCK_NS @@ -2284,9 +2374,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 W - + BOOT_LOCK_NS @@ -2349,7 +2439,52 @@ - + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + R + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + R + + + + + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + W + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + W + + + + + Write sector group protection 1 @@ -2381,7 +2516,52 @@ - + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + R + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + R + + + + + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + W + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + W + + + + + Write sector group protection 2 @@ -2707,6 +2887,1886 @@ + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + R + + Disabled + Enabled + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress + 0x0 + 0x20 + R + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress. + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + + + + Flash EPOCH + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x485.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x485.xml new file mode 100644 index 00000000..f3b430f6 --- /dev/null +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x485.xml @@ -0,0 +1,760 @@ + + + + 0x485 + STMicroelectronics + MCU + Cortex-M7 + STM32H7Rxx + STM32H7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x20 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Flash Non Volatile State + + + + + FLASH_NVSR + FLASH security status register programming. + 0x0 + 0x8 + R + + OPEN device + CLOSED device + + + + + + + + + FLASH_NVSR + FLASH security status register programming. + 0x0 + 0x8 + W + + OPEN device + CLOSED device + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + R + + BOR OFF + BOR level1: 2.1V + BOR level2: 2.4 V + BOR level3: 2.7 V + + + + + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + W + + reset level is set to 0.0 V + reset level is set to 2.1 V + reset level is set to 2.4 V + reset level is set to 2.7 V + + + + + + + User Configuration1 + + + + + IWDG1_SW + + 0x4 + 0x1 + R + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + R + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + IO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + R + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + R + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + OCTO1_HSLV + + 0x8 + 0x1 + R + + I/O Octo1 High-Speed option disabled + I/O Octo1 High-Speed option enabled + + + + OCTO2_HSLV + + 0x9 + 0x1 + R + + I/O Octo2 High-Speed option disabled + I/O Octo2 High-Speed option enabled + + + + + + + + + IWDG1_SW + + 0x4 + 0x1 + W + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + W + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + IO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + W + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + W + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + OCTO1_HSLV + + 0x8 + 0x1 + W + + I/O Octo1 High-Speed option disabled + I/O Octo1 High-Speed option enabled + + + + OCTO2_HSLV + + 0x9 + 0x1 + W + + I/O Octo2 High-Speed option disabled + I/O Octo2 High-Speed option enabled + + + + + + + User Configuration 2 + + + + + I2c_NI3C + + 0x9 + 0x1 + R + + I3C is selected + I2C is delected + + + + ECC_ON_SRAM + + 0x8 + 0x1 + R + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + + I2c_NI3C + + 0x9 + 0x1 + W + + I3C is selected + I2C is delected + + + + ECC_ON_SRAM + + 0x8 + 0x1 + W + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + DTCM RAM Protection + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + R + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + W + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + ITCM RAM Protection + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + R + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + W + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + nWRP0 + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + Flash HDP bank + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x9 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x9 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x9 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x9 + W + + + + + + + + Flash EPOCH + + + + + EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + OTP write protection + + + + + LOCKBL + OTP Lock + 0x0 + 0x10 + R + + + + + + + + + LOCKBL + OTP Lock + 0x0 + 0x10 + W + + + + + + + + FLASH ROT programming + + + + + OEM_PROV + OEM provisioned device + 0x0 + 0x8 + R + + + IROT_SELECT + OEM provisioned device + 0x18 + 0x8 + R + + + DBG_AUTH + Debug authentication method + 0x8 + 0x8 + R + + + + + + + + IROT_SELECT + OEM provisioned device + 0x18 + 0x8 + W + + + DBG_AUTH + Debug authentication method + 0x8 + 0x8 + W + + + OEM_PROV + OEM provisioned device + 0x0 + 0x8 + W + + + + + + + FLASH fixed bank + + + + + NUM_FIXED_SECT + Number of fixed sectors + 0x1 + 0x3 + R + + + + EN_SWAP_BANK + enable swap bank + 0x10 + 0x1 + R + + swap bank disable + swap bank enable + + + + LOCK_FIXED + lock fixed + 0x14 + 0x1 + R + + lock disable + lock enable + + + + + + + + + NUM_FIXED_SECT + Number of fixed sectors + 0x1 + 0x3 + W + + + + EN_SWAP_BANK + enable swap bank + 0x10 + 0x1 + W + + swap bank disable + swap bank enable + + + + LOCK_FIXED + lock fixed + 0x14 + 0x1 + W + + lock disable + lock enable + + + + + + + + + + + + \ No newline at end of file diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x497.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x497.xml index a41e44b8..9664177b 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x497.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x497.xml @@ -10,7 +10,14 @@ ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device - + + + + + + + + @@ -295,7 +302,7 @@ CPU1 CM4 Boot lock enabled - + C2BOOT_LOCK 0x1F @@ -311,7 +318,7 @@ - + IPCCDBA IPCC mailbox data buffer base address 0x0 @@ -459,14 +466,14 @@ - + SFSA This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area. 0x0 0x7 RW - + FSD 0x7 @@ -477,7 +484,7 @@ System and Flash non-secure. This bit can only be accessed when HDPADIS = 0 - + DDS 0xC @@ -488,14 +495,14 @@ CPU2 debug access disabled (when also enabled by C2SWDBGEN) - + HDPSA HDPSA[6:0] contain the start address of the first 2 kB page of the User Flash hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash hide protection area enabled. 0x10 0x7 RW - + HDPAD User Flash hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0 0x17 @@ -507,7 +514,7 @@ - + SUBGHSPISD SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled 0x1F @@ -523,7 +530,7 @@ - + C2OPT 0x1F @@ -534,7 +541,7 @@ SBRV will address Flash memory, from start address 0x0800 0000 + SBRV. - + NBRSD 0x1E @@ -545,14 +552,14 @@ SRAM1 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 - + SNBRSA SNBRSA[4:0] contain the start address of the first 1 kB page of the secure "non-backup" SRAM1 area. To keep the tool working you have to set a value greater or equal to 0xC 0x19 0x5 RW - + BRSD 0x17 @@ -563,14 +570,14 @@ SRAM2 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 - + SBRSA SBRSA[4:0] contain the start address of the first 1 kB page of the secure backup SRAM2 area. To keep the tool working you have to set a value less than 0x15 0x12 0x5 RW - + SBRV SBRV[15:0] contain the word (4B) aligned CPU2 boot reset start address offset within the selected memory area by C2OPT. 0x0 diff --git a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x501.xml b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x501.xml index 2e866a6d..df5f1fcc 100644 --- a/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x501.xml +++ b/lib/stlinkLinux/Data_Base/STM32_Prog_DB_0x501.xml @@ -47,11 +47,11 @@ OTP - + - none - none + version + Structure version 0x0 0x20 R @@ -59,1755 +59,1837 @@ - + - TR - set SAFMEM Ring current level, default value = 0b00 - 0x7 - 0x2 - RW - - - PRGWIDTH - SAFMEM Programming Pulse Width, default value = 0b0001 - 0x3 - 0x4 - RW - - - FRC - SAFMEM CLOCK frequency range selection, default value = 0b11 - 0x1 - 0x2 - RW - - - PWRUP - SAFMEM Power up control + Value + BSEC state 0x0 - 0x1 - RW + 0x2 + R - + - BIST2LOCK - 0: BIST2 is not locked, 1: BIST2 is locked. - 0x7 - 0x1 - R - - - BIST1LOCK - 0: BIST1 is not locked, 1: BIST1 is locked. - 0x6 - 0x1 - R - - - PWRON - 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. - 0x5 - 0x1 - R - - - PROGFAIL - 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. - 0x4 - 0x1 - R - - - BUSY - 0: SAFMEM is Idle, 1: SAFMEM operation is on going. - 0x3 - 0x1 - R - - - INVALID - 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. - 0x2 - 0x1 - R - - - FULLDBG - 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. - 0x1 - 0x1 - R + Data + Data + 0x0 + 0x20 + RW - SECURE - 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. - 0x0 - 0x1 + Status + Status + 0x4 + 0x20 R - + - GPLOCK - 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. - 0x4 - 0x1 - RW - - - FENREG - 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. - 0x3 - 0x1 - RW - - - DENREG - 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. - 0x2 - 0x1 + Data + Data + 0x0 + 0x20 RW - OTP - 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - DBGSWENABLE - Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. - 0xA - 0x1 - RW - - - CFGSDISABLE - Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. - 0x9 - 0x1 - RW - - - CP15SDISABLE - Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. - 0x7 - 0x2 - RW - - - SPNIDEN - Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. - 0x6 - 0x1 - RW - - - SPIDEN - Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. - 0x5 - 0x1 - RW - - - HDPEN - Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. - 0x4 - 0x1 - RW - - - DEVICEEN - Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. - 0x3 - 0x1 - RW - - - NIDEN - Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. - 0x2 - 0x1 - RW - - - DBGEN - Debug enable with signal dbgen. 0: Disabled, 1: Enabled. - 0x1 - 0x1 + Data + Data + 0x0 + 0x20 RW - DFTEN - DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - CAN_disable - 0: CAN interface is enabled, 1: CAN interface is disabled. - 0x3 - 0x1 - RW - - - GPU_disable - 0: GPU enabled, 1: GPU disabled. - 0x2 - 0x1 - RW - - - Dual_A7_disable - 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. - 0x1 - 0x1 + Data + Data + 0x0 + 0x20 RW - Crypto_disable - 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - W_R conf - This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM + Data + Data 0x0 - 0x1 + 0x20 RW - - - - - - BSEC_OTP_DISTURBED0 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 + Status + Status + 0x4 0x20 R - + - BSEC_OTP_DISTURBED1 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + Data + Data 0x0 0x20 - R + RW - - - - - - BSEC_OTP_DISTURBED2 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 + Status + Status + 0x4 0x20 R - + - BSEC_OTP_ERROR0 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + Data + Data 0x0 0x20 - R + RW - - - - - - BSEC_OTP_ERROR1 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 + Status + Status + 0x4 0x20 R - + - BSEC_OTP_ERROR2 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + Data + Data 0x0 0x20 - R + RW - - - - - - BSEC_OTP_WRLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_WRLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_WRLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SPLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SPLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SPLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SWLOCK0 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SWLOCK1 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SWLOCK2 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SRLOCK0 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SRLOCK1 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SRLOCK2 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + Data + Data 0x0 0x20 RW - - - - - - CFG0 - These bits determins the OTP mode encoding - 0x0 - 0x7 - RW + Status + Status + 0x4 + 0x20 + R - + - fdis3 - Disable CAN - 0x3 - 0x1 - RW - - - fdis2 - Disable GPU - 0x2 - 0x1 - RW - - - fdis1 - Disable CPU1 - 0x1 - 0x1 + Data + Data + 0x0 + 0x20 RW - fdis0 - Disable Crypto (license export) - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - rma_force - RMA force Bit + Data + Data 0x0 - 0x1 + 0x20 RW - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - CFG3 - These bits determins the BOOT source definition + Data + Data 0x0 0x20 RW - - - - - - CFG4 - These bits determins the BOOT monotonic counter - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - CFG5 - These bits determins the BOOT AFmux configuration + Data + Data 0x0 0x20 RW - - - - - - CFG6 - These bits determins the BOOT AFmux configuration - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - CFG7 - These bits determins the BOOT AFmux configuration + Data + Data 0x0 0x20 RW - - - - - - - CFG8 - BOOT/Device configuration. - 0x2 - 0x1E - RW - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - rma_lock - RMA lock Bit - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - CFG9 - These bits determin the device configuration. + Data + Data 0x0 0x20 RW - - - - - - CFG10 - These bits determin the device configuration. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - CFG11 - These bits determin the device configuration. + Data + Data 0x0 0x20 RW - - - - - - CFG12 - These bits determin the device configuration. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - ID0 - Lot ID on 42bit (11LSB's) - 0x15 - 0xB - RW - - - ID0 - Wafer ID - 0x10 - 0x5 - RW - - - ID0 - Wafer Y coordinates - 0x8 - 0x8 - RW - - - ID0 - Wafer X coordinates + Data + Data 0x0 - 0x8 + 0x20 RW - - - - - - ID1 - Lot ID on 42bit (31MSB's) - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - ID2 - Test program flow T[12],F[12],Q[12] - 0x14 - 0xC - RW - - - ID2 - FT program revision - 0xA - 0xA - RW - - - ID2 - EWS program revision + Data + Data 0x0 - 0xA + 0x20 RW - - - - - - HW0 - Analog TRIM - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW1 - Analog TRIM + Data + Data 0x0 0x20 RW - - - - - - HW2 - Analog TRIM and hardware options - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW3 - Analog TRIM + Data + Data 0x0 0x20 RW - - - - - - HW4 - not used yet - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW5 - memory repair bits + Data + Data 0x0 0x20 RW - - - - - - HW6 - memory repair bits - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW7 - reserved + Data + Data 0x0 0x20 RW - - - - - - PKH0 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH1 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - PKH2 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH3 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - PKH4 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH5 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - PKH6 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH7 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - XK0 - ST ECDSA Private Key for SSP - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - XK1 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW - - - - - - XK2 - ST ECDSA Private Key for SSP - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - XK3 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW - - - - - - XK4 - ST ECDSA Private Key for SSP - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - XK5 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK6 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK7 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK8 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK9 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK10 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK11 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK12 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK13 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK14 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK15 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK16 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK17 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK18 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK19 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK20 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK21 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK22 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK23 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK24 - RMA lock and relock passwords + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK25 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK26 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK27 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK28 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK29 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK30 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK31 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK32 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK33 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK34 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK35 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK36 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK37 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK38 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK39 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK40 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK41 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK42 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK43 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK44 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK45 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK46 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK47 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK48 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK49 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK50 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK51 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK52 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK53 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK54 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK55 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK56 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK57 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK58 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK59 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK60 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK61 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK62 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK63 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - ECC_USE - SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. - 0x4 - 0x4 - R + Data + Data + 0x0 + 0x20 + RW - SAFMEM_SIZE - SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. - 0x0 - 0x4 + Status + Status + 0x4 + 0x20 R - + - MAJREV - IP Version major revision information. - 0x4 - 0x4 - R + Data + Data + 0x0 + 0x20 + RW - MINREV - IP Version minor revision information. - 0x0 - 0x4 + Status + Status + 0x4 + 0x20 R - + - ID - IP Identification. + Data + Data 0x0 0x20 + RW + + + Status + Status + 0x4 + 0x20 R - + - ID - IP Magic Identification. + Data + Data 0x0 0x20 + RW + + + Status + Status + 0x4 + 0x20 R diff --git a/lib/stlinkLinux/bin/FlashLoader/0x427.stldr b/lib/stlinkLinux/bin/FlashLoader/0x427.stldr index 06bba015..47e043e1 100644 Binary files a/lib/stlinkLinux/bin/FlashLoader/0x427.stldr and b/lib/stlinkLinux/bin/FlashLoader/0x427.stldr differ diff --git a/lib/stlinkLinux/bin/FlashLoader/0x429.stldr b/lib/stlinkLinux/bin/FlashLoader/0x429.stldr index a904e024..0329c00e 100644 Binary files a/lib/stlinkLinux/bin/FlashLoader/0x429.stldr and b/lib/stlinkLinux/bin/FlashLoader/0x429.stldr differ diff --git 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diff --git a/lib/stlinkLinux/bin/FlashLoader/0x492.stldr b/lib/stlinkLinux/bin/FlashLoader/0x492.stldr index 34c10a46..40a9399e 100644 Binary files a/lib/stlinkLinux/bin/FlashLoader/0x492.stldr and b/lib/stlinkLinux/bin/FlashLoader/0x492.stldr differ diff --git a/lib/stlinkLinux/bin/FlashLoader/0x494_FUS_Operator.bin b/lib/stlinkLinux/bin/FlashLoader/0x494_FUS_Operator.bin index 4f57eafa..3698d0b6 100644 Binary files a/lib/stlinkLinux/bin/FlashLoader/0x494_FUS_Operator.bin and b/lib/stlinkLinux/bin/FlashLoader/0x494_FUS_Operator.bin differ diff --git a/lib/stlinkLinux/bin/FlashLoader/0x495_FUS_Operator.bin b/lib/stlinkLinux/bin/FlashLoader/0x495_FUS_Operator.bin index 13afc635..f26b105b 100644 Binary files a/lib/stlinkLinux/bin/FlashLoader/0x495_FUS_Operator.bin and b/lib/stlinkLinux/bin/FlashLoader/0x495_FUS_Operator.bin differ diff --git a/lib/stlinkLinux/bin/STM32_Programmer_CLI b/lib/stlinkLinux/bin/STM32_Programmer_CLI index 79caf0f4..423ad345 100644 Binary files a/lib/stlinkLinux/bin/STM32_Programmer_CLI and b/lib/stlinkLinux/bin/STM32_Programmer_CLI differ diff --git a/lib/stlinkLinux/bin/version b/lib/stlinkLinux/bin/version index 6533b668..f3ac133c 100644 --- a/lib/stlinkLinux/bin/version +++ b/lib/stlinkLinux/bin/version @@ -1 +1 @@ -2.8.0 \ No newline at end of file +2.9.0 \ No newline at end of file diff --git a/lib/stlinkLinux/lib/libCubeProgrammer_API.so b/lib/stlinkLinux/lib/libCubeProgrammer_API.so index bf57c145..0c2b7e95 100644 Binary files a/lib/stlinkLinux/lib/libCubeProgrammer_API.so and b/lib/stlinkLinux/lib/libCubeProgrammer_API.so differ diff --git a/lib/stlinkLinux/lib/libCubeProgrammer_API.so.1 b/lib/stlinkLinux/lib/libCubeProgrammer_API.so.1 index bf57c145..0c2b7e95 100644 Binary files a/lib/stlinkLinux/lib/libCubeProgrammer_API.so.1 and b/lib/stlinkLinux/lib/libCubeProgrammer_API.so.1 differ diff --git a/lib/stlinkLinux/lib/libQt5Core.so.5 b/lib/stlinkLinux/lib/libQt5Core.so.5 index f02bb9c2..4563d6df 100644 Binary files a/lib/stlinkLinux/lib/libQt5Core.so.5 and b/lib/stlinkLinux/lib/libQt5Core.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5DBus.so.5 b/lib/stlinkLinux/lib/libQt5DBus.so.5 index ddb34f00..e2e7f7fc 100644 Binary files a/lib/stlinkLinux/lib/libQt5DBus.so.5 and b/lib/stlinkLinux/lib/libQt5DBus.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5Gui.so.5 b/lib/stlinkLinux/lib/libQt5Gui.so.5 index f08f767b..2c18055a 100644 Binary files a/lib/stlinkLinux/lib/libQt5Gui.so.5 and b/lib/stlinkLinux/lib/libQt5Gui.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5Network.so.5 b/lib/stlinkLinux/lib/libQt5Network.so.5 new file mode 100644 index 00000000..083402fa Binary files /dev/null and b/lib/stlinkLinux/lib/libQt5Network.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5SerialPort.so.5 b/lib/stlinkLinux/lib/libQt5SerialPort.so.5 index 4b6d80c5..8751a17d 100644 Binary files a/lib/stlinkLinux/lib/libQt5SerialPort.so.5 and b/lib/stlinkLinux/lib/libQt5SerialPort.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5Widgets.so.5 b/lib/stlinkLinux/lib/libQt5Widgets.so.5 index ca4cb3e9..f51c86bb 100644 Binary files a/lib/stlinkLinux/lib/libQt5Widgets.so.5 and b/lib/stlinkLinux/lib/libQt5Widgets.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5XcbQpa.so.5 b/lib/stlinkLinux/lib/libQt5XcbQpa.so.5 index f1db9a40..c4584967 100644 Binary files a/lib/stlinkLinux/lib/libQt5XcbQpa.so.5 and b/lib/stlinkLinux/lib/libQt5XcbQpa.so.5 differ diff --git a/lib/stlinkLinux/lib/libQt5Xml.so.5 b/lib/stlinkLinux/lib/libQt5Xml.so.5 index 01f1a931..5f9109de 100644 Binary files a/lib/stlinkLinux/lib/libQt5Xml.so.5 and b/lib/stlinkLinux/lib/libQt5Xml.so.5 differ diff --git a/lib/stlinkLinux/lib/libcrypto.so b/lib/stlinkLinux/lib/libcrypto.so new file mode 100644 index 00000000..eab670c3 Binary files /dev/null and b/lib/stlinkLinux/lib/libcrypto.so differ diff --git a/lib/stlinkLinux/lib/libcrypto.so.1.0.0 b/lib/stlinkLinux/lib/libcrypto.so.1.0.0 index eab670c3..61082dae 100644 Binary files a/lib/stlinkLinux/lib/libcrypto.so.1.0.0 and b/lib/stlinkLinux/lib/libcrypto.so.1.0.0 differ diff --git a/lib/stlinkLinux/lib/libssl.so b/lib/stlinkLinux/lib/libssl.so new file mode 100644 index 00000000..c3f24b8c Binary files /dev/null and b/lib/stlinkLinux/lib/libssl.so differ diff --git a/lib/stlinkLinux/lib/libstp11_SAM.so.conf b/lib/stlinkLinux/lib/libstp11_SAM.so.conf index 68280ac3..d80d6ad5 100644 --- a/lib/stlinkLinux/lib/libstp11_SAM.so.conf +++ b/lib/stlinkLinux/lib/libstp11_SAM.so.conf @@ -1,6 +1,6 @@ [Global] OutputFolder=/home/laurent/.STM32CubeProgrammer/HSM/data/ -InputFolder=/home/laurent/.STM32CubeProgrammer/HSM/data/ +InputFolder=HSM/data/ [Info] IC.Label=Selenite diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x415.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x415.xml index 6c667ba6..46999e7e 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x415.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x415.xml @@ -60,13 +60,13 @@ - + - + @@ -100,8 +100,10 @@ 0xFF RWE + + - + Dual diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x419.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x419.xml index c2ceb99b..92bc1ae4 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x419.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x419.xml @@ -101,6 +101,7 @@ 0xFF RWE + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x425.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x425.xml index 3ac1f747..5ec6a4f9 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x425.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x425.xml @@ -65,6 +65,7 @@ 0x00 RWE + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x427.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x427.xml index 94733176..8f8c1ee5 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x427.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x427.xml @@ -141,7 +141,7 @@ Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 - R + RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection @@ -161,7 +161,7 @@ Sector protection mode selection option byte. 0x8 0x1 - R + RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection @@ -180,7 +180,7 @@ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 - R + RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V @@ -210,7 +210,7 @@ 0x14 0x1 - R + RW Hardware independant watchdog Software independant watchdog @@ -221,7 +221,7 @@ 0x15 0x1 - R + RW Reset generated when entering Stop mode No reset generated @@ -232,7 +232,7 @@ 0x16 0x1 - R + RW Reset generated when entering Standby mode No reset generated @@ -251,7 +251,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -262,7 +262,7 @@ 0x0 0x20 - R + RW read/Write protection active read/Write protection not active @@ -278,7 +278,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -289,231 +289,7 @@ 0x0 0x20 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP32 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - WRP48 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP48 - - 0x0 - 0x10 - W + RW read/Write protection active read/Write protection not active diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x429.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x429.xml index 4a11fef4..c8bdc84c 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x429.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x429.xml @@ -141,7 +141,7 @@ Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 - R + RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection @@ -161,7 +161,7 @@ Sector protection mode selection option byte. 0x8 0x1 - R + RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection @@ -180,7 +180,7 @@ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 - R + RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V @@ -210,7 +210,7 @@ 0x14 0x1 - R + RW Hardware independant watchdog Software independant watchdog @@ -221,7 +221,7 @@ 0x15 0x1 - R + RW Reset generated when entering Stop mode No reset generated @@ -232,7 +232,7 @@ 0x16 0x1 - R + RW Reset generated when entering Standby mode No reset generated @@ -251,7 +251,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -262,7 +262,7 @@ 0x0 0x20 - R + RW read/Write protection active read/Write protection not active @@ -272,176 +272,6 @@ - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x436.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x436.xml index 0ce44164..8141b0d1 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x436.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x436.xml @@ -42,10 +42,10 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE - + - + Dual 0x4 diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x437.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x437.xml index 3cc4bc09..e8f00736 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x437.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x437.xml @@ -134,7 +134,7 @@ Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 - R + RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection @@ -154,7 +154,7 @@ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 - R + RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V @@ -184,7 +184,7 @@ 0x14 0x1 - R + RW Hardware independant watchdog Software independant watchdog @@ -195,7 +195,7 @@ 0x15 0x1 - R + RW Reset generated when entering Stop mode No reset generated @@ -206,7 +206,7 @@ 0x16 0x1 - R + RW Reset generated when entering Standby mode No reset generated @@ -217,7 +217,7 @@ 0x17 0x1 - R + RW If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 @@ -236,7 +236,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -252,7 +252,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -268,7 +268,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -284,7 +284,7 @@ 0x0 0x20 - R + RW Write protection not active Write protection active @@ -294,111 +294,6 @@ - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x7 - 0x1 - W - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x443.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x443.xml index 61c3f692..fa3f8274 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x443.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x443.xml @@ -44,6 +44,7 @@ 0xFF RWE + @@ -438,9 +439,9 @@ - + FLASH security @@ -844,9 +845,9 @@ - + FLASH security diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x453.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x453.xml index 11762df7..e24b4002 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x453.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x453.xml @@ -4,8 +4,9 @@ 0x453 STMicroelectronics MCU + Cortex-M0+ - STM32C0 BigSpider + STM32C03x STM32C0 ARM 32-bit Cortex-M0+ based device @@ -23,14 +24,14 @@ 0x00 RWE - + - + Single - + @@ -42,7 +43,8 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE - + + @@ -56,7 +58,7 @@ - + OTP Storage @@ -83,11 +85,11 @@ RW - + Read Out Protection - + RDP @@ -96,9 +98,9 @@ 0x8 RW - Level 0, read protection not active - or any value other than 0xAA and 0xCC: Level 1,read protection of memories active - Level 2, chip read protection active + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection @@ -110,12 +112,41 @@ - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + BOR_EN + 0x8 - 0x5 + 0x1 + RW + + Configurable brown out reset disabled, power-on reset defined by POR/PDR levels + Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account + + + + BORR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x9 + 0x2 RW - + + BOR falling level 1 with threshold around 2.1 V + BOR falling level 2 with threshold around 2.3 V + BOR falling level 3 with threshold around 2.6 V + BOR falling level 4 with threshold around 2.9 V + + + + BORF_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0xB + 0x2 + RW + + BOR rising level 1 with threshold around 2.0 V + BOR rising level 2 with threshold around 2.2 V + BOR rising level 3 with threshold around 2.5 V + BOR rising level 4 with threshold around 2.8 V + @@ -123,7 +154,7 @@ User Configuration - + nRST_STOP @@ -148,7 +179,7 @@ - nRST_HDW + nRST_SHDW 0xF 0x1 @@ -202,6 +233,17 @@ Software window watchdog + + HSE_NOT_REMAPPED + + 0x15 + 0x1 + RW + + HSE_NOT_REMAPPED enable + HSE_NOT_REMAPPED disable + + RAM_PARITY_CHECK @@ -209,8 +251,19 @@ 0x1 RW - SRAM2 parity check enable - SRAM2 parity check disable + RAM_PARITY_CHECK enable + RAM_PARITY_CHECK disable + + + + SECURE_MUXING_EN + + 0x17 + 0x1 + RW + + SECURE_MUXING_EN disable + SECURE_MUXING_EN enable @@ -220,8 +273,8 @@ 0x1 RW - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit + BOOT0 pin (legacy mode) + nBOOT0 option bit @@ -234,7 +287,7 @@ Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory - + nBOOT0 @@ -245,29 +298,21 @@ nBOOT0=0 nBOOT0=1 - - - NGPIO_MODE + + + NRST_MODE 0x1B - 0x1 + 0x2 RW - NGPIO_MODE=0 - NOT_GPIO_MODE_ONLY: NGPIO_MODE=1 + Reserved + Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin + GPIO: standard GPIO pad functionality, only internal RESET possible + Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) + - - NRST_MODE - - 0x1C - 0x1 - RW - - NRST_MODE=0 - Reset Input only: NRST_MODE=1 - - IRHEN Internal reset holder enable bit @@ -278,7 +323,7 @@ Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level - + @@ -293,7 +338,7 @@ 0x0 0x6 RW - + @@ -306,7 +351,7 @@ 0x0 0x6 RW - + PCROP_RDP @@ -330,7 +375,7 @@ 0x0 0x6 RW - + @@ -343,10 +388,10 @@ 0x0 0x6 RW - + - + Write Protection @@ -355,11 +400,11 @@ WRP1A_STRT - Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + TStart offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect 0x0 0x4 RW - + WRP1A_END @@ -367,7 +412,7 @@ 0x10 0x4 RW - + @@ -380,7 +425,7 @@ 0x0 0x4 RW - + WRP1B_END @@ -388,16 +433,28 @@ 0x10 0x4 RW - + + + FLASH security + + SEC_SIZE + Securable memory area size + 0x0 + 0x5 + RW + + BOOT_LOCK Used to force boot from user area @@ -409,24 +466,17 @@ Boot forced from Main Flash memory - - SEC_SIZE - Sticky area width( Number of FLASH pages) - 0x0 - 0x5 - RW - - + - - + + Read Out Protection - + RDP @@ -435,9 +485,9 @@ 0x8 RW - Level 0, read protection not active - or any value other than 0xAA and 0xCC: Level 1,read protection of memories active - Level 2, chip read protection active + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection @@ -446,15 +496,46 @@ BOR Level - + - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + BOR_EN + 0x8 - 0x5 + 0x1 + RW + + Configurable brown out reset disabled, power-on reset defined by POR/PDR levels + Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account + + + + + BORR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x9 + 0x2 RW - + + BOR falling level 1 with threshold around 2.1 V + BOR falling level 2 with threshold around 2.3 V + BOR falling level 3 with threshold around 2.6 V + BOR falling level 4 with threshold around 2.9 V + + + + + BORF_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0xB + 0x2 + RW + + BOR rising level 1 with threshold around 2.0 V + BOR rising level 2 with threshold around 2.2 V + BOR rising level 3 with threshold around 2.5 V + BOR rising level 4 with threshold around 2.8 V + @@ -462,7 +543,7 @@ User Configuration - + nRST_STOP @@ -487,7 +568,7 @@ - nRST_HDW + nRST_SHDW 0xF 0x1 @@ -541,6 +622,17 @@ Software window watchdog + + HSE_NOT_REMAPPED + + 0x15 + 0x1 + RW + + HSE_NOT_REMAPPED enable + HSE_NOT_REMAPPED disable + + RAM_PARITY_CHECK @@ -548,8 +640,20 @@ 0x1 RW - SRAM2 parity check enable - SRAM2 parity check disable + RAM_PARITY_CHECK enable + + RAM_PARITY_CHECK disable + + + + SECURE_MUXING_EN + + 0x17 + 0x1 + RW + + SECURE_MUXING_EN disable + SECURE_MUXING_EN enable @@ -559,8 +663,8 @@ 0x1 RW - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit + BOOT0 pin (legacy mode) + nBOOT0 option bit @@ -570,10 +674,13 @@ 0x1 RW + + Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 1, otherwise system memory - + + nBOOT0 @@ -584,29 +691,31 @@ nBOOT0=0 nBOOT0=1 - - - NGPIO_MODE + + + NRST_MODE 0x1B - 0x1 + 0x2 RW - NGPIO_MODE=0 - NOT_GPIO_MODE_ONLY: NGPIO_MODE=1 + Reserved + Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin + GPIO: standard GPIO pad functionality, only internal RESET possible + Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) + - - NRST_MODE - - 0x1C - 0x1 - RW - - NRST_MODE=0 - Reset Input only: NRST_MODE=1 - - + + + + + + + + + + IRHEN Internal reset holder enable bit @@ -617,7 +726,8 @@ Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level - + + @@ -632,12 +742,12 @@ 0x0 0x6 RW - + - + PCROP1A_END @@ -645,7 +755,7 @@ 0x0 0x6 RW - + PCROP_RDP @@ -654,14 +764,14 @@ 0x1 RW - PCROP zone is kept when RDP is decreased; Partial Mass Erase done + PCROP zone is kept when RDP is decreased Partial Mass Erase done PCROP zone is erased when RDP is decreased Full Mass Erase done - - + + PCROP1B_STRT @@ -669,12 +779,12 @@ 0x0 0x6 RW - + - + PCROP1B_END @@ -682,7 +792,7 @@ 0x0 0x6 RW - + @@ -690,36 +800,39 @@ Write Protection - + WRP1A_STRT Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + 0x0 0x4 RW - + WRP1A_END End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. + 0x10 0x4 RW - + - + WRP1B_STRT Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect + 0x0 0x4 RW - + WRP1B_END @@ -727,14 +840,14 @@ 0x10 0x4 RW - + - + - + FLASH security @@ -753,7 +866,7 @@ SEC_SIZE - Sticky area width( Number of FLASH pages) + Securable memory area size 0x0 0x5 RW diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x458.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x458.xml index 0e24985f..f360eb2c 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x458.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x458.xml @@ -82,13 +82,13 @@ RW - + Single 0x4 - + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x460.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x460.xml index 4c5a7a9d..a70f6319 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x460.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x460.xml @@ -65,6 +65,10 @@ 0xFF RWE + + + + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x461.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x461.xml index d86041e9..052a4e90 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x461.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x461.xml @@ -43,6 +43,8 @@ 0xFF RWE + + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x464.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x464.xml index d7bdef5f..d947a3b0 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x464.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x464.xml @@ -43,6 +43,8 @@ 0xFF RWE + + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x466.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x466.xml index 4caeea63..5bee4648 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x466.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x466.xml @@ -347,12 +347,12 @@ - + PCROP Protection - + PCROP1A_STRT Flash Area A PCROP start address 0x0 @@ -389,7 +389,7 @@ - + PCROP1B_STRT Flash Area B PCROP start address 0x0 @@ -402,7 +402,7 @@ - + PCROP1B_END Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 @@ -458,7 +458,7 @@ - + FLASH security @@ -706,7 +706,7 @@ - + PCROP Protection @@ -794,7 +794,7 @@ - + FLASH security diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x468.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x468.xml index 52930f42..0a153c3b 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x468.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x468.xml @@ -103,7 +103,7 @@ RW - + Read Out Protection @@ -395,9 +395,6 @@ - - - Secure Protection @@ -426,7 +423,7 @@ - + Read Out Protection @@ -723,9 +720,6 @@ - - - Secure Protection diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x470.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x470.xml index dc74ca98..7c93abee 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x470.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x470.xml @@ -105,6 +105,8 @@ 0xFF RWE + + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x471.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x471.xml index ae94939f..92121d52 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x471.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x471.xml @@ -105,6 +105,8 @@ 0xFF RWE + + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x474.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x474.xml new file mode 100644 index 00000000..5daff1ea --- /dev/null +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x474.xml @@ -0,0 +1,3628 @@ + + + + 0x474 + STMicroelectronics + MCU + Cortex-M33 + STM32H50x + STM32H5 + ARM 32-bit Cortex-M33 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0xFF + RWE + + + + + Single + + + + + + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0xFF + RWE + + + + + Dual + 0x4 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in standby Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + + + User Configuration 2 + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + R + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + + + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + W + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO2_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Stop mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + + + User Configuration 2 + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + R + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + + + + + + + SRAM1_ECC + ECC in SRAM2 region configuration bit + 0xA + 0x1 + W + + Disabled + Enabled + + + + SRAM1_RST + + 0x9 + 0x1 + W + + Disabled + Enabled + + + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x3 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x3 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + R + + Disabled + Enabled + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress + 0x0 + 0x20 + R + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress. + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + + + + Flash EPOCH + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning + Provisioned + Closed + Locked + Regression + + + + + + + BOR Level + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit + 0x2 + 0x1 + W + disabled + enabled + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + + + + + \ No newline at end of file diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x479.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x479.xml index 74d305ac..755c60e1 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x479.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x479.xml @@ -117,7 +117,7 @@ RW - + Read Out Protection @@ -472,7 +472,7 @@ SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 - 0x8 + 0x9 RW @@ -846,7 +846,7 @@ SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 - 0x8 + 0x9 RW diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x481.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x481.xml index c823ee48..bf1f6f08 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x481.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x481.xml @@ -42,17 +42,21 @@ + + + + @@ -95,7 +99,7 @@ 0xFF RWE - + @@ -160,7 +164,7 @@ The Data EEPROM memory block. It contains user data. 0xFF RWE - + Single @@ -171,7 +175,7 @@ - + Single @@ -281,6 +285,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -315,14 +330,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -490,17 +505,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -787,6 +791,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -821,14 +836,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -1007,17 +1022,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -1461,6 +1465,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneouslyDescription + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -1495,14 +1510,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -1681,17 +1696,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -2153,6 +2157,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -2187,14 +2202,14 @@ - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0xF 0x1 RW - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs + SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs @@ -2362,26 +2377,15 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - Boot Configuration - + - + NSBOOTADD0 Non-secure Boot base address 0 0x7 @@ -2390,11 +2394,11 @@ - + - + NSBOOTADD1 Non-secure Boot base address 1 0x7 @@ -2404,7 +2408,100 @@ + + + + + SECBOOTADD0 + Secure boot base address 0 + 0x7 + 0x19 + RW + + + + + + + + + BOOT_LOCK + The boot is always forced to base address value programmed in SECBOOTADD0 + 0x0 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from base address memory + + + + + + Secure Area 1 + + + + + SECWM1_PSTRT + Start page of first secure area + 0x0 + 0x8 + RW + + + + SECWM1_PSTRT + Start page of first secure area + 0x0 + 0x8 + RW + + + + SECWM1_PEND + End page of first secure area + 0x10 + 0x8 + RW + + + + SECWM1_PEND + End page of first secure area + 0x10 + 0x8 + RW + + + + + + + + + HDP1_PEND + End page of first hide protection area + 0x10 + 0x8 + RW + + + + HDP1EN + Hide protection first area enable + 0x1F + 0x1 + RW + + No HDP area 1 + HDP first area is enabled + + + + + Write Protection 1 @@ -2503,6 +2600,70 @@ + + + Secure Area 2 + + + + + SECWM2_PSTRT + Start page of second secure area + 0x0 + 0x8 + RW + + + + SECWM2_PSTRT + Start page of second secure area + 0x0 + 0x8 + RW + + + + SECWM2_PEND + End page of second secure area + 0x10 + 0x8 + RW + + + + SECWM2_PEND + End page of second secure area + 0x10 + 0x8 + RW + + + + + + + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x8 + RW + + + + HDP2EN + Hide protection second area enable + 0x1F + 0x1 + RW + + No HDP area 2 + HDP second area is enabled + + + + Write Protection 2 @@ -2602,7 +2763,7 @@ - + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x482.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x482.xml index c1ba5900..288c9d95 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x482.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x482.xml @@ -107,7 +107,7 @@ 0xFF RWE - + @@ -172,7 +172,7 @@ The Data EEPROM memory block. It contains user data. 0xFF RWE - + Single @@ -183,7 +183,7 @@ - + Single @@ -245,7 +245,7 @@ RW - + Read Out Protection @@ -293,6 +293,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -502,17 +513,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -799,6 +799,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -1019,17 +1030,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -1492,6 +1492,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -1712,17 +1723,6 @@ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - @@ -2184,6 +2184,17 @@ + + TZEN + Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + nRST_STOP @@ -2349,17 +2360,6 @@ USB power delivery dead-battery disabled/ TDI pull-up activated - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x484.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x484.xml index 937102a4..99573d39 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x484.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x484.xml @@ -56,12 +56,12 @@ - + Single - + @@ -159,7 +159,7 @@ Configuration RW - + @@ -989,9 +989,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 R - + BOOT_LOCK_NS @@ -1010,9 +1010,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 W - + BOOT_LOCK_NS @@ -1075,7 +1075,52 @@ - + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + R + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + R + + + + + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + W + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + W + + + + + Write sector group protection 1 @@ -1107,7 +1152,52 @@ - + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + R + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + R + + + + + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + W + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + W + + + + + Write sector group protection 2 @@ -1433,7 +1523,7 @@ - + @@ -2263,9 +2353,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 R - + BOOT_LOCK_NS @@ -2284,9 +2374,9 @@ BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 - 0x10 + 0x18 W - + BOOT_LOCK_NS @@ -2349,7 +2439,52 @@ - + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + R + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + R + + + + + + + + + SECWM1_STRT + First sector of the secure access only zone in Bank1 + 0x0 + 0x7 + W + + + + SECWM1_END + Last sector of the secure access only zone in Bank1 + 0x10 + 0x7 + W + + + + + Write sector group protection 1 @@ -2381,7 +2516,52 @@ - + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + R + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + R + + + + + + + + + SECWM2_STRT + First sector of the secure access only zone in Bank2 + 0x0 + 0x7 + W + + + + SECWM2_END + Last sector of the secure access only zone in Bank2 + 0x10 + 0x7 + W + + + + + Write sector group protection 2 @@ -2707,6 +2887,1886 @@ + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + R + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + R + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + R + + Disabled + Enabled + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + HUK_PUF + This bit configures the nature and use of the unique key + 0xF + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + USBPD_DB_DIS + USB power delivery configuration option bit + 0x8 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_PAR + Parity in SRAM2 region configuration bit + 0x7 + 0x1 + W + + The key is treated as HUK + The key is treated as PUF + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + Disabled + Enabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + Disabled + Enabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + Disabled + Enabled + + + + SRAM2_RST + + 0x3 + 0x1 + W + + Disabled + Enabled + + + + SRAM1_3_RST + + 0x2 + 0x1 + W + + Disabled + Enabled + + + + + + + + + + Boot Configuration + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + R + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + R + + + + + + + + + BOOT_ADDR_NS + Unique Boot Entry Secure Address + 0x8 + 0x18 + W + + + + BOOT_LOCK_NS + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings + 0x0 + 0x8 + W + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress + 0x0 + 0x20 + R + + + + + + + + + BOOT_LOCK_SEC + A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP and BOOT_ADDR_SEC can still be modified following their individual rules. + The BOOT_UBE and BOOT_ADDR_SEC are frozen. SWAP can only be modified with TZEN set to 0xC3 (disabled). + + + + BOOT_ADDR_SEC + Unique Boot Entry Secure Adress. + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x20 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_1 + DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + + + + Flash data sectors + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + DATA_EN_2 + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + DATA_SECTOR_START_2 + DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + + + + Flash EPOCH + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + NS_EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + SEC_EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + ST-VIRGIN + ST-OPEN + ST-SFI-READY + ST-ROT-READY + OEM-provisioning + OEM-provisioned + TZ-OEM-Closed + OEM-Closed + OEM-Locked + OEM-Unconstrained-Debug + OEM-NS-Unconstrained-Debug + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + VDDIO_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x4 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + OEM-iRoT (system flash) selected + ST-iRoT (user flash) selected + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + WWDG_SW + IWDG control mode option status bit. + 0x4 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_SHDWN + Core domain Shutdown entry reset option status bit. + 0x5 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STOP + Core domain DStop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering DStop or DStop2 mode on core domain + no reset generated when entering DStop or DStop2 mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + USB_EN + USB peripheral enable bit + 0xE + 0x1 + R + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + R + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + R + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + R + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + R + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + R + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + R + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + R + + CAN disabled + CAN enabled + + + + + + + + + USB_EN + USB peripheral enable bit. + 0xE + 0x1 + W + + USB communication disabled + USB communication enabled + + + + HASH_EN + HASH SHA IP enable bit. + 0xD + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RNG_EN + random number generator IP enable bit + 0xC + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + PKA_EN + public key cryptography IP enable bit + 0xB + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + AES_EN + + 0xA + 0x1 + W + + HASH feature disabled + HASH feature enabled + + + + RSS_OPT + + 0x7 + 0x3 + W + + + + + + + FLASH_SIZE + + 0x4 + 0x3 + W + + 512kB product + 1MB product + 2MB product + + + + GFX_EN + GFX module option status bit + 0x3 + 0x1 + W + + GFX disabled + GFX enabled + + + + OTFDEC_EN + OTFDEC option status bit. Controls on the fly decryption of external memory + 0x2 + 0x1 + W + + OTFDEC disabled + OTFDEC enbled + + + + SAES_EN + Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage + 0x1 + 0x1 + W + + SAES disabled + SAES enabled + + + + CAN_EN + CAN module control bit + 0x0 + 0x1 + W + + CAN disabled + CAN enabled + + + + + + + diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x485.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x485.xml new file mode 100644 index 00000000..f3b430f6 --- /dev/null +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x485.xml @@ -0,0 +1,760 @@ + + + + 0x485 + STMicroelectronics + MCU + Cortex-M7 + STM32H7Rxx + STM32H7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x20 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Flash Non Volatile State + + + + + FLASH_NVSR + FLASH security status register programming. + 0x0 + 0x8 + R + + OPEN device + CLOSED device + + + + + + + + + FLASH_NVSR + FLASH security status register programming. + 0x0 + 0x8 + W + + OPEN device + CLOSED device + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + R + + BOR OFF + BOR level1: 2.1V + BOR level2: 2.4 V + BOR level3: 2.7 V + + + + + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + W + + reset level is set to 0.0 V + reset level is set to 2.1 V + reset level is set to 2.4 V + reset level is set to 2.7 V + + + + + + + User Configuration1 + + + + + IWDG1_SW + + 0x4 + 0x1 + R + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + R + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + IO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + R + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + R + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + OCTO1_HSLV + + 0x8 + 0x1 + R + + I/O Octo1 High-Speed option disabled + I/O Octo1 High-Speed option enabled + + + + OCTO2_HSLV + + 0x9 + 0x1 + R + + I/O Octo2 High-Speed option disabled + I/O Octo2 High-Speed option enabled + + + + + + + + + IWDG1_SW + + 0x4 + 0x1 + W + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + W + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + IO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + W + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + W + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + OCTO1_HSLV + + 0x8 + 0x1 + W + + I/O Octo1 High-Speed option disabled + I/O Octo1 High-Speed option enabled + + + + OCTO2_HSLV + + 0x9 + 0x1 + W + + I/O Octo2 High-Speed option disabled + I/O Octo2 High-Speed option enabled + + + + + + + User Configuration 2 + + + + + I2c_NI3C + + 0x9 + 0x1 + R + + I3C is selected + I2C is delected + + + + ECC_ON_SRAM + + 0x8 + 0x1 + R + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + + I2c_NI3C + + 0x9 + 0x1 + W + + I3C is selected + I2C is delected + + + + ECC_ON_SRAM + + 0x8 + 0x1 + W + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + DTCM RAM Protection + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + R + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + W + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + ITCM RAM Protection + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + R + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + W + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + nWRP0 + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + Flash HDP bank + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x9 + R + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x9 + R + + + + + + + + + HDP1_STRT + TIL barrier start set in number of 8kb sectors + 0x0 + 0x9 + W + + + + HDP1_END + TIL barrier end set in number of 8kb sectors + 0x10 + 0x9 + W + + + + + + + + Flash EPOCH + + + + + EPOCH + Non Volatile Non Secure EPOCH counter + 0x0 + 0x18 + R + + + + + + + + + EPOCH + Non Volatile Secure EPOCH counter + 0x0 + 0x18 + W + + + + + + + OTP write protection + + + + + LOCKBL + OTP Lock + 0x0 + 0x10 + R + + + + + + + + + LOCKBL + OTP Lock + 0x0 + 0x10 + W + + + + + + + + FLASH ROT programming + + + + + OEM_PROV + OEM provisioned device + 0x0 + 0x8 + R + + + IROT_SELECT + OEM provisioned device + 0x18 + 0x8 + R + + + DBG_AUTH + Debug authentication method + 0x8 + 0x8 + R + + + + + + + + IROT_SELECT + OEM provisioned device + 0x18 + 0x8 + W + + + DBG_AUTH + Debug authentication method + 0x8 + 0x8 + W + + + OEM_PROV + OEM provisioned device + 0x0 + 0x8 + W + + + + + + + FLASH fixed bank + + + + + NUM_FIXED_SECT + Number of fixed sectors + 0x1 + 0x3 + R + + + + EN_SWAP_BANK + enable swap bank + 0x10 + 0x1 + R + + swap bank disable + swap bank enable + + + + LOCK_FIXED + lock fixed + 0x14 + 0x1 + R + + lock disable + lock enable + + + + + + + + + NUM_FIXED_SECT + Number of fixed sectors + 0x1 + 0x3 + W + + + + EN_SWAP_BANK + enable swap bank + 0x10 + 0x1 + W + + swap bank disable + swap bank enable + + + + LOCK_FIXED + lock fixed + 0x14 + 0x1 + W + + lock disable + lock enable + + + + + + + + + + + + \ No newline at end of file diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x497.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x497.xml index a41e44b8..9664177b 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x497.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x497.xml @@ -10,7 +10,14 @@ ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device - + + + + + + + + @@ -295,7 +302,7 @@ CPU1 CM4 Boot lock enabled - + C2BOOT_LOCK 0x1F @@ -311,7 +318,7 @@ - + IPCCDBA IPCC mailbox data buffer base address 0x0 @@ -459,14 +466,14 @@ - + SFSA This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area. 0x0 0x7 RW - + FSD 0x7 @@ -477,7 +484,7 @@ System and Flash non-secure. This bit can only be accessed when HDPADIS = 0 - + DDS 0xC @@ -488,14 +495,14 @@ CPU2 debug access disabled (when also enabled by C2SWDBGEN) - + HDPSA HDPSA[6:0] contain the start address of the first 2 kB page of the User Flash hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash hide protection area enabled. 0x10 0x7 RW - + HDPAD User Flash hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0 0x17 @@ -507,7 +514,7 @@ - + SUBGHSPISD SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled 0x1F @@ -523,7 +530,7 @@ - + C2OPT 0x1F @@ -534,7 +541,7 @@ SBRV will address Flash memory, from start address 0x0800 0000 + SBRV. - + NBRSD 0x1E @@ -545,14 +552,14 @@ SRAM1 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 - + SNBRSA SNBRSA[4:0] contain the start address of the first 1 kB page of the secure "non-backup" SRAM1 area. To keep the tool working you have to set a value greater or equal to 0xC 0x19 0x5 RW - + BRSD 0x17 @@ -563,14 +570,14 @@ SRAM2 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 - + SBRSA SBRSA[4:0] contain the start address of the first 1 kB page of the secure backup SRAM2 area. To keep the tool working you have to set a value less than 0x15 0x12 0x5 RW - + SBRV SBRV[15:0] contain the word (4B) aligned CPU2 boot reset start address offset within the selected memory area by C2OPT. 0x0 diff --git a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x501.xml b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x501.xml index 2e866a6d..df5f1fcc 100644 --- a/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x501.xml +++ b/lib/stlinkMac/Data_Base/STM32_Prog_DB_0x501.xml @@ -47,11 +47,11 @@ OTP - + - none - none + version + Structure version 0x0 0x20 R @@ -59,1755 +59,1837 @@ - + - TR - set SAFMEM Ring current level, default value = 0b00 - 0x7 - 0x2 - RW - - - PRGWIDTH - SAFMEM Programming Pulse Width, default value = 0b0001 - 0x3 - 0x4 - RW - - - FRC - SAFMEM CLOCK frequency range selection, default value = 0b11 - 0x1 - 0x2 - RW - - - PWRUP - SAFMEM Power up control + Value + BSEC state 0x0 - 0x1 - RW + 0x2 + R - + - BIST2LOCK - 0: BIST2 is not locked, 1: BIST2 is locked. - 0x7 - 0x1 - R - - - BIST1LOCK - 0: BIST1 is not locked, 1: BIST1 is locked. - 0x6 - 0x1 - R - - - PWRON - 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. - 0x5 - 0x1 - R - - - PROGFAIL - 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. - 0x4 - 0x1 - R - - - BUSY - 0: SAFMEM is Idle, 1: SAFMEM operation is on going. - 0x3 - 0x1 - R - - - INVALID - 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. - 0x2 - 0x1 - R - - - FULLDBG - 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. - 0x1 - 0x1 - R + Data + Data + 0x0 + 0x20 + RW - SECURE - 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. - 0x0 - 0x1 + Status + Status + 0x4 + 0x20 R - + - GPLOCK - 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. - 0x4 - 0x1 - RW - - - FENREG - 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. - 0x3 - 0x1 - RW - - - DENREG - 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. - 0x2 - 0x1 + Data + Data + 0x0 + 0x20 RW - OTP - 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - DBGSWENABLE - Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. - 0xA - 0x1 - RW - - - CFGSDISABLE - Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. - 0x9 - 0x1 - RW - - - CP15SDISABLE - Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. - 0x7 - 0x2 - RW - - - SPNIDEN - Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. - 0x6 - 0x1 - RW - - - SPIDEN - Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. - 0x5 - 0x1 - RW - - - HDPEN - Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. - 0x4 - 0x1 - RW - - - DEVICEEN - Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. - 0x3 - 0x1 - RW - - - NIDEN - Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. - 0x2 - 0x1 - RW - - - DBGEN - Debug enable with signal dbgen. 0: Disabled, 1: Enabled. - 0x1 - 0x1 + Data + Data + 0x0 + 0x20 RW - DFTEN - DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - CAN_disable - 0: CAN interface is enabled, 1: CAN interface is disabled. - 0x3 - 0x1 - RW - - - GPU_disable - 0: GPU enabled, 1: GPU disabled. - 0x2 - 0x1 - RW - - - Dual_A7_disable - 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. - 0x1 - 0x1 + Data + Data + 0x0 + 0x20 RW - Crypto_disable - 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - W_R conf - This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM + Data + Data 0x0 - 0x1 + 0x20 RW - - - - - - BSEC_OTP_DISTURBED0 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 + Status + Status + 0x4 0x20 R - + - BSEC_OTP_DISTURBED1 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + Data + Data 0x0 0x20 - R + RW - - - - - - BSEC_OTP_DISTURBED2 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 + Status + Status + 0x4 0x20 R - + - BSEC_OTP_ERROR0 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + Data + Data 0x0 0x20 - R + RW - - - - - - BSEC_OTP_ERROR1 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 + Status + Status + 0x4 0x20 R - + - BSEC_OTP_ERROR2 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + Data + Data 0x0 0x20 - R + RW - - - - - - BSEC_OTP_WRLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_WRLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_WRLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SPLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SPLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SPLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SWLOCK0 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SWLOCK1 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SWLOCK2 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SRLOCK0 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + Data + Data 0x0 0x20 RW - - - - - - BSEC_OTP_SRLOCK1 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - BSEC_OTP_SRLOCK2 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + Data + Data 0x0 0x20 RW - - - - - - CFG0 - These bits determins the OTP mode encoding - 0x0 - 0x7 - RW + Status + Status + 0x4 + 0x20 + R - + - fdis3 - Disable CAN - 0x3 - 0x1 - RW - - - fdis2 - Disable GPU - 0x2 - 0x1 - RW - - - fdis1 - Disable CPU1 - 0x1 - 0x1 + Data + Data + 0x0 + 0x20 RW - fdis0 - Disable Crypto (license export) - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - rma_force - RMA force Bit + Data + Data 0x0 - 0x1 + 0x20 RW - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - CFG3 - These bits determins the BOOT source definition + Data + Data 0x0 0x20 RW - - - - - - CFG4 - These bits determins the BOOT monotonic counter - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - CFG5 - These bits determins the BOOT AFmux configuration + Data + Data 0x0 0x20 RW - - - - - - CFG6 - These bits determins the BOOT AFmux configuration - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - CFG7 - These bits determins the BOOT AFmux configuration + Data + Data 0x0 0x20 RW - - - - - - - CFG8 - BOOT/Device configuration. - 0x2 - 0x1E - RW - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - rma_lock - RMA lock Bit - 0x0 - 0x1 - RW + Status + Status + 0x4 + 0x20 + R - + - CFG9 - These bits determin the device configuration. + Data + Data 0x0 0x20 RW - - - - - - CFG10 - These bits determin the device configuration. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - CFG11 - These bits determin the device configuration. + Data + Data 0x0 0x20 RW - - - - - - CFG12 - These bits determin the device configuration. - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - ID0 - Lot ID on 42bit (11LSB's) - 0x15 - 0xB - RW - - - ID0 - Wafer ID - 0x10 - 0x5 - RW - - - ID0 - Wafer Y coordinates - 0x8 - 0x8 - RW - - - ID0 - Wafer X coordinates + Data + Data 0x0 - 0x8 + 0x20 RW - - - - - - ID1 - Lot ID on 42bit (31MSB's) - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - ID2 - Test program flow T[12],F[12],Q[12] - 0x14 - 0xC - RW - - - ID2 - FT program revision - 0xA - 0xA - RW - - - ID2 - EWS program revision + Data + Data 0x0 - 0xA + 0x20 RW - - - - - - HW0 - Analog TRIM - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW1 - Analog TRIM + Data + Data 0x0 0x20 RW - - - - - - HW2 - Analog TRIM and hardware options - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW3 - Analog TRIM + Data + Data 0x0 0x20 RW - - - - - - HW4 - not used yet - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW5 - memory repair bits + Data + Data 0x0 0x20 RW - - - - - - HW6 - memory repair bits - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - HW7 - reserved + Data + Data 0x0 0x20 RW - - - - - - PKH0 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH1 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - PKH2 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH3 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - PKH4 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH5 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - PKH6 - Public Key Hash - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - PKH7 - Public Key Hash + Data + Data 0x0 0x20 RW - - - - - - XK0 - ST ECDSA Private Key for SSP - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - XK1 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW - - - - - - XK2 - ST ECDSA Private Key for SSP - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - XK3 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW - - - - - - XK4 - ST ECDSA Private Key for SSP - 0x0 + Status + Status + 0x4 0x20 - RW + R - + - XK5 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK6 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK7 - ST ECDSA Private Key for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK8 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK9 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK10 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK11 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK12 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK13 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK14 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK15 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK16 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK17 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK18 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK19 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK20 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK21 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK22 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK23 - ST Public ECDSA Chip Certificate for SSP + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK24 - RMA lock and relock passwords + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK25 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK26 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK27 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK28 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK29 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK30 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK31 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK32 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK33 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK34 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK35 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK36 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK37 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK38 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK39 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK40 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK41 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK42 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK43 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK44 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK45 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK46 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK47 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK48 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK49 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK50 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK51 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK52 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK53 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK54 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK55 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK56 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK57 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK58 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK59 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK60 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK61 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK62 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - XK63 - OEM OTP secret word + Data + Data 0x0 0x20 RW + + Status + Status + 0x4 + 0x20 + R + - + - ECC_USE - SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. - 0x4 - 0x4 - R + Data + Data + 0x0 + 0x20 + RW - SAFMEM_SIZE - SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. - 0x0 - 0x4 + Status + Status + 0x4 + 0x20 R - + - MAJREV - IP Version major revision information. - 0x4 - 0x4 - R + Data + Data + 0x0 + 0x20 + RW - MINREV - IP Version minor revision information. - 0x0 - 0x4 + Status + Status + 0x4 + 0x20 R - + - ID - IP Identification. + Data + Data 0x0 0x20 + RW + + + Status + Status + 0x4 + 0x20 R - + - ID - IP Magic Identification. + Data + Data 0x0 0x20 + RW + + + Status + Status + 0x4 + 0x20 R diff --git a/lib/stlinkMac/bin/FlashLoader/0x427.stldr b/lib/stlinkMac/bin/FlashLoader/0x427.stldr index 06bba015..47e043e1 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x427.stldr and b/lib/stlinkMac/bin/FlashLoader/0x427.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x429.stldr b/lib/stlinkMac/bin/FlashLoader/0x429.stldr index a904e024..0329c00e 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x429.stldr and b/lib/stlinkMac/bin/FlashLoader/0x429.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x437.stldr b/lib/stlinkMac/bin/FlashLoader/0x437.stldr index b275ce06..078c4582 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x437.stldr and b/lib/stlinkMac/bin/FlashLoader/0x437.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x450.stldr b/lib/stlinkMac/bin/FlashLoader/0x450.stldr index c4082698..433d2806 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x450.stldr and b/lib/stlinkMac/bin/FlashLoader/0x450.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x452.stldr b/lib/stlinkMac/bin/FlashLoader/0x452.stldr index 61ea6142..a70473c9 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x452.stldr and b/lib/stlinkMac/bin/FlashLoader/0x452.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x469.stldr b/lib/stlinkMac/bin/FlashLoader/0x469.stldr index 7fa618b0..ac5b678f 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x469.stldr and b/lib/stlinkMac/bin/FlashLoader/0x469.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x470.stldr b/lib/stlinkMac/bin/FlashLoader/0x470.stldr index df5fc456..e88dcdae 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x470.stldr and b/lib/stlinkMac/bin/FlashLoader/0x470.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x471.stldr b/lib/stlinkMac/bin/FlashLoader/0x471.stldr index 758c099e..0fffa316 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x471.stldr and b/lib/stlinkMac/bin/FlashLoader/0x471.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x484.stldr b/lib/stlinkMac/bin/FlashLoader/0x484.stldr index 4ab39b92..4b533ac1 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x484.stldr and b/lib/stlinkMac/bin/FlashLoader/0x484.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x485.stldr b/lib/stlinkMac/bin/FlashLoader/0x485.stldr index 9b1fc959..9a987396 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x485.stldr and b/lib/stlinkMac/bin/FlashLoader/0x485.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x492.stldr b/lib/stlinkMac/bin/FlashLoader/0x492.stldr index 34c10a46..40a9399e 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x492.stldr and b/lib/stlinkMac/bin/FlashLoader/0x492.stldr differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x494_FUS_Operator.bin b/lib/stlinkMac/bin/FlashLoader/0x494_FUS_Operator.bin index 4f57eafa..3698d0b6 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x494_FUS_Operator.bin and b/lib/stlinkMac/bin/FlashLoader/0x494_FUS_Operator.bin differ diff --git a/lib/stlinkMac/bin/FlashLoader/0x495_FUS_Operator.bin b/lib/stlinkMac/bin/FlashLoader/0x495_FUS_Operator.bin index 13afc635..f26b105b 100644 Binary files a/lib/stlinkMac/bin/FlashLoader/0x495_FUS_Operator.bin and b/lib/stlinkMac/bin/FlashLoader/0x495_FUS_Operator.bin differ