{"payload":{"header_redesign_enabled":false,"results":[{"id":"568515662","archived":false,"color":"#adb2cb","followers":1,"has_funding_file":false,"hl_name":"nedaraad/MSc-Synthesis","hl_trunc_description":"Homework and Project for Master Course (Synthesis of Digital Systems)","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":568515662,"name":"MSc-Synthesis","owner_id":63770340,"owner_login":"nedaraad","updated_at":"2022-12-16T21:34:40.443Z","has_issues":true}},"sponsorable":false,"topics":["synthesis","homework-assignments","vhdl-coursework","fpga-programming"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":74,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Anedaraad%252FMSc-Synthesis%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/nedaraad/MSc-Synthesis/star":{"post":"vlQiDUlrGgEumcqTwyTm_4491dO5DkpGraQ5d5szfDtTVx1-IBqIiuwH5uDQZX1mGQbk_3HDrPP7WpQ-h6hSDQ"},"/nedaraad/MSc-Synthesis/unstar":{"post":"0eYOm5UiXUi9LYnWDseHoIOeJFUkaG2g4qTMxy7SPJAoSLs9wVy0kK8SDFHVDXY4tszeT-agISOPFwKKOn50cw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"hyqNXUqlassu4QhUYiHC9j0E62ZMgPQxkqf2LO8QuTzkaQaag_dT2te7R7W9A2Ee2QTrYZw2026zUJ0hQ2g5Fg"}}},"title":"Repository search results"}