Permalink
Browse files

Rip out old codegen macros.

  • Loading branch information...
1 parent fbd97ea commit d9fda9fbd0fb734102c9ba581af84a9034478dce @nelhage committed Nov 28, 2010
Showing with 44 additions and 269 deletions.
  1. +0 −1 .gitignore
  2. +1 −3 Makefile
  3. +41 −211 insts.pl
  4. +2 −54 x86.h
View
@@ -1,4 +1,3 @@
*.o
bemu
-opcodes.h
instructions.h
View
@@ -5,7 +5,7 @@ LDFLAGS=-m32 -pthread
SRCS=bemu.cpp bcpu.cpp bdecode.cpp bt.cpp bclock.cpp bconsole.cpp
ASMSRCS=bt_helper.S
OBJECTS=$(SRCS:.cpp=.o) $(ASMSRCS:.S=.o)
-GEN_H=opcodes.h instructions.h
+GEN_H=instructions.h
HEADERS=$(SRCS:.cpp=.h) $(GEN_H) x86.h
BEMU=bemu
@@ -23,8 +23,6 @@ $(UASM): CXXFLAGS += -w
$(UASM):
uasm: $(UASM)
-opcodes.h: insts.pl
- perl insts.pl > opcodes.h
instructions.h: insts.pl
perl $< -cxx > $@
View
252 insts.pl
@@ -29,222 +29,52 @@
***********************************************************************/
END_WARNING
-if (($ARGV[0]||"") eq "-cxx") {
- sub line {
- printf ' typedef %-17s %s;'."\n", $_[0], $_[1];
- }
- sub no_opcode {
- line('no_opcode', $_[0]);
- }
- sub has_opcode {
- line((sprintf 'has_opcode<0x%x>', $_[0]), $_[1]);
- }
- sub one {
- my $name = shift;
- my $opc = shift;
- if ($opc) {
- has_opcode($opc, "op_$name");
- } else {
- no_opcode("op_$name");
- }
- }
- sub pair {
- my $name = shift;
- my $opc = shift;
- if ($opc) {
- has_opcode($opc->[0], "op_$name");
- has_opcode($opc->[1], "subop_$name");
- } else {
- no_opcode("op_$name");
- no_opcode("subop_$name");
- }
- }
- sub begin {
- print "struct X86" . ucfirst(shift) . " {\n";
- }
- sub end {
- print "};\n\n";
- }
- while (my ($mnm, $opc) = each %arith) {
- begin($mnm);
- one("imm_r", shift @$opc);
- pair("imm_rm", shift @$opc);
- one("r_rm", shift @$opc);
- one("rm_r", shift @$opc);
- end();
- }
- while (my ($mnm, $opc) = each %shifts) {
- begin(uc $mnm);
- pair("cl", shift @$opc);
- pair("imm", shift @$opc);
- end();
- }
- exit 0;
+sub line {
+ printf ' typedef %-17s %s;'."\n", $_[0], $_[1];
}
-
-while (my ($mnm, $opc) = each %arith) {
- header(uc $mnm);
-
- my $imm_r = shift @$opc;
- if(defined $imm_r) {
- opcode($mnm, "imm32", "r32", ["dst"] => sub {
- byte(h($imm_r) . "+dst");
- });
- }
-
- my $imm_rm = shift @$opc;
- if(defined $imm_rm) {
- my ($base, $ext) = @$imm_rm;
- opcode($mnm, "imm32", "rm32", [qw(mod reg)] => sub {
- byte(h $base);
- modrm('mod', h $ext, 'reg');
- });
- }
-
- my $r_rm = shift @$opc;
- if(defined $r_rm) {
- opcode($mnm, "r32", "rm32", [qw(src mod reg)] => sub {
- byte(h $r_rm);
- modrm('mod', 'src', 'reg');
- });
- }
- my $rm_r = shift @$opc;
- if(defined $rm_r) {
- opcode($mnm, "rm32", "r32", [qw(mod reg dst)] => sub {
- byte(h $rm_r);
- modrm('mod', 'dst', 'reg');
- });
- }
+sub no_opcode {
+ line('no_opcode', $_[0]);
}
-
-while(my ($mnm, $spec) = each %shifts) {
- my $cl = shift @$spec;
- my ($opc, $reg) = @$cl;
- opcode($mnm, 'cl', 'rm32', [qw(mod reg)] => sub {
- byte(h $opc);
- modrm('mod', $reg, 'reg');
- });
- my $imm = shift @$spec;
- ($opc, $reg) = @$imm;
- opcode($mnm, 'imm8', 'rm32', [qw(mod reg)] => sub {
- byte(h $opc);
- modrm('mod', $reg, 'reg');
- });
+sub has_opcode {
+ line((sprintf 'has_opcode<0x%x>', $_[0]), $_[1]);
}
-
-header ('imul');
-
-opcode('imul', 'rm32', 'r32', [qw(mod reg dst)] => sub {
- byte(h 0x0f);
- byte(h 0xaf);
- modrm('mod', 'dst', 'reg');
- });
-
-opcode('imul', 'imm32', 'rm32', 'r32', [qw(mod reg dst)] => sub {
- byte(h 0x69);
- modrm('mod', 'dst', 'reg');
- });
-
-header ('idiv');
-
-opcode('idiv', 'rm32', [qw(mod reg)] => sub {
- byte(h 0xf7);
- modrm('mod', h 0x7, 'reg');
- });
-
-header ('cdq');
-
-opcode('cdq', [] => sub {
- byte(h 0x99);
- });
-
-header ('call');
-
-opcode('call', 'rel32', [], sub {
- byte(h 0xe8);
- });
-opcode('call', 'indir', 'rm32', [qw(mod reg)] => sub {
- byte(h 0xff);
- modrm('mod', h 0x2, 'reg');
- });
-
-header ('jmp');
-
-opcode('jmp', 'rel8', [], sub {
- byte(h 0xEB);
- });
-opcode('jmp', 'rel32', [], sub {
- byte(h 0xE9);
- });
-opcode('jmp', 'indir', 'rm32', [qw(mod reg)] => sub {
- byte(h 0xff);
- modrm('mod', h 0x4, 'reg');
- });
-
-header ('jcc');
-
-opcode('jcc', 'rel8', ['cc'] => sub {
- byte('0x70 | (cc)');
- });
-opcode('jcc', 'rel32', ['cc'] => sub {
- byte(h 0x0F);
- byte('0x80 | (cc)');
- });
-
-header ('cmov');
-
-opcode ('cmov', 'rm32', 'r32', [qw(cc mod reg dst)] => sub {
- byte(h 0x0f);
- byte('0x40 | (cc)');
- modrm('mod', 'dst', 'reg');
- });
-
-header ('setcc');
-
-opcode ('setcc', 'rm8', [qw(cc mod reg)] => sub {
- byte(h 0x0f);
- byte('0x90 | (cc)');
- modrm('mod', 0, 'reg');
- });
-
-# Start helper routines
-
-our @LINES;
-
-sub header {
- print "/* " . uc $_[0] . " */\n\n";
+sub one {
+ my $name = shift;
+ my $opc = shift;
+ if ($opc) {
+ has_opcode($opc, "op_$name");
+ } else {
+ no_opcode("op_$name");
+ }
}
-
-sub opcode {
- my $mnm = shift;
- my @asmargs = ("x86", "$mnm");
- my ($arg, $margs, $sub);
- while(!ref($arg = shift)) {
- push @asmargs, $arg;
+sub pair {
+ my $name = shift;
+ my $opc = shift;
+ if ($opc) {
+ has_opcode($opc->[0], "op_$name");
+ has_opcode($opc->[1], "subop_$name");
+ } else {
+ no_opcode("op_$name");
+ no_opcode("subop_$name");
}
- $margs = $arg;
- $sub = shift;
- {
- local @LINES = ();
- $sub->();
- unshift @LINES, ("#define " .
- join("_", map {uc} @asmargs) .
- "(" . join (",", 'buf', @$margs) . ")") . " {";
- push @LINES, ' ' x 8 . '}';
- my $mlen = max map{length} @LINES;
- my $macro = join("\\\n",
- map{$_ . (" " x ($mlen + 2 - length $_)) } @LINES);
- $macro =~ s/\s*$//;
- print "$macro\n\n";
- }
}
-
-sub byte {
- my $byte = shift;
- push @LINES, " " x 8 . "X86_BYTE(buf, $byte);";
+sub begin {
+ print "struct X86" . ucfirst(shift) . " {\n";
}
-
-sub modrm {
- my ($mod, $regop, $rm) = @_;
- byte("MODRM($mod, $regop, $rm)");
+sub end {
+ print "};\n\n";
+}
+while (my ($mnm, $opc) = each %arith) {
+ begin($mnm);
+ one("imm_r", shift @$opc);
+ pair("imm_rm", shift @$opc);
+ one("r_rm", shift @$opc);
+ one("rm_r", shift @$opc);
+ end();
+}
+while (my ($mnm, $opc) = each %shifts) {
+ begin(uc $mnm);
+ pair("cl", shift @$opc);
+ pair("imm", shift @$opc);
+ end();
}
View
56 x86.h
@@ -4,28 +4,6 @@
/* compiled code buffer */
typedef uint8_t* ccbuff;
-#define MODRM(mod, regop, rm) ({ \
- uint8_t _mod=(mod), _regop=(regop), _rm=(rm); \
- ASSERT(!(_mod & (~0x3))); \
- ASSERT(!(_regop & (~0x7))); \
- ASSERT(!(_rm & (~0x7))); \
- (_mod << 6)|(_regop << 3)|(_rm); \
-})
-
-/* Cheat because the encoding is the same... */
-#define SIB(scale, index, base) MODRM(scale, index, base)
-
-typedef enum {
- X86_EAX = 0x00,
- X86_ECX = 0x01,
- X86_EDX = 0x02,
- X86_EBX = 0x03,
- X86_ESP = 0x04,
- X86_EBP = 0x05,
- X86_ESI = 0x06,
- X86_EDI = 0x07,
-} x86_reg;
-
#define PREFIX_LOCK 0xF0
#define PREFIX_REPNZ 0xF2
#define PREFIX_REPZ 0xF3
@@ -78,42 +56,12 @@ typedef uint8_t cc_t;
* byte follows (with mod != 3)
*/
-#define REG_SIB X86_ESP
+#define REG_SIB X86ESP.val
/*
* With mod = 0, this specifies a 32-bit displacement
*/
-#define REG_DISP32 X86_EBP
-
-#define X86_BYTE(cc, b) (cc)->byte(b)
-
-#define X86_4BYTE(cc, val) (cc)->word(val)
-
-/* For readability */
-#define X86_IMM32 X86_4BYTE
-#define X86_DISP32 X86_4BYTE
-#define X86_IMM8 X86_BYTE
-#define X86_DISP8 X86_BYTE
-#define X86_REL32(cc, label) (cc)->rel32((uint32_t)label)
-
-#define X86_SIB(ptr, scale, index, base) ({ \
- X86_BYTE(ptr, SIB(scale, index, base)); \
- })
-
-#define X86_INC_RM32(ptr, mod, rm) ({ \
- X86_BYTE(ptr, 0xff); \
- X86_BYTE(ptr, MODRM(mod, 0, rm)); \
- })
-
-/*
- * We use the AT&T convention of SRC_DST.
- *
- * These macros output only the opcode and a ModR/M byte; It is the
- * caller's responsibility to follow them with SIB, displacement, and
- * immediate value if appropriate.
- */
-
-#include "opcodes.h"
+#define REG_DISP32 X86EBP.val
/* Begin C++ */

0 comments on commit d9fda9f

Please sign in to comment.