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Copyright © sistenix.com 2016
Authors: Nelson Campos (nelson@sistenix.com) and Plateny Ponchet (plateny@gmail.com)
You can use, modify and redistribute this codes but please credit the authors.

sv_math

  • reusable math modules (multiplication, division, square root and logarithm) in SystemVerilog

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Reusable math modules (multiplication, division, square root and logarithm) in SystemVerilog

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